KR100408345B1 - A Transflective LCD and method for fabricating thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a reflective liquid crystal display device including a polysilicon thin film transistor.

Conventionally, among the semi-transmissive electrodes of the reflective liquid crystal display device, an electrode in primary contact with a drain electrode is used as a transparent electrode, and a reflective electrode partially in contact with the transparent electrode with an inorganic insulating layer interposed therebetween. Configured.

As described above, when the reflective electrode is patterned, galvanic corrosion occurs between the reflective electrode and the transmissive electrode by etching liquid penetrating into the plurality of pinholes formed in the inorganic insulating layer. A number of mask processes are required, including separately forming contact holes for the transmissive electrodes to contact. Therefore, the yield of a product falls.

The present invention for solving the above problems is formed in a structure in which the reflective electrode is floated on the lower portion of the transmission electrode with a thick organic insulating film interposed therebetween. In this way, the mask process is reduced and galvanic corrosion does not occur between the reflective electrode and the transmissive electrode.

Therefore, there is an advantage that the yield of the product is improved.

Description

Array substrate for reflective transmissive liquid crystal display device and manufacturing method thereof {A Transflective LCD and method for fabricating

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a reflective liquid crystal display device including a polysilicon thin film transistor.

Generally, the transflective liquid crystal display device has the functions of a transmissive liquid crystal display device and a reflective liquid crystal display device, and both a back light and an external natural or artificial light source can be used to limit the surrounding environment. It does not receive, there is an advantage that can reduce the power consumption (power consumption).

Therefore, there is a growing interest in the commercial application of the transflective liquid crystal display device, and researches on this are being actively conducted.

Hereinafter, a structure and a manufacturing method of a typical transmissive liquid crystal display array substrate and a reflective transmissive liquid crystal display array substrate will be described with reference to the drawings.

1 is a plan view showing a part of an array substrate for a general transmissive liquid crystal display device.

As shown, the array substrate 2 has a plurality of gate wirings 6 including a predetermined area of gate pads 4 at one end thereof, and storage wirings 7 formed in parallel thereto, and intersects with the two wirings. A plurality of data lines 10 including a data pad 8 having a predetermined area are formed at one end of the pixel line P and the gate lines 6. A transparent pixel electrode 18 is formed on the pixel region P, and the gate pad terminal 5 and the data pad contact hole 34 contacting the gate pad 4 through the gate pad contact hole 32. The data pad terminal 9 in contact with the data pad 8 through) serves as a means for receiving a signal from the outside.

The thin film transistor T including the gate electrode 12, the source electrode 14, the drain electrode 16, and the active layer 17 is formed at the intersection of the gate wiring 6 and the data wiring 10.

In this case, the thin film transistor T has a coplanar structure in which the gate electrode 12 is formed on the active layer 17, and the active layer 17 is formed of polycrystalline silicon.

The pixel electrode 18 is configured to be in contact with the drain electrode 16 through the drain contact hole 28.

The gate electrode 12 is connected to the gate wiring 6, and the source electrode 14 is connected to the data wiring 10.

Some pixel areas P through which the storage wiring 7 pass are the storage capacitors C.

The storage capacitor is configured in such a manner that an island-shaped metal layer 15 contacting the pixel electrode 18 through the storage contact hole 30 accumulates electric charges along with a part of the storage wiring 7. .

An array substrate for a transmissive liquid crystal display device is constructed with the structure as described above. Hereinafter, a manufacturing process will be briefly described with reference to the cross-sectional view of FIG. 2 (see FIG. 1).

FIG. 2 is a cross-sectional view taken along lines II ′, II-II ′, and III-III ′ of FIG. 1.

As shown in FIG. 2, a buffer layer 20, which is a first insulating film, is formed on the transparent insulating substrate 2, and an island-like semiconductor layer 17 is formed on the buffer layer 20.

The center portion of the semiconductor layer 17 is a first active region 17a functioning as an active channel, and both sides of the semiconductor layer 17 are second active regions 17b and 17c doped with impurities. Is defined as).

Next, a gate insulating film 22 serving as a second insulating film is formed on the semiconductor layer 17.

Next, a conductive metal material is deposited and patterned on the gate insulating layer 22 to form a gate electrode 12 on the semiconductor layer 17 and a gate connected to the gate electrode 12 and extending in one direction. A gate pad 4 having a predetermined area is formed at the end of the wiring 6 and the gate wiring 6.

At the same time, the storage wiring 7 extending in one direction in parallel with the gate wiring 6 is formed.

Next, an insulating material is deposited on the entire surface of the substrate 2 including the gate electrode 12 to form an interlayer insulating film 24 as a third insulating film, and then the interlayer insulating film and the lower gate insulating film are patterned. Portions of the second active regions 17b and 17c are exposed, respectively.

Next, the ohmic contact layers 23a and 23b are formed by doping impurities into the exposed second active regions 17b and 17c.

Source and drain electrodes 14 and 16 contacting the second active regions 17b and 17c by depositing and patterning a conductive metal material on the entire surface of the substrate 2 on which the ohmic contact layers 23a and 23b are formed. And an upper electrode 15 of the storage capacitor, connected to the source electrode 14, extending in one direction, and forming a data line 10 having a data pad 8 having a predetermined area at one end thereof.

Next, a passivation layer 26, which is a fourth insulating layer, is formed on the source and drain electrodes 14 and 16 using a transparent organic insulating material, and then patterned to form the drain electrode 16 and the upper portion of the story capacitor. A portion of the electrode 15, the drain contact hole 28 exposing the gate pad 4 and the data pad 4, the storage contact hole 30, the gate pad contact hole 32, and the data pad contact. The hole 34 is formed.

Next, a transparent conductive metal is deposited and patterned on the fourth insulating layer 26 to form a pixel electrode 18 in contact with the exposed drain electrode 16 and a gate pad in contact with the gate pad 4. A data pad terminal 9 is formed in contact with the terminal 5 and the data pad 8.

In the same manner as described above, the array substrate for a transmissive liquid crystal display device according to the first example can be manufactured.

However, as mentioned above, the transmissive liquid crystal display device has been developed to overcome the power consumption due to the limitation of the light source.

3 is an enlarged plan view showing a part of a conventional array substrate for a transflective liquid crystal display device.

The reflective array substrate 30 is planar, except for the configuration of the pixel electrodes 63 and 72 formed in the pixel region P, and substantially the same structure as that of the transmissive array substrate. That is, the thin film transistor T, which is a switching element, is positioned in a matrix type on the transparent insulating substrate 30, and the gate wiring 41 and the data wiring 54 passing through the plurality of thin film transistors T cross each other. ) Is formed.

The thin film transistor T is a polysilicon thin film transistor in which polysilicon is formed as an active layer, and has a coplanar structure in which the gate electrode 40 is formed under the source electrode 40 and the drain electrode 50.

One end of the gate wiring 41 and the data wiring 54 includes a gate pad 44 and a data pad 56 for receiving a signal from the outside, and each of the pads 44 and 56 is a transparent conductive film. The gate pad terminal 64 and the data pad terminal 66 are formed in contact with each other.

The thin film transistor T includes a gate electrode 40, a source electrode 50, a drain electrode 52, and an active layer 36 formed on the gate electrode 40.

The active layer has an extension 37 extending in a predetermined area on the pixel area.

In the above-described configuration, the storage wiring 42 is formed of the same material as the gate wiring 41, and the storage wiring 42 is configured in one direction via the plurality of pixel areas P.

In the above-described configuration, the storage line 42 includes an extended area 43 extended to have a predetermined area on the pixel area P.

Above the extended region 43 of the storage line 42, a reflective electrode 72 contacting the pixel electrode 63 through a second drain contact hole 48b exposing the transparent pixel electrode 63 is formed. Are stacked.

The pixel electrode 63 is configured to be in contact with the drain electrode 52 through the first drain contact hole 62 exposing the drain electrode 52.

In such a configuration, the storage capacitor C and the reflective part E are simultaneously configured in the pixel area P. FIG.

That is, the extended portion 37 of the active layer and the extended region 43 of the storage interconnection 42 respectively function as first and second capacitor electrodes, and an extended region of the storage interconnection. The second storage capacitor portion 43 and the pixel electrode 63 function as first and second capacitor electrodes, respectively.

In addition, since the reflective plate 72 is formed above the storage capacitor C, it corresponds to the reflective part E of the pixel region P. FIG. Of course, the remaining pixel areas except for the reflective part correspond to the transmissive part (F).

4A and 4F, a brief description will be made of a conventional method of fabricating an array substrate for a reflective transmissive liquid crystal display device. (In the following, reference numerals not shown in the drawings showing the process will be described with reference numerals of FIG. 3). do.)

4A and 4F are cross-sectional views taken along the process sequence of FIG. 3 along the lines IV-IV ′, V-V ′, and VI-VI ′.

First, the drawing illustrated in FIG. 4A is formed by depositing one of a group of inorganic insulating materials composed of a silicon oxide film (SiO ₂ ) and a silicon nitride film (SiN _X ) on a substrate 30 to form a first insulating film 32. The amorphous semiconductor layer 34 is formed by depositing amorphous silicon (a-Si: H) on the first insulating layer 32.

The first insulating layer 32 is also referred to as a buffer layer to prevent diffusion of the alkali material eluted from the inside of the substrate 30 during a later process.

The amorphous silicon layer 34 is crystallized into a polysilicon layer by a predetermined crystallization method.

The crystallization method may be a solid phase crystallization method, a metal induced crystallization method, a crystallization method using a laser, FE-MIC crystallization method and the like.

Thereafter, in the process of FIG. 4B, the polysilicon layer is patterned into an island-shaped semiconductor layer 36, a gate insulating layer 38, which is a second insulating layer, is formed on the semiconductor layer 36, and the conductive metal is successively deposited. do.

The deposited metal film is patterned to form the gate electrode 40 and the gate wiring 41. The semiconductor layer 36 has an extension 37 configured to extend into the pixel region P. As shown in FIG.

(The role of the extension will be explained later in the process.)

A gate pad 44 is formed at one end of the gate wiring 41 to have a predetermined area and receive a signal voltage from the outside.

At the same time, the storage wiring 43 is formed parallel to the gate wiring 41 at a predetermined interval, and the portion of the storage wiring 42 that passes above the pixel region P is extended to a predetermined area ( 43).

The island 36 may be divided into two regions, in which the first active region A is a pure silicon region, and the second active region B is an impurity region. The second active region B is located at both edges of the first active region A. FIG.

In addition, the gate insulating layer 38 and the gate electrode 40 are formed on the first active region A. FIG.

After the gate electrode 40 is formed, ion doping is performed to form an ohmic contact layer in the second active region B. In this case, the gate electrode 40 serves as an ion stopper to prevent the dopant from penetrating into the first active region A. FIG. When the ion doping, the electrical properties of the silicon island 36 is changed according to the type of dopant, and when the dopant is doped with a group 3 element such as B ₂ H ₆ , it is a P-type semiconductor and a group 5 such as PH ₃ . When the element is doped, it acts as an N-type semiconductor. The dopant needs to be appropriately selected according to the use of the semiconductor device. After the ion doping process, the process proceeds to the step of activating the dopant.

Next, as shown in FIG. 4C, an interlayer insulating film, which is a third insulating film, is formed over the entire surface of the gate electrode 40, the second active region B, the first insulating film 32, and the second insulating film 38. The inter layer insulator 46 is deposited and patterned to form source / drain contact holes 48a and 48b in the second active region B, respectively.

Next, aluminum (Al), aluminum alloy, tungsten (W), copper (Cu), chromium (Cr), and molybdenum (Mo) on the substrate 30 on which the source / drain contact holes 48a and 48b are formed. A source electrode and a drain electrode 50 and 52 contacting the left and right impurity regions B through the source / drain contact holes 48a and 48b, respectively, by depositing and patterning a selected one of the conductive metal groups. To form.

At the same time, a data pad 56 is formed in a predetermined area at one end of the data wiring 54 and the data wiring 54 in contact with the source electrode 50.

By this process, the polysilicon thin film transistor T is completed.

Next, as shown in FIG. 4D, after the insulating material is deposited on the entire surface of the substrate 30 including the thin film transistor T to form the fourth insulating layer 58, the thin film transistor proceeds to hydrogenate. In order to proceed the heat treatment process.

The hydrogenation process is for removing defects on the surface of the active layer, and serves to fill the lattice defects generated on the surface of the active channel by hydrogen atoms to improve the conductivity of the surface of the active layer.

After the heat treatment, a fifth insulating film is coated by applying one selected from the group of transparent organic insulating materials including benzocyclobutene and acrylic resin to have a high opening ratio on the fourth insulating film 58. Form 60.

Next, the fifth insulating layer 60 and a part of the plurality of insulating layers below the same are patterned at the same time to expose the first drain contact hole 62 exposing the drain electrode 52 and the gate pad 44. The gate pad contact hole 61 and the data pad contact hole 65 exposing the data pad 56 are formed.

Next, as shown in FIG. 4E, indium-tin-oxide and indium-zinc-oxide are formed on the patterned fifth insulating layer 60. Selected one of the transparent conductive metal group is deposited and patterned to contact the exposed drain electrode 52 and extend on the pixel region P and the exposed gate pad 44. And a gate pad terminal 64 in contact with the data pad and a data pad terminal 66 in contact with the exposed data pad 56.

Next, as shown in FIG. 4F, a sixth insulating film 68 is formed by thinly depositing silicon oxide (SiO ₂ ) and silicon nitride film (SiN _x ) on the entire surface of the substrate 30 on which the pixel electrode 63 is formed. Form.

Next, the sixth insulating layer 58 is patterned to form a second drain condition hole 70 exposing an upper portion of the pixel electrode 62 in contact with the drain electrode 52.

Next, a selected one of a conductive metal group including aluminum (Al) and an aluminum alloy is deposited and patterned on the entire surface of the substrate 30 on which the second drain contact hole 70 is formed, thereby forming an upper portion of the pixel region P. The reflective electrode 72 is formed in a predetermined area and contacts the pixel electrode 62 exposed on the drain electrode 52.

Next, a first etching hole exposing the gate pad terminal electrode 64 and the data pad terminal electrode 66 is patterned again by patterning the sixth insulating layer 68 in which the reflective electrode 72 is patterned and exposed. 74 and the second etching hole 76 are formed.

The last step of exposing the terminal electrodes 64 and 66 may be performed by simultaneously exposing the reflective electrode 72 and the transparent pixel electrode 63 to an etching solution for etching the reflective electrode 72. This is to prevent the case.

If both electrodes are exposed to the etching solution at the same time, galvanic corrosion occurs, causing serious damage to the electrodes.

When the above-described process is completed, the storage region C ₁ + C ₂ including the first storage capacitor C ₁ and the second storage capacitor C ₂ is formed in the pixel area.

In the first storage capacitor part C ₁ , the expansion part 37 of the semiconductor layer and the expansion area 43 of the storage wiring serve as a first capacitor electrode and a second capacitor electrode, respectively. The insulating film 38 interposed therebetween serves as a dielectric material.

At this time, the insulating film is formed to a thickness of about 1500 ~ 2000Å.

Among the above-described configurations of the first storage capacitor, the reason why the extension 37 of the active layer may serve as a capacitor electrode is as follows.

This is because the voltage applied to the pixel electrode 63 through the drain electrode 52 is almost applied to the extension 37 of the active layer formed under the storage wiring.

Since the active layer is composed of a semiconductor layer, when a voltage is not applied, the active layer is in a neutral state. However, when the voltage is applied, electrons and holes in the neutral state are excited to form a channel through which electrons can be moved. .

Thus, the active layer serves as an electrode.

Among the storage capacitors C ₁ + C ₂ , the second storage capacitor C ₂ serves as an expansion region of the storage wiring and the transparent pixel electrode to serve as a first capacitor electrode and a second capacitor electrode. A plurality of insulating layers 46, 58, and 60 positioned between the two electrodes serve as a dielectric.

At this time, the second insulating film layer 46 on the gate electrode of the plurality of insulating film layer is formed to a thickness of about 7000Å, the third insulating film layer located on the source electrode 54 and the drain electrode 52 It is formed with a thickness of about 4000Å, and the protective film layer 60 made of the organic insulating material is formed to a thickness of about 1 to 1.5㎛.

Comparing the charge charging amount of the second storage capacity portion and the second storage capacity portion, the first storage capacity portion shows a much larger capacity value than the second storage capacity portion.

This is because the thinner the dielectric is, the larger the charge filling value is.

In the above-described process, an array substrate for a reflective transmissive liquid crystal display device including the polysilicon thin film transistor according to the related art can be manufactured.

However, conventional transflective array substrates require more manufacturing processes than conventional transmissive array substrates.

That is, to prevent galvanic corrosion between the reflective electrode 72 and the transparent electrodes 63, 64, 66, a sixth insulating layer 68 is deposited, and the reflective electrode 72 and the lower transparent pixel electrode 63 are deposited. The first step of patterning the sixth insulating film 68 to contact the (I), and the pattern to expose the gate pad terminal 64 and the data pad terminal 66 after patterning the reflective electrode 72 The 2nd process of patterning the 6 insulating film 68 is mentioned, for example.

Therefore, there is a problem that the productivity of the product is lowered.

In the conventional transflective array substrate, when a defect such as a pin hole occurs in the sixth insulating layer (thin inorganic layer) 68, the reflective electrode 72 is formed on the lower pixel electrode 63. ) Etching solution can penetrate.

As a result, the above-described galvanic corrosion occurs between the reflective electrode 72 and the pixel electrode 63 by the etching solution, and thus there is a problem that an open defect in which the electrode is corroded occurs.

In order to solve the above problems, the present invention simplifies the process, and enables a structure in which a thick organic insulating film is positioned between the reflective electrode and the transmissive electrode, thereby preventing galvanic corrosion between the two electrodes to produce a product. The purpose is to improve the yield.

1 is a plan view schematically illustrating a part of an array substrate for a general transmissive liquid crystal display device;

2 is a cross-sectional view taken along the line II ′, II-II ′, and III-III ′ of FIG. 1;

3 is a plan view schematically showing a part of a conventional array substrate for a reflective transmissive liquid crystal display device;

4A through 4F are cross-sectional views of the process of cutting through IV-IV`, V-V`, and VI-VI` of FIG.

5 is a cross-sectional view schematically illustrating a portion of an array substrate for a reflective transmissive liquid crystal display device according to the present invention;

6A through 6E are cross-sectional views illustrating the process sequence according to the first exemplary embodiment of the present invention, by cutting the lines of Figs.

7A to 7B are cross-sectional views illustrating the process sequence according to the second embodiment of the present invention, by cutting the lines VIII-VIII, VIII-VIII, VIII-VIII of FIG.

8A to 8B are cross-sectional views illustrating the process sequence according to the third exemplary embodiment of the present invention by cutting the line VIII-VIII, VIII-VIII, VIII-VIII of FIG. 5.

<Description of Symbols for Main Parts of Drawings>

130 substrate 132 first insulating film

138: second insulating film (gate insulating film) 146: third insulating film

148: fourth insulating film 158: fifth insulating film

160: sixth insulating film 162: drain contact hole

163: pixel electrode 164: gate pad

166: data pad 172: reflector

170: gate pad terminal 174: data pad terminal

According to an aspect of the present invention, an array substrate for a reflective transmissive liquid crystal display device includes: a substrate; A thin film transistor formed on the substrate in an order of an active layer, a gate electrode, a drain electrode, and a source electrode; A gate wiring connected to the gate electrode and including a gate pad having a predetermined area at one end thereof, and a storage wiring configured to be parallel to the gate wiring at a predetermined interval; A data line defining a pixel area crossing the gate line and connected to the source electrode and including a source pad having a predetermined area at one end thereof; An extension part extending from the active layer to a pixel area by a predetermined area; A reflector formed on the extension and not in contact with the drain electrode; And a pixel electrode formed on the reflective plate and in contact with the drain electrode.

A buffer layer is further configured below the active layer.

The buffer layer is formed of one selected from the group of inorganic insulating materials consisting of silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ).

The storage wiring is made of the same material as the gate wiring.

The reflector is composed of one selected from the group of metals including aluminum and aluminum alloy having excellent reflectance.

The pixel electrode is made of one selected from a group of transparent conductive metals consisting of indium tin oxide (ITO) and indium zinc oxide (IZO).

According to an aspect of the present invention, there is provided a method of manufacturing an array substrate for a transflective liquid crystal display device, the method comprising: preparing a substrate; Forming a thin film transistor on the substrate in the order of an active layer, a gate electrode, a drain electrode, and a source electrode; Forming a gate wiring connected to the gate electrode and including a gate pad having a predetermined area at one end thereof, and a storage wiring configured to be parallel to the gate wiring at a predetermined interval; Defining a pixel region crossing the gate wiring, and forming a data wiring connected to the source electrode and including a source pad having a predetermined area at one end thereof; An extension part extending from the active layer to a pixel area in a predetermined area; Forming a reflector formed on the extension and not in contact with the drain electrode; And forming a pixel electrode formed on the reflective plate and in contact with the drain electrode.

According to another aspect of the present invention, an array substrate for a transflective liquid crystal display device includes a substrate;

A thin film transistor comprising an active layer, a gate electrode, a drain electrode, and a source electrode, which are reflective plates on the substrate; A gate wiring connected to the gate electrode and including a gate pad having a predetermined area at one end thereof, and a storage wiring configured to be parallel to the gate wiring at a predetermined interval; A data line defining a pixel area crossing the gate line and connected to the source electrode and including a source pad having a predetermined area at one end thereof; An extension part extending from the active layer to a pixel area by a predetermined area; An island-shaped metal layer formed in contact with the storage wiring in a portion of an upper portion of the pixel region with an insulating film interposed therebetween and having an insulating film interposed therebetween; A reflector formed on the metal layer with an insulating film interposed therebetween and not in contact with the drain electrode; And a transparent pixel electrode formed over the reflective plate with an insulating film therebetween and in contact with the drain electrode.

In the above-described configuration, the reflective plate and the pixel electrode may be configured to be in contact with each other.

According to another aspect of the present invention, there is provided a method of manufacturing an array substrate for a transflective liquid crystal display device, the method including: preparing a substrate; Forming a thin film transistor on the substrate in the order of an active layer, a gate electrode, a drain electrode, and a source electrode; Forming a gate wiring connected to the gate electrode and including a gate pad having a predetermined area at one end thereof, and a storage wiring configured to be parallel to the gate wiring at a predetermined interval; Defining a pixel area crossing the gate wiring, and forming a data wiring connected to the source electrode and including a source pad having a predetermined area at one end thereof; Forming an extension extending from the active layer to the pixel area by a predetermined area; Forming an island-shaped metal layer formed in contact with the storage wiring on an upper portion of the storage region passing through the pixel region, and having an insulating layer interposed therebetween; Forming a reflective plate on the metal layer with an insulating film interposed therebetween and not in contact with the drain electrode; And forming a transparent pixel electrode on the reflective plate with an insulating film interposed therebetween and in contact with the drain electrode.

Hereinafter, in the first to third embodiments according to the present invention, the manufacturing process of the present invention having the above-described configuration will be described in detail.

First Embodiment

The present invention is to form a reflector in a state in which a transparent organic insulating film is interposed between the bottom of the transparent electrode (floating).

5 and 6a to 6d will be described a manufacturing process of the array substrate for a reflective transmissive liquid crystal display device according to the present invention.

5 is a plan view schematically illustrating a portion of an array substrate for a reflective transmissive liquid crystal display device according to the present invention.

As shown, unlike the conventional method, the reflective electrode includes a reflective plate 172 that does not contact the drain electrode 152.

Therefore, a separate contact hole process for contacting the reflector and the drain electrode is omitted in comparison with the prior art. (However, since the planar configuration is similar to that of the prior art, the description of most components is omitted. Is added to 100 and is used.) Hereinafter, the manufacturing process for the above-described configuration will be described with reference to FIGS. 6A to 6D.

6A to 6D are cross sectional views taken along the process sequence of FIG. 5 and taken along the process sequence. (Refer to reference numeral of FIG. 5).

First, as shown in FIG. 6A, one selected from the group of inorganic insulating materials including a silicon oxide layer (SiO ₂ ) and a silicon nitride layer (SiN _x ) is deposited on the transparent insulating substrate 130 to form a buffer layer as a first insulating layer. layer 132 is formed.

The buffer layer 132 is not an essential component and may be omitted if necessary.

Next, amorphous silicon (a-Si: H) is deposited on the buffer layer 132 and crystallized by a predetermined method to form a polysilicon layer 134.

Next, as shown in FIG. 6B, the polysilicon layer is patterned to form an island-shaped semiconductor layer 136. At the same time, an extension portion 137 extending from the semiconductor layer onto the pixel region (P in Fig. 5) is formed.

The semiconductor layer 134 is defined as a first active region A serving as an active channel and a second active region B doped with impurities.

The gate insulating layer 138 as the second insulating layer is formed by depositing one selected from the group of inorganic insulating materials including a silicon nitride layer (SiN _x ) and a silicon oxide layer (SiO ₂ ) on the substrate 130 on which the semiconductor layer 104 is formed. To form.

Next, a conductive metal is deposited and patterned on the semiconductor layer 136 to be connected to the gate electrode 140 and the gate electrode 140 on the first active region A in one direction. The gate wiring 141 is formed and a gate pad 144 formed at a predetermined area at one end of the gate wiring is formed.

At the same time, the storage wiring 142 is formed in parallel with the gate wiring 141 at predetermined intervals, and a portion of the storage wiring 142 that passes above the pixel area P is extended to a predetermined area ( 143).

Next, as shown in FIG. 6C, an insulating material is deposited on the entire surface of the substrate 130 on which the gate electrode 140 and the like are formed to form an interlayer insulating film 146, which is a third insulating film 146, and then patterned. The first contact hole and the second contact hole 148a and 148b exposing the semiconductor layer defined as the second active region B are exposed.

Next, a conductive metal group including aluminum (Al), aluminum alloy, chromium (Cr), tungsten (W), molybdenum (Mo), and neobium (Nb) on the third insulating layer 146 is selected. One is deposited and patterned to form a source electrode 150 contacting the exposed second active region B and a drain electrode 152 spaced apart from the source electrode 150.

At the same time, a data line 154 connected to the source electrode 150 extends in one direction and includes a data pad 156 having a predetermined area at one end thereof.

The data line 154 crosses the gate line 141 to define a pixel area P.

Polysilicon thin film transistor (T) is configured through the above process.

Next, as shown in FIG. 6D, an insulating material is deposited on the thin film transistor T to form a fourth insulating film 158, and then hydrogenation of the TFT is performed.

Next, a selected one of a conductive metal group such as aluminum (Al) and an aluminum alloy having excellent reflectance is deposited on the fourth insulating layer 158 and patterned to form a reflecting plate 172 on the pixel region P. do.

The reflective plate 172 is configured to overlap the expansion area 143 of the storage wiring 142 in a plane.

Next, one selected from the group of transparent organic insulating materials including benzocyclobutene and acryl-based resin is deposited and patterned on the entire surface of the substrate 130 on which the reflective plate 172 is formed. 5 An insulating film 160 is formed.

Next, the gate pad 144 is formed in a portion corresponding to the drain contact hole 162 exposing the drain electrode 152 by patterning the fifth insulating layer 160 and the first contact hole of the gate pad 144. ) And a gate pad contact hole 166 exposing () and a data pad contact hole 166 exposing the data pad 156.

Next, as shown in FIG. 6E, a transparent conductive metal including indium-tin-oxide and indium-zinc-oxide on the fifth insulating layer 160. A selected one of the group is deposited and patterned to be in contact with the exposed drain electrode 152, and the pixel electrode 163 formed on the pixel region P and the gate pad terminal 170 in contact with the gate pad 164. ) And a day pad terminal 166 in contact with the data pad 156.

In the above-described configuration, the extended portion 137 of the active layer and the extended region 143 of the storage wiring function as the second capacitor electrode to form the first storage capacitor C ₁ , and the storage The extension region 143 of the wiring and the pixel electrode 163 function as the first and second capacitor electrodes, respectively, to form the second storage capacitor C ₂ .

As described above, an array substrate for a reflective transmissive liquid crystal display device including the polysilicon thin film transistor according to the present invention can be manufactured.

In the above-described process, since the array substrate structure according to the present invention is a structure in which a reflecting plate is formed below the transparent electrode, it is not necessary to form a sixth insulating layer as compared with the conventional art. Accordingly, a separate contact hole for contacting the transparent electrode and the reflective electrode are not formed, and then a process for separately exposing the gate pad terminal and the data pad terminal is not necessary.

Accordingly, there is an advantage in that two mask processes can be reduced as compared to the process of the conventional array substrate for reflection type liquid crystal display device.

Hereinafter, the second embodiment has a structure in which the storage capacity of the storage capacity portion is larger than that of the first embodiment.

Example 2--

Hereinafter, a second embodiment of the present invention will be described with reference to the cross-sectional views of FIGS. 7A to 7B. (It is the same in plan except that the storage contact hole is added on the pixel area. do.)

7A to 7B are cross-sectional views taken along the lines VII-VII, VII-VII and VII-VII of FIG. 5.

The second embodiment of the present invention is characterized in that an island-shaped metal layer is formed on the expansion region 143 of the storage wiring 142 and is in contact with the expansion region 143 through a contact hole.

Example 2 according to the present invention is the same as the process of Example 1, some processes will be described to simplify the drawings to explain the process.

As shown in FIG. 7A, after depositing the inorganic insulating material as described above on the transparent insulating substrate 130, a buffer layer 132 serving as the first insulating layer is formed.

Next, after depositing amorphous silicon (a-Si: H) on the buffer layer 132, a polysilicon layer crystallized by a predetermined method is patterned to form an island-shaped semiconductor layer 136 and a pixel in the semiconductor layer. The extension part 137 extended on the area | region (P of FIG. 5) is comprised.

The semiconductor layer 136 is defined as a first active region A serving as an active channel and a second active region B doped with impurities.

A gate insulating layer 138 which is a second insulating layer is formed on the substrate 130 on which the semiconductor layer 136 is formed.

Next, a gate electrode 140 is formed on the first active region A, a gate wiring 141 connected to the gate electrode 140 in one direction, and a predetermined area at one end of the gate wiring. The formed gate pad 144 is formed.

At the same time, the storage wiring 142 is formed parallel to the gate wiring 141 by a predetermined distance, and the portion of the storage wiring 142 that passes above the pixel area P is extended to a predetermined area ( 143).

An insulating material is deposited on the entire surface of the substrate 130 on which the gate electrode 140 and the like are formed to form an interlayer insulating film 146, which is a third insulating film 146, and then patterned to define the second active region B. The first contact hole and the second contact hole 148a and 148b exposing the semiconductor layer and the third contact hole 154 exposing the extension region 143 of the storage wiring are formed.

Next, a selected one of conductive metal groups including aluminum (Al), aluminum alloy, chromium (Cr), tungsten (W), molybdenum (Mo), and neodymium (AlNd) is deposited on the third insulating layer 146. And a pattern, contacting the source electrode 150 in contact with the exposed second active region B, the drain electrode 152 spaced apart from the predetermined interval, and the extension region 143 of the exposed storage wiring 142. An island-shaped source / drain metal layer 157 is formed.

At the same time, a data line 154 connected to the source electrode 150 extends in one direction and includes a data pad 156 having a predetermined area at one end thereof.

Through the process as described above, the polysilicon thin film transistor T and the first storage electrode 157 of the storage capacitor C are configured.

Next, as illustrated in FIG. 7B, an insulating material is deposited on the thin film transistor T to form a fourth insulating layer 160, and then hydrogenation of the TFT is performed.

Next, one selected from a group of conductive metals such as aluminum (Al) and an aluminum alloy having excellent reflectance is deposited on the fourth insulating layer 160 and patterned to form a reflective plate 172 on the pixel region P. do.

The reflective plate 172 is configured to overlap the first storage electrode 157 in plan view.

Next, one selected from the group of transparent organic insulating materials including benzocyclobutene and acryl-based resin is deposited and patterned on the entire surface of the substrate 130 on which the reflective plate 172 is formed. 5 An insulating film 160 is formed.

Next, the fifth insulating layer 160 is patterned to partially expose the drain electrode 152, the gate pad 144, and the data pad 156.

Next, the pixel electrode 163 formed on the pixel region P and the gate pad terminal contacting the gate pad 144 while contacting the drain electrode 152 using the transparent conductive metal material as described above. A data pad terminal 176 is formed to contact 170 and the data pad 156.

In the above-described configuration, a first storage capacitor C ₁ , in which the extended portion 143 of the active layer and the extended region 143 of the storage wiring functions as a first and second capacitor electrode, is formed. A second storage capacitor C ₂ is formed in which the extension region 143 and the source / drain metal layer 172 function as first and second capacitor electrodes, respectively.

As described above, the fabrication process of the second embodiment of the present invention has no additional process compared with the fabrication achievement of the first embodiment. In addition, the insulating film 146 between the two electrodes 157 and 163 exists compared with the first embodiment. Since the structure is omitted, there is an advantage that an improved accumulation capacity can be obtained as compared with the related art.

Hereinafter, Embodiment 3 of the present invention proposes a structure in which storage capacity is further improved as compared with Embodiment 2 described above.

Example 3

Hereinafter, a third embodiment of the present invention will be described with reference to the cross-sectional views of FIGS. 8A to 8B. (The third embodiment of the present invention also includes the planar structure of FIG. 5 except for the contact hole formed on the pixel area. same.)

8A to 8B are cross sectional views taken along the lines VII-VII, VII-VII, and VII-VII of FIG. 5 (see FIG. 5 for reference numerals).

As shown, the third embodiment of the present invention constitutes a first storage electrode 157 in contact with an extended region of the storage wiring 142, and the pixel electrode is in contact with a reflector formed with the organic insulating layer interposed therebetween. Characterized in that configured to.

Hereinafter, a process according to a third embodiment of the present invention will be described.

As shown in FIG. 8A, after depositing the inorganic insulating material as described above on the transparent insulating substrate 130, a buffer layer 132 serving as the first insulating layer is formed.

Next, after depositing amorphous silicon (a-Si: H) on the buffer layer 132, a polysilicon layer crystallized by a predetermined method is patterned to form an island-shaped semiconductor layer 136 and a pixel in the semiconductor layer. The extension part 137 extended on the area | region (P of FIG. 5) is comprised.

The semiconductor layer 136 is defined as a first active region A serving as an active channel and a second active region B doped with impurities.

A gate insulating layer 138 which is a second insulating layer is formed on the substrate 130 on which the semiconductor layer 136 is formed.

Next, a gate electrode 140 is formed on the first active region A, a gate wiring 141 connected to the gate electrode 140 in one direction, and a predetermined area at one end of the gate wiring. The formed gate pad 144 is formed.

At the same time, the storage wiring 142 is formed in parallel with the gate wiring 141 at predetermined intervals, and a portion of the storage wiring 142 that passes above the pixel area P is extended to a predetermined area. 143).

A semiconductor layer defined as the second active region B is formed by depositing an insulating material on the entire surface of the substrate 130 on which the gate electrode 140 and the like are formed to form an interlayer insulating layer 146 as a third insulating layer. The first contact hole and the second contact hole 148a and 148b exposing the second contact hole 148a and the third contact hole 154 exposing the extension region 143 of the storage line are formed.

Next, a conductive metal group including aluminum (Al), aluminum alloy, chromium (Cr), tungsten (W), molybdenum (Mo), and neobium (Nb) on the third insulating layer 146 is selected. One is deposited and patterned to contact the source electrode 150 contacting the exposed second active region B, the drain electrode 152 spaced a predetermined distance from each other, and the extended region of the exposed storage wiring 143. An island-shaped source / drain metal layer 157 is formed.

At the same time, a data line 154 connected to the source electrode 150 extends in one direction and includes a data pad 156 having a predetermined area at one end thereof.

Polysilicon thin film transistor (T) is configured through the above process.

Next, as shown in FIG. 8B, an insulating material is deposited on the thin film transistor T to form a fourth insulating film 158, and then hydrogenation of the TFT is performed.

Next, one selected from a group of conductive metals such as aluminum (Al) and an aluminum alloy having excellent reflectance is deposited on the fourth insulating layer 158 and patterned to form a reflective plate 172 on the pixel region P. do.

The reflective plate 172 is configured to overlap the expansion area 143 of the storage wiring 142 in a plane.

Next, one selected from the group of transparent organic insulating materials including benzocyclobutene and acryl-based resin is deposited and patterned on the entire surface of the substrate 130 on which the reflective plate 172 is formed. 5 An insulating film 160 is formed.

Next, the fifth insulating layer 160 is patterned to expose the drain electrode 152, the gate pad 144, the data pad 156, and a part of the reflective plate 172.

Next, the pixel electrode 163 and the gate pad 144 formed on the pixel region P while simultaneously contacting the drain electrode 152 and the reflecting plate 172 using the transparent conductive metal material as described above. ) And a gate pad terminal 170 in contact with the data pad and a data pad terminal 174 in contact with the data pad 156.

In the above-described configuration, the reflective plate 172 in contact with the pixel electrode 163 together with the source / drain metal layer 157 in contact with the extension region 143 of the storage wiring 142 serves as the storage second electrode. The second storage capacitor C ₂ , and the source / drain metal layer 157 connected to the expansion region 143 of the storage line and the extension 137 of the active layer are respectively formed of the first storage electrode and the first storage electrode. The first storage capacitor C ₁ serving as the second storage electrode is configured.

The manufacturing process of the third embodiment of the present invention as described above is no additional process compared to the second embodiment, and compared with the first embodiment, since the insulating film is a structure in which two layers are omitted, the first and second implementations are performed. Compared to the example, there is an advantage that a more improved accumulation capacity can be obtained.

When the reflective array substrate is manufactured by the method according to the present invention as described above, the following effects are obtained.

First, since the number of processes is reduced, the yield of the product can be improved.

Second, since a thick organic insulating film exists between the reflective electrode and the transmissive electrode, galvanic corrosion does not occur between the two electrodes.

Therefore, the defective opening of an electrode can be prevented.

Third, by using an island-shaped metal layer in contact with the extension region and a reflector in contact with the pixel electrode as the first storage electrode and the second storage electrode, the storage capacitor value can be made larger. It works.

Claims (16)

A substrate; A thin film transistor formed on the substrate in an order of an active layer, a gate electrode, a drain electrode, and a source electrode; A gate wiring connected to the gate electrode and including a gate pad having a predetermined area at one end thereof, and a storage wiring configured to be parallel to the gate wiring at a predetermined interval; A data line defining a pixel area crossing the gate line and connected to the source electrode and including a source pad having a predetermined area at one end thereof; An extension part extending from the active layer to the pixel area by a predetermined area; A reflector formed over the expansion portion with an insulating film interposed therebetween and not in contact with the drain electrode; A pixel electrode formed over the reflective plate with an insulating film interposed therebetween and in contact with the drain electrode Array substrate for a transmissive liquid crystal display device comprising a. The method of claim 1, An array substrate for a transflective liquid crystal display device further comprising a buffer layer under the active layer. The method of claim 2, And the buffer layer is one selected from the group of inorganic insulating materials consisting of silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ). The method of claim 1, And the storage wiring is formed of the same material as the gate wiring. Preparing a substrate; Forming a thin film transistor on the substrate in the order of an active layer, a gate electrode, a drain electrode, and a source electrode; Forming a gate wiring connected to the gate electrode and including a gate pad having a predetermined area at one end thereof, and a storage wiring configured to be parallel to the gate wiring at a predetermined interval; Defining a pixel area crossing the gate wiring, and forming a data wiring connected to the source electrode and including a source pad having a predetermined area at one end thereof; Forming an extension extending from the active layer to the pixel area by a predetermined area; Forming a reflector formed on the extension and not in contact with the drain electrode; Forming a pixel electrode formed on the reflective plate and in contact with the drain electrode; Array substrate manufacturing method for a reflective transparent liquid crystal display device comprising a. The method of claim 5, A method of manufacturing an array substrate for a reflective transmissive liquid crystal display device, further comprising a buffer layer under the active layer. A substrate; A thin film transistor formed on the substrate in an order of an active layer, a gate electrode, a drain electrode, and a source electrode; A gate wiring connected to the gate electrode and including a gate pad having a predetermined area at one end thereof, and a storage wiring configured to be parallel to the gate wiring at a predetermined interval; A data line defining a pixel area crossing the gate line and connected to the source electrode and including a source pad having a predetermined area at one end thereof; An extension part extending from the active layer to a pixel area in a predetermined area; An island-shaped metal layer formed on and in contact with the storage wiring with an insulating film interposed therebetween; A reflector formed on the metal layer with an insulating film interposed therebetween and not in contact with the drain electrode; A transparent pixel electrode formed over the reflective plate with an insulating film therebetween and in contact with the drain electrode; An array substrate for reflective transmissive liquid crystal display device comprising. The method of claim 7, wherein And a buffer layer further comprising a buffer layer under the active layer. The method of claim 8, And the buffer layer is one selected from the group of inorganic insulating materials consisting of silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ). The method of claim 7, wherein And the storage wiring is formed of the same material as the gate wiring. The method of claim 7, wherein And the island-shaped metal layer is formed of the same material as the source electrode and the drain electrode. The method of claim 7, wherein And an array substrate in which the reflecting plate and the pixel electrode are in contact with each other. Preparing a substrate; Forming a thin film transistor on the substrate in the order of an active layer, a gate electrode, a drain electrode, and a source electrode; Forming a gate wiring connected to the gate electrode and including a gate pad having a predetermined area at one end thereof, and a storage wiring configured to be parallel to the gate wiring at a predetermined interval; Defining a pixel area crossing the gate wiring, and forming a data wiring connected to the source electrode and including a source pad having a predetermined area at one end thereof; Forming an extension part extending from the active layer to the pixel area by a predetermined area; Forming an island-shaped metal layer formed in contact with the storage wiring on an upper portion of the storage region passing through the pixel region, and having an insulating layer interposed therebetween; Forming a reflective plate on the metal layer with an insulating film interposed therebetween and not in contact with the drain electrode; And forming a transparent pixel electrode on the reflective plate with an insulating film interposed therebetween, the transparent pixel electrode being in contact with the drain electrode. The method of claim 13, A method of manufacturing an array substrate for a reflective transmissive liquid crystal display device, further comprising a buffer layer under the active layer. The method of claim 14, And the buffer layer is formed of one selected from the group of inorganic insulating materials consisting of silicon nitride (SiN _x ) and silicon oxide (SiO ₂ ). The method of claim 13, And forming the reflective plate and the pixel electrode in contact with each other.