KR100404319B1 - Fabrication method of high density and high uniformity solder bump without Cu cross-contamination in Si-LSI laboratory - Google Patents

Abstract

The present invention relates to a high density / high uniform solder bump forming method that can prevent copper cross-contamination, and more specifically, to a solder ball forming method having high density / high uniformity and copper cross-contamination. It is about how to solve the problem.

In order to solve the above problem, the present invention sputters the electrode for electroplating on a large scale integrated circuit chip substrate, and then forms a via by coating a photoresist film by a multi-coating method, and then solders. Provided is a solder bump forming method, characterized in that a solder ball is formed by sputtering a copper seed for plating.

Description

Fabrication method of high density and high uniformity solder bump without Cu cross-contamination in Si-LSI laboratory}

The present invention relates to a high density / high uniform solder bump forming method that can prevent copper cross-contamination, and more specifically, to a solder ball forming method having high density / high uniformity and copper cross-contamination. It is about how to solve the problem.

Flip chip interconnection technology using solder bumps is desperately needed for system miniaturization, light weight, and high speed, and is required for 10 × 10 mm ² chips after 1 ~ 2 years. As the integration of the number of input / output pins is expected to be more than 1500, the importance of flip chip interconnection technology is being emphasized. Flip chip interconnection technology needs to secure technological preoccupation as soon as possible and is recognized as a necessary technology in domestic industry.

Silicon large scale integrated circuit (LSI) processes can be classified into lithography, implantation, and metallization. Metals commonly used in silicon LSI laboratories include TiW, TiN, aluminum and the like. In order to achieve high integration of a large scale integrated circuit, the line width of the wiring must be narrowed, but when the line width of the wiring is narrowed, the wiring resistance becomes large, which interferes with the electrical signal transmission and affects the IC performance. Copper is one of the material candidates that can solve this problem because of its low wiring resistance. Therefore, copper has been in the spotlight as a wiring material for modules and multilayer boards requiring high integration and high speed / high frequency performance. In addition, copper is a material that must be used since it is used as a layer for seeding and solder plating for copper buffer layer plating when forming a solder ball. Wafer track, vacuum chuck, hot plate for photoresist baking, mask aligner for photoresist exposure, microscope, wafer carrier for semiconductor chip fabrication Wafer carriers may cause unintentional metal cross-contamination by using the metal without distinguishing it.

In view of this, not only the process including copper can be performed while maintaining the existing silicon LSI lab process, but there is an urgent need for a process without copper cross-contamination, but most silicon LSI processes do not use copper as a wiring material. There are many cases. Because copper is easy to diffuse, even if cross contamination of parts per million (ppm) on the chip wafer acts as a source of leakage current of the transistor, thus affecting the IC performance. This can be fatal.

Conventional solder bump formation method has a via of copper seed and electroplating electrode for solder plating, while independently holding a process laboratory capable of processing copper, outside the silicon LSI lab. Sputtering prior to photoresist coating has resulted in the formation of solder balls [JD Mis et al., USA patent no. 5767010]. However, this process requires a separate preparation of each laboratory and the process equipment, there is a problem that costs a lot in terms of equipment equipment, equipment management.

If the silicon LSI laboratory equipment is not used independently and the copper process laboratory is shared, the copper seed and electroplating electrodes are sputtered before the via formation for solder plating. Since there may be a small amount of copper on the back and side surfaces, copper may be left on the process equipment during the via forming process, so the integrated circuit board using the equipment is easily contaminated with copper, so the hot plate used in silicon LSI ), Mask aligners, sputtering equipment, etc. cannot be used.

Therefore, the present invention is to solve the problems of the prior art as described above, the present invention solves the copper cross-contamination problem through a new solder ball forming method, the solder ball height 60㎛ at low cost The above object is to form a ball for flip-chip interconnection having high density / high uniformity.

1 is a state diagram showing an electron micrograph of a via pattern having a height of 50 μm and a diameter of 100 μm formed from a thick photoresist coated by several coating methods;

2 is a state diagram showing an electron micrograph of a high density solder ball having a height of 60 μm, a diameter of 60 μm, and a cycle of 150 μm formed by a copper cross contamination problem solving method;

3A to 3G are flowcharts illustrating a manufacturing process of a solder bump formed by a method for solving a copper cross-contamination problem according to an exemplary embodiment of the present invention.

Table 1 shows the process algorithms for high density, high quality solder bump formation.

※ Explanation of code about main part of drawing ※

1: chip substrate 2: chip-Al electrode pad

3: substrate passivation film 4: electrode for TiW / Al plating

5: photosensitive film 6: seed layer (Cu / Ti under ball metallurgy)

7: solder bump

High uniformity / high density solder bump forming method for preventing copper contamination according to the present invention for achieving the above object is by sputtering the electrode for electroplating, and then a photosensitive film coating by a multi-coating technology A method of forming a solder bump is provided, wherein a solder ball is formed by sputtering a copper seed for solder plating after forming a via.

Preferably, the copper / titanium (Cu / Ti) seeds on the surface of the photoresist film selectively etch the copper seeds on the surface of the photoresist film during the copper plating using a difference in resistance between vias and the surface of the photoresist film. A method for forming solder bumps is provided, characterized by self-etching.

Hereinafter, with reference to the accompanying drawings will be described in more detail a high density / high uniform solder bump forming method that can prevent copper contamination according to an embodiment of the present invention.

1 is a state diagram showing an electron micrograph of a via pattern having a height of 50 μm and a diameter of 100 μm formed from a thick photoresist (PR) coated by several coating methods according to the present invention; 2 is a state diagram showing an electron micrograph of a high density solder ball having a height of 60 μm, a diameter of 60 μm, and a cycle of 150 μm formed by a copper cross contamination problem solving method.

In order to obtain a high solder ball, a photosensitive film having a thickness of 50 µm-70 µm must be obtained. In order to obtain a photosensitive agent having the thickness, the photosensitive agent can be coated several times. In order to obtain a uniform and dense solder ball, the equipment aspects such as securing electrode contacts, uniformity of liquid circulation, and the use of a ripple-free rectifier are important, but special care should be taken when soldering. In particular, since copper / titanium (Cu / Ti) seeds are sputtered after via formation, it is necessary to thinly sputter the copper / titanium (Cu / Ti) seeds so as not to plate copper and solder on the photoresist film surface.

If the copper is thinly plated before the electroplating of the solder, the copper / titanium (Cu / Ti) seeds on the surface of the photoresist film 5 may be deposited on the surface of the photoresist film due to the difference in resistance between the vias and the surface of the photoresist film. The seeds can be selectively etched during copper plating. Therefore, after proper plating of copper, etching the copper / titanium layer (6) and subsequently plating copper and solder (7) can solve the copper contamination problem in the silicon LSI process, and the bump height is high at low cost. It is possible to form solder balls of high density.

Figure 2 is a state diagram showing the shape of the high-density solder ball made by such a process, the left side is a plan view, the right side is a side view taken with high resolution. The solder ball forming process sequence and forming method of high density / high uniformity are as follows.

Example 1

3A to 3G are manufacturing process diagrams of solder bumps formed by the copper cross-contamination problem solving method. 3A and 3B show an electrode sputtering and photoresist coating process for plating, wherein the figures show TiW (TiW) on a silicon substrate 1 formed and die passivated by an LSI chip pad 2 in a silicon LSI laboratory. After sputtering the 2200 kPa) / Al (4000 kPa) plating electrode 4, the AZ4000 series photoresist was coated several times at 1000 rpm to obtain a photoresist film 5 having a thickness of 50 µm to 70 µm. It is shown. Coating the photoresist film 5 at a low spin speed causes the coated photoresist film 5 to be thickened at the wafer edge so that the mask is strongly pressed against the mask aligner ( hard contact) After the photoresist film 5 was coated to prevent the wafer from being unevenly applied, the edge portion of the photoresist film 5 was removed. Baking of the photoresist film 5 was performed at 110 ° C. for 3 minutes every time the photoresist film 5 was coated to prevent the photoresist film 5 from peeling off during recoating.

Example 2

FIG. 3C shows a via forming process using a contact aligner, which uses the contact aligner to prevent deformation of the photoresist film 5 which may be generated by instantaneous exposure of strong light. Sufficient light is exposed to shorten the development time of the photoresist film 5, and because the exposure time is long, the mask aligner is momentarily prevented from being affected by vibration, and light is emitted from the mask. The hard contact method was used to minimize diffraction.

Example 3

In order to develop the photoresist film 5 in a short time, ultrasonic power of weak power was used, and a vertical angle of the via was obtained by 85 ° or more (see FIG. 1). Via formation and development time were significantly improved compared to without the use of ultrasound.

Example 4

FIG. 3D shows a copper / titanium (Cu / Ti) sputtering process, in which a silicon LSI is used to form the vias of 40, 60, 80, and 100 μm in a test pattern to form solder bumps. After formation in the laboratory, thin copper / titanium (Cu / Ti) seeds 6 were fab-outed out of the silicon LSI lab.

In order to secure electrode contacts for electroplating and the copper / titanium (Cu / Ti) seed layer 6 to minimize conduction efficiency on the surface of the photoresist film 5, the wafer edge is separated so as to be on the surface of the photoresist film 5. The role of the electrode of the copper / titanium (Cu / Ti) seed 6 was minimized to secure the plating rate difference between the via and the surface of the photosensitive film. Therefore, by using this difference in plating speed, the copper seed 6 layer on the surface of the photoresist film 5 was etched during plating so that copper was selectively plated (selective plating method) only on the vias. This selective plating method was first devised in the present invention.

Example 5

3E-3F are solder bump plating and photoresist and electrode etch processes, which are current losses that may be caused by the copper / titanium layer 6 remaining on the surface of the photoresist film 5 when plating the solder. After plating a copper buffer to prevent solder precipitation (7) on the surface of the photoresist film (5), after slightly immersing the wafer in a FA: FB: DI solution, copper / buffer in a buffered hydrogen fluoride (HF) solution The titanium layer 6 was completely etched. Since copper may be oxidized during etching of the copper / titanium layer 6, the solder plating 7 having a composition ratio of 6: 4 after cleaning in an organic acid solution to remove the oxide film on the copper plating surface has a low current density. By gradually increasing to a high current density at to obtain a uniform plating of the solder (7). In addition, the solder was over-plated 7 above the via height to form a high bump. Through the above-described process, as shown in FIG. 2, a high density solder ball having a solder ball diameter of 40 μm and a ball pitch of 100 μm could be easily formed.

The TiW / Al electrode 4 was etched after peeling off the photoresist film 5 with acetone from the wafer on which the solder 7 was plated (FIG. 3F).

Example 6

FIG. 3G illustrates the solder bump reforming process. In this process, the solder 7 is reflowed in a nitrogen atmosphere to form a ball-shaped solder ball.

Table 1 is a process algorithm for the formation of high density, high quality solder bumps of FIGS. 3A to 3G, and the process in the silicon LSI laboratory and the fab.-out of the silicon LSI laboratory can be easily understood.

While the invention has been described above based on the preferred embodiments thereof, these embodiments are intended to illustrate rather than limit the invention. It will be apparent to those skilled in the art that various changes, modifications, or adjustments to the above embodiments can be made without departing from the spirit of the invention. Therefore, the protection scope of the present invention will be limited only by the appended claims, and should be construed as including all such changes, modifications or adjustments.

As described above, even if several ppm are contaminated on the chip wafer due to copper contamination, it may act as a source of leakage current of the transistor, which may have a fatal effect on the IC performance. The present invention can be solved, and by making the most of the existing equipment, the ball height is high due to low facility investment, and a high density solder ball can be formed, thereby greatly reducing the production cost.

Claims (10)

In the solder bump forming method, A first step of sputtering an electrode for electroplating on a highly integrated circuit chip substrate; A second step of forming a photoresist film having a thickness of 50 μm to 70 μm by coating a photosensitive agent on the electrode plating electrode several times; A third step of forming a via penetrating the photoresist film and the electroplating electrode by exposing the photoresist film in a hard contact manner using a contact aligner on the photoresist film; A fourth step of sputtering copper / titanium seeds for solder plating onto the photoresist film; A fifth step of forming a solder bump by soldering the copper / titanium seed by a selective plating method using a plating speed difference between the via and the photoresist film, and then soldering the via; A sixth step of etching the electroplating electrode to prevent conduction between the solder bumps after removing the photoresist film; And And forming a solder ball by reflowing the solder bumps. The method of claim 1, And the fourth step is to sputter a thin copper / titanium (Cu / Ti) seed in order to prevent the copper and solder from being plated on the surface of the photoresist film. The method of claim 2, In the fifth step, the copper / titanium (Cu / Ti) seeds on the surface of the photoresist film may be selectively selected during the copper plating on the copper seeds on the surface of the photoresist film by using a difference in resistance between vias and the surface of the photoresist film. Solder bump forming method characterized in that the etching (self-etching). The method of claim 1, The second step is a solder bump forming method, characterized in that to coat the photoresist film by a multi-coating technique to obtain a photoresist film of 50㎛-70㎛ thickness. delete delete The method of claim 1, After the fourth step, the copper / titanium layer is completely covered after plating a copper buffer to prevent current loss that may be caused by the copper / titanium seed and deposition of solder on the photoresist film surface. Solder bump forming method further comprising the step of etching. The method of claim 1, The fifth step is a solder bump forming method, characterized in that to gradually increase the solder plating from a low current density to a high current density to form the solder plating of a uniform structure. The method of claim 8, The fifth step is a solder bump forming method, characterized in that the solder plating to be higher than the via height to form the high solder bump. delete