KR960011855B1 - Manufacturing method of bump of semiconductor device - Google Patents

Manufacturing method of bump of semiconductor device Download PDF

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Publication number
KR960011855B1
KR960011855B1 KR1019920018468A KR920018468A KR960011855B1 KR 960011855 B1 KR960011855 B1 KR 960011855B1 KR 1019920018468 A KR1019920018468 A KR 1019920018468A KR 920018468 A KR920018468 A KR 920018468A KR 960011855 B1 KR960011855 B1 KR 960011855B1
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South Korea
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forming
bump
metal layer
film
layer
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KR1019920018468A
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Korean (ko)
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KR940010284A (en
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윤상현
김진태
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삼성전자 주식회사
김광호
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material

Abstract

The method includes the steps of; forming an electrode pad(4) on a semiconductor chip(100), forming a passivation film(6) exposed to most of electrode pads; forming the first metal layer; forming the first mask layer having the first entrance unit in the region for a form of bump(16); forming the second metal layer in the first entrance unit; forming the second mask layer having a plurality of the second entrance unit; forming the third metal layer of an island type which is connected with the second metal layers respectively.

Description

반도체장치의 범프 형성방법Bump Formation Method of Semiconductor Device

제1도 내지 제4도는 종래의 범프 형성방법을 설명하기 위한 단면도들.1 to 4 are cross-sectional views illustrating a conventional bump forming method.

제5도 내지 제8도는 본 발명에 의한 범프 형성방법을 설명하기 위한 단면도들.5 to 8 are cross-sectional views for explaining the bump forming method according to the present invention.

본 발명은 반도체장치의 범프 형성방법에 관한 것으로, 특히 Al전극의 표면에 선택적으로 형성되고 외부 배선층에 우수하게 접속시킬 수 있는 반도체장치의 칩 범프(Chip Bump)의 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bump forming method of a semiconductor device, and more particularly, to a method of forming a chip bump of a semiconductor device which can be selectively formed on the surface of an Al electrode and can be connected to an external wiring layer excellently.

최근 전자기기의 소형화에 수반해서 IC(Integrated Cirouit)라든지 LSI(Large Scale Integration) 등과 같은 반도체칩은 고밀도 및 집적화가 급진적으로 진행되고 있는 한편, 반도체소자의 설치면적에 있어서도 전극 피치간의 축소화라든지 입출력단자의 갯수를 증대시켜야 된다는 경향이 있다. 또 전자식 탁상기라든지 IC카드에 있어서도 카드화에 대응하는 박형화가 요구된다.Recently, with the miniaturization of electronic devices, semiconductor chips such as IC (Integrated Cirouit) and LSI (Large Scale Integration) are rapidly progressing in high density and integration, while reducing the pitch between electrode pitches and input / output terminals in the installation area of semiconductor devices. There is a tendency to increase the number of. In addition, even in an electronic tabletop or an IC card, a thinning corresponding to cardization is required.

TAB(Tape Automated Bonding)방식이나 플립칩 방식 등과 같은 와이어리스(wireless) 본딩방식은 일괄접합과 위치맞춤 정도로부터 오는 신뢰성, 설치면적의 박형화 및 자동화적인 면에서 금후 LSI칩의 설치 기술의 주류가 되고 있다. 이 와이어리스 본딩방식에서는 일반적으로 LSI칩의 알루미늄전극상에 범프라 일컬어지는 금속돌기물이 형성되게 된다.Wireless bonding methods such as TAB (Tape Automated Bonding) and flip chip methods have become the mainstream of LSI chip installation technology in the future in terms of reliability, thinning of installation area and automation resulting from batch bonding and alignment accuracy. . In this wireless bonding method, bumpy metal projections are generally formed on an aluminum electrode of an LSI chip.

종래의 방법으로 형성되는 범프는 제1도 내지 제4도의 형성공정에 의해 형성된다.The bump formed by the conventional method is formed by the forming process of FIGS.

제1도를 참조하면, 반도체기판(100)상에 절연막(2)을 형성하고, 예컨대 알루미늄(Al)과 같은 도전물질을 증착시킨 다음 상기 도전물질을 패터닝하여 전극패드(4)를 형성한다. 이어서, 상기 전극패드(4) 위에 보호막용 물질을 증착시켜 패시베이션막(Passivation film; 6)을 형성한 다음, 상기 전극패드(4)의 일부가 노출되도록 상기 패시베이션막(6)을 패터닝한다.Referring to FIG. 1, an insulating film 2 is formed on a semiconductor substrate 100, a conductive material such as aluminum (Al) is deposited, and then the conductive material is patterned to form an electrode pad 4. Subsequently, a passivation film 6 is formed by depositing a protective film on the electrode pad 4, and then the passivation film 6 is patterned to expose a portion of the electrode pad 4.

제2도를 참조하면, 전극패드의 일부가 노출된 상태에서 상기 전극패드(4)의 표면에 형성된 자연산화막을 제거하기 위하여 고진공장치에서 RF식각 방식을 이용하여 상기 산화막을 제거한다. 이어서, 상기 산화막이 제거된 즉시 범프형성에 대비한 접착용 금속막(8), 장벽용 금속막(10) 및 도금용 금(Au)막(12)을 스퍼터링(sputtering)방식에 의해 각각 200Å∼500Å, 1,000Å∼3,000Å, 500Å∼2,000Å 정도의 증착시킨다.Referring to FIG. 2, in order to remove a natural oxide film formed on the surface of the electrode pad 4 while a part of the electrode pad is exposed, the oxide film is removed by using an RF etching method in a high vacuum apparatus. Subsequently, as soon as the oxide film was removed, the adhesive metal film 8, the barrier metal film 10, and the plating gold (Au) film 12 prepared for bump formation were each sputtered by 200 kPa. The deposition is performed at 500 mV, 1,000 mV to 3,000 mV and about 500 mV to 2,000 mV.

제3도를 참조하면, 전해도금영역을 한정하기 위하여 결과물의 전면에 20㎛∼30㎛ 정도의 두께로 포토레지스트(14)를 도포한 다음, 노광 및 현상공정 등을 거쳐 전해도금영역상의 포토레지스트를 제거한다. 이어서, 상기 포토레지스트가 제거된 공간에 전해도금방식을 이용하여 Au범프(16)를 형성한다.Referring to FIG. 3, in order to limit the electroplating region, the photoresist 14 is applied to the entire surface of the resultant with a thickness of about 20 µm to 30 µm, and then subjected to exposure and development processes, and the like, on the electroplating region. Remove it. Subsequently, Au bumps 16 are formed in the space where the photoresist is removed by using an electroplating method.

제4도을 참조하면, 남아있는 포토레지스트를 제거한 다음, 상기 Au범프(16)를 식각마스크로 하여 스퍼터링된 하부의 막질들, 즉 Au막(12), 장벽막(10) 및 접착막(8)을 차례로 이방성 식각한다. 이때, 상기 막질들의 식각시 할로겐화 가스와 염소계 가스를 적절히 혼합하여 실시함으로서 상기 범프의 상단표면에 미세한 V자 모양의 홈(18)을 형성하도록 한다. 이어서, 각 층간의 접착력을 향상시키기 위하여 250℃∼350℃ 정도의 온도에서 1시간∼2시간 정도 열처리를 실시한다.Referring to FIG. 4, after the remaining photoresist is removed, the lower film materials sputtered with the Au bumps 16 as an etch mask, that is, the Au film 12, the barrier film 10, and the adhesive film 8 are removed. Is then anisotropically etched. At this time, the etching of the film quality is performed by appropriately mixing the halogenated gas and chlorine-based gas to form a fine V-shaped groove 18 on the upper surface of the bump. Subsequently, in order to improve the adhesive force between each layer, heat processing is performed for about 1 hour-2 hours at the temperature of about 250 degreeC-350 degreeC.

상술한 종래의 칩범프 형성방법에 따르면, ILB(Inner Lead Bonding)후 범프의 상단부가 옆으로 처지는 경향이 있으며, 범프의 하단부에 형성되어 있는 막질에 크랙(crack)을 유발할 수 있다. 또한, ILB시 범프의 상단부에 형성되는 V자 모양의 미세한 홈(18)은 그 크기와 모양등을 리드표면의 상황에 맞게 적절하게 대처하기가 어렵다는 문제점이 있다.According to the conventional chip bump formation method described above, the upper end portion of the bump tends to sag sideways after the inner lead bonding (ILB), and may cause cracks in the film formed on the lower end portion of the bump. In addition, the V-shaped fine groove 18 formed at the upper end of the bump during ILB has a problem that it is difficult to properly deal with the size and shape of the bump according to the situation of the lead surface.

따라서, 본 발명의 목적은 상기한 종래의 문제점을 해결할 수 있는 칩범프 형성방법을 제공하는데 있다.Accordingly, it is an object of the present invention to provide a chip bump forming method that can solve the above-mentioned conventional problems.

본 발명의 다른 목적은 ILB시 접착력을 향상시킬 수 있는 칩범프 형성방법을 제공하는데 있다.Another object of the present invention to provide a chip bump forming method that can improve the adhesive strength during ILB.

상기 목적은 달성하기 위하여 본 발명은 반도체장치의 제조방법에 있어서, 반도체기판상에 형성된 전극패드 위에 소정의 물질층을 형성하는 공정; 상기 물질층 위에 마스크용 물질을 도포한 후 상기 마스크용 물질을 패터닝하여 제1마스크층을 형성하는 공정; 상기 제1마스크층에 의해 개구된 영역에 제1범프를 형성하는 공정; 결과물 전면에 마스크용 물질을 도포한 후 패터닝하여 상기 제1범프의 상부에 사기 제1범프와 면적이 다른 한 개 또는 다수의 개구부를 형성하는 공정; 및 상기 개구부를 통해 상기 제1범프의 상부에 제2범프를 형성하는 공정을 포함하는 것을 특징으로 하는 반도체장치의 범프 형성방법을 제공한다.In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising: forming a layer of a material on an electrode pad formed on a semiconductor substrate; Applying a mask material on the material layer and then patterning the mask material to form a first mask layer; Forming a first bump in a region opened by the first mask layer; Coating and patterning the mask material on the entire surface of the resultant to form one or a plurality of openings different in area from the first bump on the first bump; And forming a second bump on the first bump through the opening.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제5도 내지 제8도는 본 발명에 의한 칩범프 형성방법이 일실시예를 설명하기 위한 단면도들이다.5 to 8 are cross-sectional views illustrating a chip bump forming method according to an embodiment of the present invention.

제5도를 참조하면, 반도체기판상에 절연막, 전극패드 및 보호막을 형성한 상태를 도시한 것으로서, 먼저, 반도체기판(100)상에 예컨대 산화막과 같은 절연물질을 도포하여 절연막(2)을 형성하고, 예컨대 알루미늄(Al)과 같은 도전물질을 증착시킨 다음 상기 도전물질을 패터닝하여 전극패드(4)를 형성한다. 이어서, 상기 전극패드(4) 위에 예컨대 실리콘산화막(SiO2) 또는 실리콘질화막(Si3N4)과 같은 물질을 증착시켜 패시베이션막(6)을 형성한 다음, 상기 패시베이션막을 선택적으로 식각하여 상기 전극패드(4)의 대부분을 노출시킨다.Referring to FIG. 5, an insulating film, an electrode pad, and a protective film are formed on a semiconductor substrate. First, an insulating material such as an oxide film is coated on the semiconductor substrate 100 to form an insulating film 2. For example, an electrode pad 4 is formed by depositing a conductive material such as aluminum (Al) and then patterning the conductive material. Subsequently, a passivation layer 6 is formed by depositing a material such as a silicon oxide layer (SiO 2 ) or a silicon nitride layer (Si 3 N 4) on the electrode pad 4 , and then selectively etching the passivation layer. Most of the pad 4 is exposed.

계속해서, 전극패드의 일부가 노출된 상태에서 상기 전극패드(4)의 표면에 형성된 자연산화막을 제거하기 위하여 고진공장치에서 RF식각방식을 이용하여 상기 산화막을 제거한다.Subsequently, in order to remove the natural oxide film formed on the surface of the electrode pad 4 while a part of the electrode pad is exposed, the oxide film is removed by using an RF etching method in a high vacuum apparatus.

이어서, 상기 산화막이 제거된 즉시 결과물 위에 침전 또는 스퍼터링(sputtering)방식에 의해 범프형성에 대비한 밑바탕 금속층으로 접착(adhesion)용 금속막(8), 장벽(barrier)용 금속막(10) 및 도금용 금(Au)막(12)을 각각 200Å∼500Å, 1,000Å∼3,000Å, 500Å∼2,000Å 정도의 두께로 증착시킨다.Subsequently, immediately after the oxide film is removed, the metal film 8 for adhesion, the metal film 10 for barrier, and the plating are formed on the resultant as a base metal layer in preparation for bump formation by precipitation or sputtering. The gold (Au) film 12 is deposited to a thickness of about 200 mW to 500 mW, 1,000 mW to 3,000 mW and 500 mW to 2,000 mW, respectively.

제6도를 참조하면, 전해도금영역 한정하기 위하여 결과물의 전면에 약 20㎛∼30㎛ 정도의 두께로 포토레지스트를 도포한 다음 노광 및 현상공정 등을 거쳐 전해도금영역상의 포토레지스트를 제거함으로써 제1포토레지스트 패턴(14)를 형성한다. 이어서, 상기 포토레지스트 패턴(14)에 의해 개구된 공간에 상기 밑바탕 금속층을 음극으로 하는 전해도금 방식을 이용하여 제1Au범프(16)를 형성한다.Referring to FIG. 6, in order to limit the electroplating area, a photoresist is applied to the entire surface of the resultant with a thickness of about 20 μm to 30 μm, and then the photoresist on the electroplating area is removed by exposure and development processes. One photoresist pattern 14 is formed. Subsequently, the first Au bumps 16 are formed in the space opened by the photoresist pattern 14 by using an electroplating method using the underlying metal layer as a cathode.

제7도를 참조하면, 1차적으로 형성된 상기 제1Au범프(16)의 상부에 포토레지스트를 제6도의 경우에 비해 비교적 얇게, 즉 1㎛∼15㎛ 정도의 두께로 도포한 후 노광 및 현상 등의 공정을 거쳐 상기 1차 Au범프(16)의 상부가 노출되도록 하는 제2포토레지스트 패턴(18)을 형성한다.Referring to FIG. 7, the photoresist is first applied to the upper portion of the first Au bump 16 formed relatively thinner than that of FIG. 6, that is, 1 μm to 15 μm, and then exposed and developed. Through the process of forming a second photoresist pattern 18 to expose the upper portion of the primary Au bumps 16.

이어서, 상기 제2포토레지스트 패턴(18)에 의해 노출된 부분에 전해도금방식으로 버섯모양 또는 벽(straight wall)모양의 형태로 상기 제1Au범프와 면적이 다른 한 개 또는 다수의 제2Au범프(20)를 1㎛∼15㎛ 의 높이로 형성한다.Subsequently, one or a plurality of second Au bumps different in area from the first Au bumps in the form of mushrooms or straight walls may be formed by electroplating on the portions exposed by the second photoresist pattern 18. 20) is formed at a height of 1 µm to 15 µm.

제8도를 참조하면, 1차 및 2차 범프 형성용으로 사용된 포토레지스트를 동시에 제거한 다음, 상기 Au범프를 식각마스크로 하여 스퍼터된 하부의 밑바탕 금속층, 즉 Au막(12), 장벽막(10) 및 접착막(8)을 차례로 이방성 식각한다.Referring to FIG. 8, at the same time, the photoresist used for forming the primary and secondary bumps is simultaneously removed, and then the underlying underlying metal layer sputtered with the Au bumps as an etch mask, that is, the Au film 12 and the barrier film ( 10) and the adhesive film 8 are sequentially anisotropically etched.

이어서, 각 층간의 접착력을 향상시키고 접촉저항을 감소시키기 위하여 약 250℃∼350℃ 정도의 온도에서 1시간∼2시간 정도의 열처리를 실시한다.Subsequently, heat treatment is performed for about 1 hour to 2 hours at a temperature of about 250 ° C. to 350 ° C. to improve adhesion between the layers and to reduce contact resistance.

상술한 본 발명에 의한 칩범프 형성방법에 따르면, Au범프의 상단부의 접착면적이 증가되거나, 또는 상기 Au범프 상단부에 요철부가 형성되고, 범프상단면의 가장자리와 가운데 부분의 높이가 균일하게 형성되므로, 리드(lead)와 열압착 본딩시 보다 효과적인 합금이 형성되어 기계적 강도가 향상되며, ILB시 범프를 통해 전극패드 또는 패시베이션에 가해지는 기계적 충격을 2차로 형성된 범프에 의해 완화시킬 수도 있다.According to the chip bump forming method according to the present invention, the adhesion area of the upper end of the Au bump is increased, or the uneven portion is formed in the upper end of the Au bump, the height of the edge and the center of the upper surface of the bump uniformly formed In addition, a more effective alloy is formed during the lead and thermocompression bonding, thereby improving mechanical strength, and a mechanical shock applied to the electrode pad or the passivation through the bump during ILB may be mitigated by the secondary bump.

또한, 리드표면의 상태에 따라 범프표면의 모양을 다양하게 만들어 줄 수 있다.In addition, the shape of the bump surface can be varied according to the state of the lead surface.

본 발명은 상기 실시예에 한정되지 않으며, 본 발명이 기술적 사상내에서 당분야의 통상의 지식을 가진 자에 의해 많은 변형이 가능함은 물론이다.The present invention is not limited to the above embodiments, and the present invention can be modified in many ways by those skilled in the art within the technical idea.

Claims (5)

반도체기판 상에 전극패드를 형성하는 단계; 전극패드가 형성된 결과물 상에, 상기 전극패드의 중앙부를 포함하는 전극패드의 대부분을 노출시키는 패시베이션막을 형성하는 단계; 상기 패시베이션막이 형성된 결과물 상에 제1금속층을 형성하는 단계; 상기 제1금속층 상에, 범프가 형성될 영역에 제1개구부를 갖는 제1마스크층을 형성하는 단계와; 상기 제1개구부내에 제2금속층을 형성하는 단계; 상기 제2금속층이 형성된 결과물 상에, 상기 제2금속층의 일부를 노출시키는 제2개구부를 하나이상 갖는 제2마스크층을 형성하는 단계; 및 상기 제2개구부들을 통해 상기 제2금속층과 각각 연결되는 섬모양의 제2금속층들을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 장치의 범프 형성방법.Forming an electrode pad on the semiconductor substrate; Forming a passivation film exposing a majority of the electrode pads including a central portion of the electrode pads on the resultant electrode pads; Forming a first metal layer on the resultant product on which the passivation film is formed; Forming a first mask layer having a first opening in a region where bumps are to be formed on the first metal layer; Forming a second metal layer in the first opening; Forming a second mask layer having at least one second opening that exposes a portion of the second metal layer on the resultant product on which the second metal layer is formed; And forming second island-like metal layers connected to the second metal layer through the second openings, respectively. 제1항에 있어서, 상기 제1마스크층은 20∼30㎛ 정도의 두께로 형성하고, 상기 제2마스크층은 1∼15㎛ 정도의 두께로 형성하는 것을 특징으로 하는 반도체 장치의 범프 형성방법.The method of claim 1, wherein the first mask layer is formed to a thickness of about 20 to 30 μm, and the second mask layer is formed to a thickness of about 1 to 15 μm. 제1항에 있어서, 상기 제2금속층 및 제3금속층은 전해도금 방식으로 형성되는 것을 특징으로 하는 반도체 장치의 범프 형성방법.The method of claim 1, wherein the second metal layer and the third metal layer are formed by an electroplating method. 제1항에 있어서, 상기 제1금속층은 접착용 금속막과 장벽용 금속막으로 이루어지는 것을 특징으로 하는 반도체 장치의 범프 형성방법.The bump forming method of claim 1, wherein the first metal layer comprises an adhesive metal film and a barrier metal film. 제1항에 있어서, 상기 제2금속층은 금(Au) 범프로 이루어지는 것을 특징으로 하는 반도체 장치의 범프 형성방법.The method of claim 1, wherein the second metal layer is formed of gold (Au) bumps.
KR1019920018468A 1992-10-08 1992-10-08 Manufacturing method of bump of semiconductor device KR960011855B1 (en)

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