KR100399969B1 - Sense amplifier for improved programmable logic array - Google Patents

Abstract

PURPOSE: A sense amplifier for improved programmable logic array is provided to improve a period of time for processing signals by reducing a delay period of time for processing the signals. CONSTITUTION: A sense amplifier for improved programmable logic array includes a first node, a second node, a third node, an input part(10), a precharge part, a voltage dropping part, a pull-down part, an amplification part(14), and an output part(16). The input part(10) provides signals corresponding to plural input signals to the first node. The precharge part is used for precharging the second node by a supply voltage. The voltage dropping part is connected between the second node and the first node in order to drop a voltage level of the second node as much as a predetermined level. The pull-down part performs a pull-down driving operation for the first node in response to the first node. The amplification part(14) is connected between the second node and the third node in order to supply an amplified signal to the third node. The output part(16) outputs a signal of the third node to the outside.

Description

Enhanced Sense Amplifier for Programmable Logic Arrays

The present invention relates to a sense amplifier, and more particularly to a sense amplifier used in a programmable logic array (PLA).

Conventionally, sense amplifiers are commonly utilized in decoder blocks consisting of multiple logic gates in microcomputer units (MPUs) from decoder logic to programmable logic arrays. Such sense amplifiers are, for example, low-level voltages, such as thin film memories. It can be said that the function of amplifying the signal to a predetermined level raises the signal to the logic voltage level of the system.

As a conventional sense amplifier mainly used for the programmable logic array as described above, there is a type as shown in FIG. As shown in the figure, a typical sense amplifier for a programmable logic array is composed of a plurality of n-type field effect transistors (hereinafter referred to as n-type transistors) and a plurality of p-type field effect transistors (hereinafter referred to as p-type transistors). And an input unit 20, an amplifier unit 22, and an output unit 24.

In FIG. 2, the input unit 20 receives three input signals A, B, and C through a gate, and three n-type transistors MN21, MN22, and MN23 connected in parallel between the node 21 and the ground voltage supply terminal. The precharge signal prech A is input to the gate, and the source is connected to the power supply voltage VDD supply terminal, and the drain is configured as the p-type transistor MP21 connected to the node 21.

In addition, the amplifier 22 is configured with a typical differential amplifier, which is well known in the art, amplifies the difference between two input voltages (gate voltages of two n-type transistors MN24 and MN25) and outputs a change in the output voltage. The two p-type transistors MP22 and MP23 and the n-type transistors MN24 and MN25 which are symmetrical to each other, and the n-type transistors MN24 and MN25 are subjected to pressure under a selection signal SEL for setting a current value through a gate. N-type transistor (MN26) connected in common with each source of the source and the drain is connected to the ground voltage supply terminal.

On the other hand, the reference voltage generator 24 is to provide a reference voltage which is an input voltage provided to the gate of the n-type transistor MN25 in the amplifier 22, between the power supply voltage VDD supply terminal and the ground voltage supply terminal. The reference voltage Vref is generated by voltage distribution using three n-type transistors MN27, MN28, and MN29 connected in series.

On the output side of the amplifier 22, an output unit 26 formed of an inverter INV2 is provided. The output value OUT of the output unit 26 has a low level voltage up to a system logic voltage level at a later stage. It will be the amplified voltage value.

On the other hand, in the conventional sense amplifier for a programmable logic array having the above-described configuration, the node 21 is a large capacitor because the cells are connected, and when looking at the voltage swing here, When multiple inputs are at high level, they go to ground level and when all the multiple inputs are at low level, they make full swing from ground to VDD going to voltage VDD level.

As a result, since both C and ΔV are large at Δt = C1 / εΔV, there is a problem in that the delay time is large. That is, the conventional sense amplifier has a disadvantage that the processing speed of the signal is slow due to this delay time.

Accordingly, the present invention is to solve the above-mentioned problems of the prior art, an improved programmable that can reduce the voltage swing width in the signal processing path, and to reduce the delay time of the signal processing by making a fast transition when the signal transitions The purpose is to provide a sense amplifier for a logic array.

An improved programmable sense array for a programmable logic array of the present invention for achieving the above object comprises: a first node, a second node, and a third node; An input unit configured to provide a signal corresponding to a plurality of input signals to the first node; A precharge unit for precharging the second node with a power supply voltage VDD; A voltage drop unit connected between the second node and the first node to drop the voltage level of the second node by a predetermined level to transfer the voltage level to the first node; A pull-down unit configured to pull down the first node in response to the first node; An amplifying unit connected between the second node and the third node to provide the amplified signal to the third node, and performing a positive feedback to achieve a fast transition of the signal; And an output unit configured to output the signal of the third node to the outside.

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

1 shows a circuit diagram of a sense amplifier for a programmable logic array in accordance with a preferred embodiment of the present invention. As shown in the figure, the sense amplifier of the present invention includes an input section 10, precharge section 11, voltage drop section 12, pull-down section 13, amplifier section 14 and output section 16 It includes.

In FIG. 1, the input unit 10 transmits a signal in response to a plurality of input signals A, B, and C to the node 11, and receives the respective input signals A, B, and C at the gate. 11 and a plurality of n-type transistors MN11, MN12, and MN13 connected in parallel between the ground voltage supply terminal.

Therefore, when any one of the input signals A, B, and C is activated, the node 11 becomes the ground voltage level.

The precharge unit 11 is composed of a p-type transistor MP13 that is controlled by the precharge signal prech A and precharges the node 12 to the power supply voltage VDD level. That is, it is composed of a pgud transistor MP13 having a precharge signal prech A applied to its gate and a source-drain path connected between the power supply voltage supply node and node 12.

Therefore, when the precharge signal prech A is activated, the node 12 is at the power supply voltage VDD level.

The voltage drop unit 12 substantially constitutes the most important part of the present invention, and is formed between the node 12 and the node 11 to drop the voltage of the node 12 by a predetermined voltage and transmit it to the node 11. The voltage drop section 12 is composed of two n-type transistors MN14 and MN15 connected in series between the node 12 and the node 11, and the threshold voltage (2V) of the two n-type transistors MN14 and MN15 is provided. _The voltage drops by _T ) and is transmitted to node 11. Specifically, the n-type transistor MN14 has a gate connected to a power supply voltage supply source and a source connected to a node 12, and the n-type transistor MN15 has a gate and a source common to the drain of the n-type transistor MN14 described above. And the drain is connected to node 11.

The pull-down section 13 is composed of an n-type transistor MN16 having a node 11 connected to a gate and a source-drain path connected between the node 13 and the ground voltage supply terminal. It plays a role of driving 13 down.

The amplifier 14 is composed of two p-type transistors MP11 and MP12 symmetrically connected to each other. The p-type transistor MP11 has a gate connected to the drain of the p-type transistor MP12 through the node 13. The drain is connected to node 12 and the source is connected to the supply voltage supply. In addition, the p-type transistor MP12 has a gate connected to the drain of the p-type transistor MP11 through a node 13, a drain connected to a furnace 13, and a source connected to a power supply voltage supply terminal.

The output unit 16 is configured as an inverter INV1 having an input terminal connected to the node 13 to provide a final output OUT.

Next, the main functions of the sense amplifier of the present invention having the above configuration will be described in detail.

First, in the sense amplifier of the present invention, as one of two technical means for improving the speed of signal processing, by adding two n-type transistors (MN14, MN15) between node 11 and node 12, all of the plurality of inputs Is inactive and the node voltage Vnode11 at node 11 goes to VDD-2V _T. That is, the voltage level of the node 12 precharged by the power supply voltage VDD drops and is transmitted to the node 11.

Subsequently, when any one of the plurality of input signals is activated and is at the high level, the node voltage Vnode11 at the node 11 becomes the ground level.

Thus, the voltage swing of node 11 is not swinging the full swing (swing between VDD and ground voltage), but swings between (VDD-2V _T ) and ground voltage.

In addition, in the sense amplifier of the present invention, one of two technical means for improving the speed of signal processing is positive through two p-type transistors MP11 and MP12 connected between node 12 and node 13. By forming a feed back, a quick transition between node 12 and node 13 can be achieved.

More specifically, in the sense amplifier of the present invention, when a transition is caused by two p-type transistors MP11 and MP12 connected between the node 12 and the node 13, the voltage at the node 12 and the node 13 can be quickly changed. It is to achieve feedback. In other words, when the voltage of the node 12 decreases, the gate voltage of the p-type transistor MP12 decreases, so that the voltage of the node 13 increases faster, and when the voltage of the node 12 increases, the gate voltage of the p-type transistor MP12 increases. The voltage at node 13 will be lowered faster. As already mentioned above, node 13 also affects node 12, so that node 12 and node 13 progress faster.

As described above, in the sense amplifier according to the present invention, it is possible to decrease the C value and ΔV value at Δt = C 1 / εΔV and increase the current i in the transition period, and consequently improve the speed of signal processing. .

1 is a circuit diagram of an improved sense amplifier for a programmable logic array in accordance with one preferred embodiment of the present invention;

2 is a circuit diagram of a conventional sense amplifier for a programmable logic array.

Explanation of symbols on the main parts of the drawings

10: input unit 12: voltage swing control unit

14 amplification unit 16 output unit

Claims (6)

In a sense amplifier for a programmable logic array, A first node, a second node, and a third node; An input unit configured to provide a signal corresponding to a plurality of input signals to the first node; A precharge unit for precharging the second node with a power supply voltage VDD; A voltage drop unit connected between the second node and the first node to drop the voltage level of the second node by a predetermined level to transfer the voltage level to the first node; A pull-down unit configured to pull down the first node in response to the first node; An amplifying unit connected between the second node and the third node to provide the amplified signal to the third node, and performing a positive feedback to achieve a fast transition of the signal; And Output unit for outputting the signal of the third node to the outside An enhanced sense amplifier for a programmable logic array, comprising: a. The method of claim 1, The amplification unit, A first p-type transistor connected between a power supply voltage supply terminal and the second node and having a gate connected to a third node; And A second p-type transistor connected between a power supply voltage supply terminal and the third node and having a gate connected to the second node An improved sense amplifier for an programmable logic array comprising a. The method of claim 1, And the pull-down part is configured of an n-type transistor having a gate connected to the first node and a source-drain path connected between the third node and a ground voltage supply terminal. The method of claim 1, The voltage drop unit, A first n-type transistor having a gate connected to a power supply voltage supply terminal and a drain connected to the second node; And A second n-type transistor having a gate and a source connected to a drain of the first n-type transistor and a drain connected to the first node An improved sense amplifier for an programmable logic array comprising a. The method of claim 1, And wherein said output portion comprises an inverter having an input coupled to said third node. The method of claim 1, The input unit includes a plurality of n-type transistors connected in parallel between the first node and a ground voltage supply terminal, and a corresponding input signal among the plurality of input signals is applied to each gate of the plurality of n-type transistors. Improved sense amplifier for programmable logic arrays.