KR100394064B1 - Data output buffer circuit - Google Patents

Abstract

PURPOSE: A data output buffer circuit is provided to increase an output speed of the next data by making the impedance of output terminal high after outputting data. CONSTITUTION: A data output buffer circuit includes a memory cell(1), a sense amplifier(2), a synchronous clock generator(3), a latch(4), a precharge clock generator(5), a plurality of NOR gates(NOR1,NOR2). The sense amplifier(2) is used for amplifying output data of the memory cell(1). The synchronous clock generator(3) is used for delaying an external clock signal and generating an internal clock signal. The latch(4) is used for latching output data of the sense amplifier according to a rising edge of the internal clock. The precharge clock generator(5) is used for delaying the external clock signal and outputting a clock to make the impedance of output terminal high after data output period. The NOR gates(NOR1,NOR2) are used for performing a logical OR operation for the output signals of the latch and the precharge clock signal of the precharge clock generator in order to output an operated result to each gate of a first and a second NMOS transistor(NM1,NM2).

Description

Data output buffer circuit {omitted}

The present invention relates to a data output buffer circuit, and more particularly, to a data output buffer circuit that makes only an output after a data output and a high impedance state, and increases the speed when the next data is output.

The conventional data output buffer circuit receives an external clock signal CLK as shown in FIG. 1A and delays the external clock signal CLK to generate an internal clock signal CLK_IO as shown in FIG. 1B , And outputs the output data DOUT as shown in FIG. 1C in synchronism with the rising edge of the internal clock signal CLK_IO. However, when the output data DOUT is inverted from a high state to a low state or inverted from a low state to a high state, that is, when the output data and the next data are inverted and output, The output speed of the output data is delayed at the output terminal of the output buffer circuit, so that the data output speed is decreased, and high-speed data output is not easy.

The output of the conventional data output buffer circuit described above is characterized in that the waveform of the output data DOUT has a long period and no high-impedance (hi-z) state exists between the output waveforms as shown in Fig.

However, in the conventional data output buffer circuit, when the data is output and the next data is inverted and outputted, the data output transition time is long, so that it is difficult to operate at high speed and the noise is generated due to the large peak current at the transition There is a problem that the circuit configuration is complicated in order to solve the problem.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a method and an apparatus for outputting one data, holding the output data for a predetermined output holding time, forcibly putting the output stage into a high- And to provide a data output buffer circuit having a minimum transition time when the data is outputted.

1 is a timing chart of a conventional data output buffer circuit.

2 is a circuit diagram of a data output buffer circuit according to the present invention;

Fig. 3 is a timing chart of a main part in Fig. 2; Fig.

DESCRIPTION OF THE REFERENCE SYMBOLS

1: Memory cell. 2: Sense amplifier.

3: Synchronous clock generator. 4: latch.

5: Precharge clock generator. NOR1, NOR2: Noah Gate.

NM1, NM2: An NMOS transistor.

The above-mentioned object is achieved by outputting the next data after making the output terminal into the high impedance state with the precharge clock generated by the precharge clock generating unit under the control of the continuous output mode after the data is output and the constant output hold time Will be described in detail with reference to the accompanying drawings.

2 is a circuit diagram of a data output buffer circuit according to the present invention. As shown in FIG. 2, a sense amplifier 2 for receiving output data of a memory cell 1 and amplifying the data, an external clock signal CLK, A synchronous clock generating unit 3 for receiving an internal clock signal CLK_IO and generating an internal clock signal CLK_IO for internal synchronization by delaying the received clock signal CLK_IO at a rising edge of an internal clock signal CLK_IO generated by the synchronous clock generating unit 3 A latch 4 for latching the output data of the sense amplifier 2 synchronously and outputting the output data to the output stage, and a latch 4 for delaying the external clock signal CLK to make the output terminal in a high impedance state after the output- A precharge clock generator 5 for outputting the charge clock signal CLK_OPRE and a precharge clock generator 5 for outputting the output signals UP and DN of the latch 4 to precharge clock signals CLK_OPRE) and the Noah combination, (NM1), will be described in detail the operation of the present invention to be configured as a NOR gate (NOR1), (NOR2), configured in this way applied to the gate of the (NM2) as follows.

The data output from the memory cell 1 is amplified by the sense amplifier 2 to increase the signal level ratio because the signal level ratio between the logic '1' signal and the logic '0' signal is very close to the range of two to three And a data input terminal D of the latch 4. The synchronous clock generator 3 for synchronizing the data output buffer circuit receives the external clock signal CLK as shown in FIG. Generates the internal clock signal CLK_IO as shown in FIG. 3B by delaying the signal CLK, and outputs the internal clock signal CLK_IO to the latch 4. The precharge clock generator 5 controlled by the continuous output mode signal BRM delays the external clock signal CLK to maintain the output stage in the high impedance state after the data output hold time, And generates the precharge clock signal CLK_OPRE as shown. When the precharge clock generator 5 is controlled by the continuous output mode signal BRM, the control of the data output buffer circuit is not only facilitated but also controls the CAS latency and the burst length, The consumption of the power required to generate the signal CLK_OPRE can be minimized.

The latch 4 latches the data input from the sense amplifier 2 synchronously with the rising edge of the internal clock signal CLK_IO generated by the synchronous clock generator 3 and outputs the two output signals UP ) And (DN). However, since the precharge clock generator 5 generates the high-potential precharge clock signal CLK_OPRE after the output hold time tOH of the data has elapsed as described above, the precharge clock signal CLK_OPRE is generated during the output hold time tOH The two output signals UP and DN output from the latch 4 are inverted through the NOR gates NOR1 and NOR2 and applied to the gates of the NMOS transistors NM1 and NM2, The output data DOUT corresponding to the output data DOUT is output. That is, when the output signal UP of the latch 4 is outputted at a high potential and the output signal DN is output at a low potential, a low potential is outputted from the NOR gate NOR1 and a high potential is outputted from the NOR gate NOR2 The NMOS transistor NM1 is turned off and the NMOS transistor NM2 is turned on to output the output data DOUT at a low potential and the output signal UP of the latch 4 is outputted at a low potential, The NMOS transistor NM1 is turned on and the NMOS transistor NM2 is turned off to output the output data DOUT at a high potential. When the output data DOUT is output and the output hold time tOH is exceeded, the high charge precharge clock signal CLK_OPRE is output from the new charge clock generator 5 as shown in FIG. 3C. Therefore, the NOR gate NOR1 And NOR2, the NMOS transistors NM1 and NM2 are all turned off, and the output terminal becomes a high impedance state. The value of the output data DOUT is determined from the high impedance state of the output stage in accordance with the output signals UP and DN of the latch 2 as described above since the precharge clock signal CLK_OPRE is low in level And output.

As described above, in the data output buffer circuit according to the present invention, after the data is output and the output hold time has elapsed, the output terminal is made to be in the high impedance state by the precharge clock generated by the precharge clock generator, Since the next data is output, the data output speed is increased by minimizing the output transition time, the peak current is reduced and the noise is less generated, and the circuit is simplified by controlling the precharge clock generator in the continuous output mode, It also has an easy effect.

Claims (2)

A synchronous clock generator for generating an internal clock signal for internal synchronization by receiving and delaying an external clock signal; a synchronous clock generator for generating an internal clock signal for a rising edge of the internal clock generated by the synchronous clock generator; A precharge clock generator for outputting a precharge clock signal for delaying the external clock signal and for putting the output terminal in a high impedance state after a data output hold time, And a NOR gate which applies the output signals UP and DN of the latch to the gates of the NMOS transistors NM1 and NM2 of the output stage in combination with the precharge clock signal of the precharge clock generator, (NOR1) and (NOR2), respectively. The data output buffer circuit according to claim 1, wherein the precharge clock generating unit is subjected to operation control by a continuous output mode signal.