KR100388216B1 - A semiconductor memory device which comprises flash memory cells of multi-level - Google Patents

Abstract

An apparatus for detecting a data level of a multilevel flash memory according to the present invention generates a wide range of data levels by using only a relatively low level of reference current, thereby widening the width of each data level, and error in detecting the data level according to the change of the reference current. The purpose is to prevent. The present invention provides a data level detection apparatus for a multilevel flash memory cell having first to fourth data levels, comprising a reference current generator, a word line voltage generator, and first and second comparators. The reference current generator generates a first reference current and a second reference current. The word line voltage generator generates a first word line voltage higher than the threshold voltages of the first data level and the second data level and a second word line voltage higher than the threshold voltages of the third data level and the fourth data level. The first comparator compares the drain current of the multilevel flash memory cell with the first reference current. The second comparator compares the drain current of the flash memory cell with the second reference current.

Description

A semiconductor memory device comprising a flash memory cell having a multi-level device TECHNICAL FIELD A SEMICONDUCTOR MEMORY DEVICE WHICH COMPRISES FLASH MEMORY CELLS OF MULTI-LEVEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memories, and more particularly to an apparatus for detecting data levels of multilevel flash memory cells.

Flash memory is a type of electrically erasable and programmable ROM (EEPROM), and the erase operation of the data is very fast in blocks rather than bytes, which is very fast. Three or more data levels may be stored in a multilevel flash memory cell among such flash memories. That is, one flash memory cell can store multi-level data. Such a multi-level flash memory requires a separate data level detection device to read data. 1 and 2 are diagrams illustrating an apparatus for detecting a data level of a conventional multilevel flash memory cell. 1 is a graph showing current-voltage characteristics of a data level detection apparatus of a conventional multilevel flash memory cell, and FIG. 2 is a circuit diagram of a data level detection apparatus of a conventional multilevel flash memory cell.

In FIG. 1, the multilevel of the prior art is configured such that the first to fourth data levels Level1 to Level4 are distinguished by one word line voltage V_read and three reference currents Iref1 to Iref3. The first data level Level1 is when the drain current of the memory cell at the word line voltage V_read is greater than the first reference current Iref1 and is between the first reference current Iref1 and the second reference current Iref2. Is a third data level (Level3) between the second data level (Level2), the second reference current (Iref2) and the third reference current (Iref3), the fourth data level (Level4) less than or equal to the third reference current (Iref3) Separate by. The circuit of FIG. 2 constitutes hardware by applying the above concept.

In FIG. 2, the drain current of the memory cell 104 is input to the three comparators 106 as a comparison signal, and each of the three comparators 106 has three reference currents (each generated in the three transistors 102). Iref1 to Iref3) are input as reference signals. The output of each comparator 106 is encoded by the encoder 108 and output as digital logic values d0 to d1 indicating the level.

In such a conventional multi-level flash memory, there is a problem in that a reference current is required between each data level, so that the width of each data level becomes narrow. In addition, as the data level increases, the detection of the data level is performed at a high current level. Therefore, the magnitude of the reference current changes due to the difference in characteristics of each transistor generating the reference current. Increasingly, there is a great difficulty in accurately detecting the cursor data level.

An apparatus for detecting a data level of a multilevel flash memory according to the present invention generates a wide range of data levels by using only a relatively low level of reference current, thereby widening the width of each data level, and error in detecting the data level according to the change of the reference current. The purpose is to prevent.

1 is a graph showing current-voltage characteristics of a data level detection apparatus of a conventional multilevel flash memory cell.

2 is a circuit diagram of a data level detection apparatus of a conventional multilevel flash memory cell.

3 is a graph showing current-voltage characteristics of a data level detection device of a multilevel flash memory cell according to the present invention;

4 is a block diagram of a data level detection apparatus of a multilevel flash memory cell according to the present invention;

Explanation of symbols on the main parts of the drawings

V_read: Wordline voltage 102, 104, 404: Multilevel flash memory cell

106, 406: Comparator 108, 408: Encoder

402: word line voltage generator 410: reference current generator

CTRL: control signal

In order to achieve the above object, the present invention provides a semiconductor memory device including N multilevel flash memory cells, comprising: a reference current generator for generating a first reference current and a second reference current, and the flash memory cell; A word line voltage generator configured to generate a word line voltage for driving the first memory; a first comparator comparing the current of the flash memory cell with the first reference current; and a current of the flash memory cell with the second reference current; It comprises a second comparator. Here, the word line voltage is higher than the threshold voltage of the n-th level, lower than the threshold voltage of the (n + 1) th level, and the first reference current is smaller than the current of the (n-1) th level, and the nth level. Preferably, the second reference current is a current at a level for checking on / off of the flash memory cell. And an encoder for generating a signal indicative of the level of the flash memory cell by encoding the comparison result in the first and second comparators. The data level of the multilevel flash memory according to the present invention. A preferred embodiment of the detection apparatus will be described below with reference to FIGS. 3 and 4. 3 is a graph showing current-voltage characteristics of a data level detection device of a multilevel flash memory cell according to the present invention, and FIG. 4 is a block diagram of a data level detection device of a multilevel flash memory cell according to the present invention. In 3, the first and second data levels Level1 and Level3 and the fourth and fourth data levels Level3 and Level4 are respectively distinguished by two word line voltages V_read1 and V_read2. The first data level Level1 and the second data level Level2 are distinguished from each other by the reference current Iref, and the third data level Level3 and the fourth data level Level4 also belong to the reference current Iref. By each other. The circuit of FIG. 4 constitutes hardware by applying the concept of the present invention as described above.

In FIG. 4, the word line voltage generator 402 generates a first word line voltage V_read1 or a second word line voltage V_read2 by operating by a control signal CTRL provided from an external control system. Output to the gate of cell 404. The memory cell 404 is turned on by one of the two word line voltages V_read1 and V_read2 according to the level of data stored therein to generate a drain current having a magnitude proportional to the data level.

The reference current generator 410 generates a 0 A current signal together with another reference current together with the reference current Iref mentioned in the description of FIG. 3. The first reference current Iref is the reference signal of the second comparator 406b and the second reference current 0A is the reference signal of the first comparator 406a.

The second comparator 406b compares the first reference current Iref with the drain current of the memory cell and outputs the comparison result. The first comparator 406a compares the drain current of the memory cell with the second reference current 0A and outputs the comparison result. First, the first comparator 406a compares the drain current of the memory cell 404 with a reference signal of 0 A to determine whether the memory cell 404 is turned on by the word line voltage V_read. If the memory cell 404 is turned on while the first word line voltage V_read1 is generated in the word line voltage generator 402, the levels of the stored data are the first data level Level1 and the second data level. One of (Level2). If the memory cell 404 is turned on while the second word line voltage V_read2 is generated in the word line voltage generator 402, the levels of the stored data are the third data level (Level3) and the fourth data level ( Level 4). In this manner, the first comparator 406a determines whether the memory cell 404 is turned on to thereby adjust the first and second data levels Level1 (Level2) and the third and fourth data levels (Level3) (Level4). Make a distinction.

The first comparator 406a may distinguish between the first data level Level1 and the second data level Level2 or the third data level Level3 and the fourth data level. Referring to FIG. 3, when the drain current of the memory cell 404 is compared with the first reference current Iref and the drain current is greater than the first reference current Iref, the data level may be the first data level Level1. If one of the third data level Level3 and the drain current is smaller than the first reference current Iref, the data level is one of the second data level Level2 and the fourth data level Level4. . The second comparator 406b further refines the comparison result of the first comparator 406a to detect the data level.

If the drain current is greater than the first reference current Iref while the memory cell 404 is turned on by the first word line voltage V_read1, the stored data is the first data level Level1 and conversely, the drain current. Is smaller than the first reference current Iref, the stored data is the second data level Level2.

If the drain current is greater than the first reference current Iref while the memory cell 404 is turned on by the second word line voltage V_read2, the stored data is the third data level Level3 and conversely, the drain current. Is smaller than the first reference current Iref, the stored data is the fourth data level Level4.

The data level detection apparatus of the multilevel flash memory according to the present invention generates a wide range of data levels by using only a relatively low level reference current, thereby widening the width of each data level, and detecting the data level according to the change of the reference current. It provides the effect of preventing errors.

Claims (3)

A semiconductor memory device comprising a flash memory cell having N multilevels, A reference current generator for generating a first reference current and a second reference current; A word line voltage generator configured to generate a word line voltage for driving the flash memory cell; A first comparator comparing the current of the flash memory cell with the first reference current; A second comparator comparing the current of the flash memory cell with the second reference current; Include, The word line voltage is higher than the threshold voltage of the nth level, lower than the threshold voltage of the (n + 1) th level, and the first reference current is smaller than the current of the (n-1) th level, and of the nth level. A semiconductor memory device, characterized in that greater than the current. The method of claim 1, And the second reference current is a current having a level for checking on / off of the flash memory cell. The method of claim 1, And an encoder for encoding a result of the comparison in the first comparator and the second comparator to generate a signal indicative of the level of the flash memory cell.