KR100385467B1 - Method for manufacturing a contact electrode of semiconductor device - Google Patents
Method for manufacturing a contact electrode of semiconductor device Download PDFInfo
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- KR100385467B1 KR100385467B1 KR10-2001-0036667A KR20010036667A KR100385467B1 KR 100385467 B1 KR100385467 B1 KR 100385467B1 KR 20010036667 A KR20010036667 A KR 20010036667A KR 100385467 B1 KR100385467 B1 KR 100385467B1
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- contact hole
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- diffusion barrier
- interlayer insulating
- contact electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
- H01L21/02362—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment formation of intermediate layers, e.g. capping layers or diffusion barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02131—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being halogen doped silicon oxides, e.g. FSG
Abstract
본 발명은 반도체 장치의 콘택전극 제조방법에 관한 것으로, 특히 이 방법은 반도체 기판 상부에 제 1확산 방지막과, 플로우린이 함유된 층간 절연막과, 제 2확산 방지막을 순차적으로 형성하고, 제 2확산 방지막에서 제 1확산 방지막을 식각해서 설정된 콘택홀보다 소정 폭이 큰 제 1콘택홀을 형성하고 제 1 콘택홀에 캡핑막을 매립하고, 캡핑막을 식각해서 설정된 폭을 갖는 제 2콘택홀을 형성한 후에, 제 2콘택홀에 도전체를 매립하여 콘택전극을 형성한다. 그러므로, 본 발명은 배리어 메탈 및 갭필 공정시 불량이 발생하더라도 캡핑막이 FSG 층간 절연막을 둘러싸고 있기 때문에 플루오린(F)에 의한 콘택 전극의 침투를 방지할 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a contact electrode of a semiconductor device. In particular, the method sequentially forms a first diffusion barrier film, an interlayer insulating film containing fluorine, and a second diffusion barrier film on a semiconductor substrate. After the first diffusion barrier is etched in to form the first contact hole having a predetermined width larger than the set contact hole, the capping film is buried in the first contact hole, and the capping film is etched to form the second contact hole having the set width, A conductor is embedded in the second contact hole to form a contact electrode. Therefore, the present invention can prevent penetration of the contact electrode by fluorine (F) because the capping film surrounds the FSG interlayer insulating film even when defects occur in the barrier metal and gap fill processes.
Description
본 발명은 반도체 제조방법에 관한 것으로서, 특히 콘택홀 내부에 배리어 메탈막(barrier metal)을 형성하기 전에 콘택홀 주변을 절연막으로 캐핑하여FSG(Fluorine doped Silicate Glass) 층간 절연막내에 형성되는 콘택 전극의 플루오린(F)에 의한 침투를 방지할 수 있는 반도체 장치의 콘택전극 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor, and in particular, a fluorine layer of a contact electrode formed in a fluorine doped silicate glass (FSG) interlayer insulating layer by capping around the contact hole with an insulating layer before forming a barrier metal layer in the contact hole. A method for manufacturing a contact electrode of a semiconductor device capable of preventing penetration by lean (F).
반도체 장치는 고집적화에 따라 셀의 크기와 금속 배선의 피치(pitch)가 동시에 감소하게 되었다. 이러한 금속 배선 피치의 감소는 배선 저항을 증가시키며 인접한 배선간에 형성되는 정전용량을 증가시켜 소자로부터 원하는 동작 속도를 획득하는데 어려움이 있었다. 이를 위해 반도체 장치는 2층 이상의 다층 배선을 형성하게 되었으며, 이러한 다층 배선 공정에서 하부 금속 배선 패턴 위에 상부 금속 배선의 패턴을 형성하는데 있어서 전기적인 절연 역할을 하는 층간 절연막의 평탄화 공정이 필수적으로 요구되었다.As semiconductor devices become more integrated, the cell size and the pitch of metal wirings are simultaneously reduced. This reduction in pitch of the metal wiring increases the wiring resistance and increases the capacitance formed between adjacent wirings, making it difficult to obtain a desired operating speed from the device. To this end, the semiconductor device has formed a multi-layer wiring of two or more layers, and in this multi-layer wiring process, a planarization process of an interlayer insulating film, which serves as an electrical insulation, is essential in forming the pattern of the upper metal wiring on the lower metal wiring pattern. .
한편, 반도체 소자의 고집적화에 따라 금속 배선 사이의 간격 또한 축소되는데, 이러한 금속 배선 사이의 단축 거리로 인해 기생 커패시턴스로 인한 시정수(RC) 지연과 전력 소모 감소를 위해 저유전율을 갖는 금속 배선 사이의 층간 절연막 물질이 필요하게 되었다.On the other hand, the gap between metal wirings is also reduced according to the high integration of semiconductor devices. Due to the shorter distance between the metal wirings, the time constant (RC) delay due to parasitic capacitance and the low dielectric constant between metal wirings are reduced to reduce power consumption. There is a need for an interlayer dielectric material.
이러힌 요구에 따라, 층간 절연물질은 유전상수 4이상인 절연 물질인 BPSG(Boro Phospho Silicate Glass), PSG(Phospho Silicate Glass), BSG(Boro Silicate Glass) 대신에 유전상수가 3∼3.5 정도인 FSG(Fluorine doped Silicate Glass)막으로 대체되고 있다. 대개, FSG막은 증착과 식각이 동시에 이루어져 갭필(gap-fill) 능력이 우수한 고밀도 플라즈마의 화학기상증착법(high density plasma chemical vapor deposition: 이하 HDP CVD라 함)을 이용하여 증착된다.According to this requirement, the interlayer insulating material has a dielectric constant of 3 to 3.5 instead of Bos Phospho Silicate Glass (BPSG), Phospho Silicate Glass (PSG), and Boro Silicate Glass (BSG), which have an dielectric constant of 4 or more. Fluorine doped Silicate Glass) is being replaced. Usually, the FSG film is deposited using high density plasma chemical vapor deposition (hereinafter referred to as HDP CVD), which has a good gap-filling ability due to simultaneous deposition and etching.
도 1 내지 도 4는 종래 기술에 의한 반도체 장치의 콘택전극 제조 공정을 순차적으로 나타낸 공정 순서도이다.1 to 4 are process flowcharts sequentially showing a process of manufacturing a contact electrode of a semiconductor device according to the prior art.
도 1에 도시된 바와 같이, 반도체 기판(10)에 반도체 소자 공정을 진행한 후에 금속 배선(12)을 형성하고, 그 위에 제 1확산 방지막(14)을 얇게 증착한다. 그리고 제 1확산 방지막(14) 상부에 HDP CVD로 FSG을 증착하여 층간 절연막(16)을 형성하고, 그 위에 제 2확산 방지막(18)을 적층한 후에, 화학기계적 연마(Chemical Mechanical Polishing: 이하 CMP라 칭함)공정으로 제 2확산 방지막(18)의 표면을 평탄화한다.As shown in FIG. 1, after the semiconductor device process is performed on the semiconductor substrate 10, the metal wiring 12 is formed, and the first diffusion barrier layer 14 is deposited thinly thereon. After the FSG is deposited on the first diffusion barrier film 14 by HDP CVD to form an interlayer insulating film 16 and the second diffusion barrier film 18 is deposited thereon, the chemical mechanical polishing (CMP) is described below. The surface of the second diffusion barrier film 18 is planarized.
그리고 도 2에 도시된 바와 같이, 콘택 마스크를 이용한 사진 및 식각 공정을 진행하여 상기 제 2확산 방지막(18)에서 제 1확산 방지막(14)까지 식각하여 콘택홀(20)을 형성한다. 이 콘택홀(20)에 의해 금속 배선(12)의 표면이 개방된다.As shown in FIG. 2, a contact hole 20 is formed by performing a photolithography and an etching process using a contact mask to etch from the second diffusion barrier layer 18 to the first diffusion barrier layer 14. The surface of the metal wiring 12 is opened by the contact hole 20.
도 3에 도시된 바와 같이, 콘택홀(20)이 형성된 기판에 배리어 메탈막(22)으로서 Ti/TiN을 형성한 후에 도전체 물질로서 텅스텐(W)(24)을 갭필한다.As shown in FIG. 3, after forming Ti / TiN as the barrier metal film 22 on the substrate on which the contact hole 20 is formed, tungsten (W) 24 is gapfilled as a conductor material.
그리고나서 도 4에 도시된 바와 같이, 제 2확산 방지막(18) 표면이 드러날때까지 텅스텐(24) 및 배리어 메탈막(22)을 CMP로 평탄화하여 콘택전극을 형성한다.Then, as shown in FIG. 4, the tungsten 24 and the barrier metal film 22 are planarized with CMP until the surface of the second diffusion barrier film 18 is exposed to form a contact electrode.
그러나, 상기 종래 기술에 의한 콘택전극의 제조 방법에 있어서, 배리어 메탈막(22)과 텅스텐(24)의 증착 공정시 스텝커버리지(step-coverage) 또는 보이드(void) 등의 문제가 발생하게 되면, 도면 부호 26에 도시된 바와 같이 콘택홀에 드러난 FSG 층간 절연막(16)의 플루오린(F)이 콘택전극으로 침투(attack)하게 된다.However, in the method of manufacturing a contact electrode according to the related art, when a problem such as step coverage or void occurs during the deposition process of the barrier metal film 22 and tungsten 24, As shown by reference numeral 26, fluorine F of the FSG interlayer insulating layer 16 exposed in the contact hole penetrates into the contact electrode.
그러므로, 종래에는 층간 절연막(16)으로 FSG막을 사용할 경우 플루오린(F)-침투를 줄이기 위하여 층간 절연막의 플루오린(F)의 농도를 줄이게 된다. 하지만, 플루오린의 농도를 줄일 경우 층간 절연막의 유전 상수가 높아지기 때문에 절연 특성이 저하되는 문제가 있었다.Therefore, when the FSG film is conventionally used as the interlayer insulating film 16, the concentration of fluorine (F) in the interlayer insulating film is reduced to reduce the fluorine (F) -infiltration. However, when the concentration of fluorine is reduced, the dielectric constant of the interlayer insulating film is increased, which causes a problem of deterioration of the insulating properties.
본 발명의 목적은 이와 같은 종래 기술의 문제점을 해결하기 위하여 FSG 층간 절연막이 있는 기판에 설정된 콘택홀보다 넓은 콘택홀을 식각하고 콘택홀에 절연물질의 캡핑막을 매립한 후에 캡핑막에 설정된 크기의 콘택홀을 형성함으로써 배리어 메탈 및 갭필 공정시 불량이 발생하더라도 캡핑막이 FSG 층간 절연막을 둘러싸고 있기 때문에 플루오린(F)에 의한 콘택 전극의 침투를 방지할 수 있는 반도체 장치의 콘택전극 제조방법을 제공하고자 한다.An object of the present invention is to etch a contact hole wider than the contact hole set in the substrate having the FSG interlayer insulating film and to fill the contact hole capping film of the insulating material in order to solve the problems of the prior art, the contact of the size set in the capping film The present invention provides a method for manufacturing a contact electrode of a semiconductor device that can prevent penetration of a contact electrode by fluorine (F) because the capping film surrounds the FSG interlayer insulating film even when defects occur in the barrier metal and gap fill process by forming holes. .
이러한 목적을 달성하기 위하여 본 발명은 반도체 기판 상부에 제 1확산 방지막과, 플로우린이 함유된 층간 절연막과, 제 2확산 방지막을 순차적으로 형성하는 단계와, 제 2확산 방지막에서 제 1확산 방지막을 식각해서 설정된 콘택홀보다 소정 폭이 큰 제 1콘택홀을 형성하고 제 1 콘택홀에 캡핑막을 매립하는 단계와, 캡핑막을 식각해서 설정된 폭을 갖는 제 2콘택홀을 형성하는 단계와, 제 2콘택홀에 도전체를 매립하여 콘택전극을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention sequentially forms a first diffusion barrier, an interlayer insulating film containing fluorine, and a second diffusion barrier on the semiconductor substrate, and etching the first diffusion barrier in the second diffusion barrier. Forming a first contact hole having a predetermined width larger than that of the set contact hole and embedding a capping film in the first contact hole, forming a second contact hole having a set width by etching the capping film, and forming a second contact hole. Embedding a conductor in the to form a contact electrode.
도 1 내지 도 4는 종래 기술에 의한 반도체 장치의 콘택전극 제조 공정을 순차적으로 나타낸 공정 순서도,1 to 4 are process flowcharts sequentially showing a contact electrode manufacturing process of a semiconductor device according to the prior art;
도 5 내지 도 10은 본 발명에 따른 반도체 장치의 콘택전극 제조 공정을 순차적으로 나타낸 공정 순서도.5 to 10 are process flowcharts sequentially showing a process of manufacturing a contact electrode of a semiconductor device according to the present invention.
<도면의 주요부분에 대한 부호의 설명＞<Description of the code | symbol about the principal part of drawing>
100 : 반도체 기판 102 : 도전체 패턴, 도전 영역100 semiconductor substrate 102 conductor pattern, conductive region
104 : 제 1확산 방지막 106 : FSG 층간 절연막104: first diffusion barrier film 106: FSG interlayer insulating film
108 : 제 2확산 방지막 110 : 제 1콘택홀108: second diffusion barrier 110: first contact hole
112 : 캡핑막 114 : 제 2콘택홀112: capping film 114: second contact hole
116 : 배리어 메탈막 118 : 콘택전극116: barrier metal film 118: contact electrode
이하 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.
도 5 내지 도 10은 본 발명에 따른 반도체 장치의 콘택전극 제조 공정을 순차적으로 나타낸 공정 순서도이다.5 to 10 are process flowcharts sequentially illustrating a process of manufacturing a contact electrode of a semiconductor device according to the present invention.
도 5에 도시된 바와 같이, 반도체 기판(102)에 반도체 소자 공정을 진행한 후에 금속 배선(102)을 형성하고, 그 위에 제 1확산 방지막(104)을 얇게 증착한다. 그리고 제 1확산 방지막(104) 상부에 HDP CVD로 FSG을 증착하여 층간 절연막(106)을 형성하고, 그 위에 제 2확산 방지막(108)을 두껍게 적층한 후에, CMP 공정으로 제 2확산 방지막(108)의 표면을 평탄화한다.As shown in FIG. 5, after the semiconductor device process is performed on the semiconductor substrate 102, a metal wiring 102 is formed, and a first diffusion barrier film 104 is deposited thereon. Then, the FSG is deposited on the first diffusion barrier film 104 by HDP CVD to form an interlayer insulating film 106, and the second diffusion barrier film 108 is thickly stacked thereon, and then the second diffusion barrier film 108 is formed by a CMP process. Planarize).
그리고 도 6에 도시된 바와 같이, 제 2확산 방지막(108)에서 제 1확산 방지막(104)을 식각해서 설정된 콘택홀의 선폭보다 소정 폭이 넓은 제 1콘택홀(110)을 형성한다. 이때, 제 1콘택홀(110)과 설정된 콘택홀의 폭 차이는 이후 층간 절연막(106)의 플루오린(F)이 콘택홀로 침투되는 것을 막기 위한 캡핑막이 남는 부분이다.As shown in FIG. 6, the first diffusion barrier layer 104 is etched from the second diffusion barrier layer 108 to form a first contact hole 110 having a predetermined width wider than the line width of the contact hole. In this case, the width difference between the first contact hole 110 and the set contact hole is a portion in which a capping film for preventing the fluorine F of the interlayer insulating layer 106 from penetrating into the contact hole remains.
그 다음 도 7에 도시된 바와 같이, 제 1 콘택홀(110)에 캡핑막(capping layer) (112)을 매립하고 그 표면을 CMP로 평탄화한다. 이때, 캡핑막(112)은 산화 또는 질화물질을 포함한 절연 물질이다.Then, as shown in FIG. 7, a capping layer 112 is embedded in the first contact hole 110 and the surface thereof is planarized with CMP. In this case, the capping layer 112 is an insulating material including an oxidized or nitride material.
이어서 도 8에 도시된 바와 같이, 캡핑막(112)에 실제 콘택 마스크를 이용한 사진 및 식각 공정을 진행하여 캡핑막(112)을 식각해서 설정된 콘택홀의 폭을 갖는 제 2콘택홀(114)을 형성한다. 이로 인해, 제 2콘택홀(114)에 의해 금속 배선(102)의 표면이 개방된다.Subsequently, as shown in FIG. 8, the capping layer 112 is subjected to a photo-etching process using an actual contact mask and an etching process to etch the capping layer 112 to form a second contact hole 114 having a width of the contact hole. do. As a result, the surface of the metal wiring 102 is opened by the second contact hole 114.
그 다음 도 9에 도시된 바와 같이, 제 2콘택홀(114)이 형성된 기판에 배리어메탈막(116)으로서 Ti/TiN을 형성한다.Next, as shown in FIG. 9, Ti / TiN is formed as a barrier metal film 116 on the substrate on which the second contact hole 114 is formed.
그리고나서 도 10에 도시된 바와 같이, 배리어 메탈막(116)이 형성된 제 2콘택홀(114)에 도전체 물질로서 텅스텐(W)(118)을 갭필하고, 제 2확산 방지막(108) 표면이 드러날때까지 텅스텐(118) 및 배리어 메탈막(116)을 CMP로 평탄화하여 콘택전극을 형성한다. 이때, 텅스텐 콘택전극(118)의 둘레에는 캡핑막(112)이 있기 때문에 FSG 층간 절연막(106)의 플루오린(F)이 콘택홀로 침투되는 것을 막을 수 있다.Then, as shown in FIG. 10, a tungsten (W) 118 is gap-filled into the second contact hole 114 in which the barrier metal film 116 is formed, and the surface of the second diffusion barrier 108 is formed. The tungsten 118 and the barrier metal film 116 are planarized with CMP until exposed to form a contact electrode. In this case, since the capping layer 112 is formed around the tungsten contact electrode 118, the fluorine F of the FSG interlayer insulating layer 106 may be prevented from penetrating into the contact hole.
이상 설명한 바와 같이, 본 발명은 FSG 층간 절연막이 있는 기판에 설정된 콘택홀보다 넓은 콘택홀을 식각하고 콘택홀에 절연물질로 캡핑막을 매립한 후에 캡핑막에 설정된 콘택홀을 형성함으로써 배리어 메탈 및 갭필 공정시 불량이 발생하더라도 캡핑막이 FSG 층간 절연막을 둘러싸고 있기 때문에 플루오린(F)에 의한 콘택 전극의 침투를 방지할 수 있다.As described above, in the present invention, a barrier metal and a gapfill process are formed by etching a contact hole wider than a contact hole set in a substrate having an FSG interlayer insulating film, and filling a capping film with an insulating material in the contact hole, and then forming a contact hole set in the capping film. Even when a defect occurs, the capping film surrounds the FSG interlayer insulating film, so that penetration of the contact electrode by fluorine (F) can be prevented.
그러므로, 본 발명은 층간 절연막의 물질로 FSG를 사용할 경우 콘택홀로의 플루오린(F) 침투를 막기 때문에 FSG 층간 절연막의 플루오린(F)의 농도를 높여 층간 절연막의 유전 상수를 향상시킬 수 있는 효과가 있다.Therefore, the present invention prevents the penetration of fluorine (F) into the contact hole when the FSG is used as the material of the interlayer insulating film, thereby increasing the concentration of fluorine (F) of the FSG interlayer insulating film to improve the dielectric constant of the interlayer insulating film. There is.
한편, 본 발명은 상술한 실시예에 국한되는 것이 아니라 후술되는 청구범위에 기재된 본 발명의 기술적 사상과 범주내에서 당업자에 의해 여러 가지 변형이 가능하다.On the other hand, the present invention is not limited to the above-described embodiment, various modifications are possible by those skilled in the art within the spirit and scope of the present invention described in the claims to be described later.
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| KR100385467B1 true KR100385467B1 (en) | 2003-05-27 |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08288391A (en) * | 1994-11-30 | 1996-11-01 | Samsung Electron Co Ltd | Wiring formation of semiconductor element |
| US6008118A (en) * | 1997-12-19 | 1999-12-28 | United Microelectronics Corp. | Method of fabricating a barrier layer |
| KR20010003789A (en) * | 1999-06-25 | 2001-01-15 | 김영환 | Method of forming an inter-layer insulating film in a semiconductor device |
| KR20010005270A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Fabricating method for semiconductor device |
| US6232217B1 (en) * | 2000-06-05 | 2001-05-15 | Chartered Semiconductor Manufacturing Ltd. | Post treatment of via opening by N-containing plasma or H-containing plasma for elimination of fluorine species in the FSG near the surfaces of the via opening |
| KR20010050830A (en) * | 1999-10-04 | 2001-06-25 | 니시무로 타이죠 | Semiconductor device and method of manufacturing the same |
| US6294832B1 (en) * | 2000-04-10 | 2001-09-25 | National Science Council | Semiconductor device having structure of copper interconnect/barrier dielectric liner/low-k dielectric trench and its fabrication method |
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2001
- 2001-06-26 KR KR10-2001-0036667A patent/KR100385467B1/en not_active IP Right Cessation
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08288391A (en) * | 1994-11-30 | 1996-11-01 | Samsung Electron Co Ltd | Wiring formation of semiconductor element |
| US6008118A (en) * | 1997-12-19 | 1999-12-28 | United Microelectronics Corp. | Method of fabricating a barrier layer |
| KR20010003789A (en) * | 1999-06-25 | 2001-01-15 | 김영환 | Method of forming an inter-layer insulating film in a semiconductor device |
| KR20010005270A (en) * | 1999-06-30 | 2001-01-15 | 김영환 | Fabricating method for semiconductor device |
| KR20010050830A (en) * | 1999-10-04 | 2001-06-25 | 니시무로 타이죠 | Semiconductor device and method of manufacturing the same |
| US6294832B1 (en) * | 2000-04-10 | 2001-09-25 | National Science Council | Semiconductor device having structure of copper interconnect/barrier dielectric liner/low-k dielectric trench and its fabrication method |
| US6232217B1 (en) * | 2000-06-05 | 2001-05-15 | Chartered Semiconductor Manufacturing Ltd. | Post treatment of via opening by N-containing plasma or H-containing plasma for elimination of fluorine species in the FSG near the surfaces of the via opening |
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