KR100379539B1 - Semiconductor package and method for fabricating the same - Google Patents

Abstract

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package and a method for manufacturing the same, which are suitable for manufacturing a wafer-level stacked package that is easy to respond to changes in chip size.

The semiconductor package for achieving the above object is a plurality of bonding pads arranged in one direction on the center portion of the upper surface of each of the plurality of unit semiconductor chips, the plurality of unit semiconductor chips on the excluding the lower surface of the bonding pad and the plurality of unit semiconductor chips A conductive layer formed on the conductive layer, a lead partially contacting the conductive layer on both sides of the bonding pad of one of the plurality of unit semiconductor chips on which the bonding pad and the conductive layer are formed; And a plurality of unit semiconductor chips which are sequentially stacked such that a conductive layer having bonding pads of each unit semiconductor chip is formed on a lower surface of the first and the plurality of unit semiconductor chips.

Description

Semiconductor package and manufacturing method therefor {SEMICONDUCTOR PACKAGE AND METHOD FOR FABRICATING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a semiconductor package. In particular, when manufacturing a stacked chip size package (CSP) in the form of a lead manufactured at a wafer level, the semiconductor package and its fabrication can be easily applied and easily mounted. It is about a method.

In general, the packaging technology for integrated circuits in the semiconductor industry continues to evolve to meet the demand for miniaturization and mounting reliability.

The demand for miniaturization is accelerating the development of packages that are close to chip-scale, and the demand for mounting reliability has highlighted the importance of package manufacturing technology that can improve the efficiency of mounting work and the mechanical and electrical reliability after mounting. .

A semiconductor package according to the related art will now be described with reference to the accompanying drawings.

1 is a cross-sectional view illustrating a structure of a conventional semiconductor package.

The conventional semiconductor package has a structure in which an upper and a lower package are stacked.

In this case, the lower package includes a lead frame 2 stacked on a part of the wafer 1, a bonding wire 3 connecting the bonding pad in the center of the wafer 1 and the inner lead of the lead frame 2, and the lead. It consists of a molding resin (4) molded to surround the wafer (1), the lead frame (2), the bonding wire (3) so that a part of the frame (2) is exposed, and the upper package is the same as the lower package. .

Here, the lower package and the upper package are stacked in contact with one surface of each lead frame 2.

The conventional semiconductor package as described above has the following problems.

First, if the chip size is changed, a separate package manufacturing process is required to cope with this and equipment is required, thereby reducing production efficiency.

Second, if the chip is shrinking, a separate substrate is required.

Disclosure of Invention The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor package and a method for manufacturing the same, which are particularly suitable for manufacturing a wafer-level stacked package that is easy to respond to changes in chip size.

1 is a cross-sectional view showing a structure of a conventional semiconductor package

2 is a cross-sectional view illustrating a structure of the semiconductor package according to the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with an embodiment of the present invention.

4A through 4H are cross-sectional views illustrating a method of manufacturing a semiconductor package in accordance with an embodiment of the present invention.

FIG. 5 is a process diagram of manufacturing a laminated CSP by combining the unit structures of FIGS. 3D and 4H. FIG.

Explanation of symbols for the main parts of the drawings

31 wafer 31a, 31b unit semiconductor chip

31a-1, 31a-2, 31a-3, 31a-4: first to fourth unit semiconductor chips

32: bonding pad 33: saw blade (saw blade)

34: cut part 35: metal layer

36: first photosensitive film 37: base metal layer

38: solder lead layer 39: second photosensitive film

A semiconductor package according to the present invention for achieving the above object includes a plurality of bonding pads arranged in one direction on a central portion of a plurality of unit semiconductor chips, and the plurality of bonding pads except for the bonding pads and the lower surfaces of the plurality of unit semiconductor chips. A conductive layer formed on the unit semiconductor chip, and a lead partially protruding in contact with the conductive layers on both sides of the bonding pad of one of the plurality of unit semiconductor chips on which the bonding pad and the conductive layer are formed ( lead) and a plurality of unit semiconductor chips which are sequentially stacked such that a conductive layer having bonding pads of each unit semiconductor chip is formed on the lower surfaces of the first and the plurality of unit semiconductor chips.

The method of manufacturing a semiconductor package according to the present invention having the above structure has a first bonding pad arranged in one direction on a central portion of an upper surface of a first semiconductor chip, and has a front surface excluding the first bonding pad and a lower surface of the first semiconductor chip. A first step of forming a first unit semiconductor chip having a first conductive layer on the side of the first bonding pad, the first unit semiconductor chip having a lead protruding outwardly in contact with the first conductive layer on both sides of the first bonding pad, A second step of forming a plurality of unit semiconductor chips having a plurality of second bonding pads arranged in one direction at a central portion thereof and having a second conductive layer on a front surface of the second bonding pad except for a lower surface of the second semiconductor chip; A second bonding pad and a second conductive layer of one of the plurality of unit semiconductor chips formed by the second step on the bottom surface of the first unit semiconductor chip formed by the first step A second bonding pad and a second bonding pad of one unit semiconductor chip of the plurality of unit semiconductor chips formed by the second step on the bottom surface of the stacked unit semiconductor chip formed by the third step and the third step of laminating And a fourth step of laminating the conductive layer so as to contact the conductive layer.

Referring to the accompanying drawings, a semiconductor package and a method of manufacturing the present invention will be described.

2 is a structural cross-sectional view of a semiconductor package of the present invention.

3A to 3D are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention, and FIGS. 4A to 4H are cross-sectional views illustrating a method of manufacturing a semiconductor package according to an exemplary embodiment of the present invention.

FIG. 5 is a process diagram of manufacturing a laminated CSP by combining the unit structures of FIGS. 3D and 4H.

The semiconductor package of the present invention includes a stacked chip size package (CSP) in the form of a lead manufactured at the wafer level, and a laminated CSP having an external protruding lead attached to the rearranged bond pad layer.

More specifically, as shown in FIG. 2, four first to fourth unit semiconductor chips 31a-1, 31a-2, 31a-3, and 31a-4 are stacked.

At this time, a plurality of bonding pads 32 are formed in one direction at the center of the upper surface of each unit semiconductor chip.

In the first unit semiconductor chip 31a-1, the metal layer 35 is formed to surround the surface of the semiconductor chip 31a except for the bottom surface of the bonding pad 32 and the semiconductor chip 31a-1. In addition, one surface is in contact with the metal layers 35 on both sides of the bonding pad 32 and has a lead protruding outward to have a symmetrical configuration.

At this time, the outer protruding lead is composed of a barrier metal layer 37 in contact with the metal layer 35 and a solder lead layer 38 formed on the barrier metal layer 37.

The second, third, and fourth unit semiconductor chips 31a-2, 31a-3, and 31a-4 are stacked to contact the bottom surface of the first unit semiconductor chip 31a-1. At this time, the metal layer 35 formed on the side surface of each unit semiconductor chip is protruded to the outside, and the surface on which the bonding pads 32 are formed is stacked so as to be in contact with the bottom surface of another semiconductor chip.

In the above description, a configuration in which four unit semiconductor chips are stacked is described, but a plurality of semiconductor chips can be stacked to form a wafer-level CSP.

In the method for manufacturing the semiconductor package of the present invention having the above structure, first, as shown in FIG. 3A, a plurality of bonding pads 32 are formed on a predetermined upper portion of the wafer 31 in one line direction.

In this case, the bonding pads 32 are formed in plural so as to be arranged in one direction on the central portion of the upper surface of the unit chip to be cut by the scribe lane (S / L) during the sawing process.

As shown in FIG. 3B, the sawing process 34 is a scribe lane on the wafer 31 using a saw blade 33 so that the wafer 31 remains a predetermined thickness (see FIG. 3B). Half Cut Saw Process A cut portion 34 is formed.

Thereafter, as shown in FIG. 3C, a metal layer 35 for pad repositioning is deposited on the wafer 31 including the wafer 31 subsequently sawed.

Although not shown in the drawing, the photoresist is coated on the entire surface, and the photoresist is selectively patterned by an exposure and development process so that only the bonding pad 32 is exposed. The metal layer 35 formed on the bonding pad 32 is removed using the patterned photoresist as a mask.

Thereafter, as illustrated in FIG. 3D, the back surface of the wafer 31 is ground to be removed to the metal layer 35 formed under the sawed wafer 31 and separated into unit semiconductor chips 31a and 31b, respectively.

A plurality of unit semiconductor chips are manufactured by the above method.

Next, FIGS. 4A and 4C are manufactured by the same process as FIGS. 3A and 3C.

Subsequently, after the first photoresist layer 36 is coated on the rearranged metal layer 35 as illustrated in FIG. 4D, the bonding pad 32 and the sawed wafer 31 and the metal layer 35 adjacent thereto are formed. The first photosensitive film 36 is selectively patterned by an exposure and development process so as to remain on top (to have the form of an external protruding lead to be formed later).

The base metal layer 37 is sputtered and deposited on the patterned first photoresist layer 36 and the exposed metal layer 35, and the solder lead layer 38 is electroplated. .

Next, as illustrated in FIG. 4E, a second photosensitive film 39 is applied to the entire surface of the solder lead layer 38, and the bonding pad 32 and the solder lead layer 38 on the upper portion of the region adjacent thereto are sawed and wafer 31. The second photosensitive film 39 is selectively patterned by an exposure and development process so that the upper solder lead layer 38 is exposed. At this time, the metal layer 35 on the side of the sawed wafer 31 is not exposed.

Thereafter, as illustrated in FIG. 4F, the solder lead layer 38 and the base metal layer 37 are sequentially etched using the patterned second photoresist layer 39 to expose the first photoresist layer 36.

As shown in FIG. 4G, the first and second photosensitive films 36 and 39 are removed to form an external protruding lead composed of the base metal layer 37 and the solder lead layer 38.

The height of the external protruding lead may be changed by adjusting the height of the first photosensitive film 36. In addition, the first photosensitive film 36 is used for an elastomer.

In order to maintain the strength of the external protruding lead, a solder lead containing a large amount of tin may be used.

Subsequently, as shown in FIG. 4H, the back surface of the wafer 31 is ground to remove the metal layer 35 formed under the sawed wafer 31 so that the unit semiconductor chips 31a and 31b each have an external protruding lead. Separate with).

Next, as shown in Figs. 5A and 5B, as shown in Fig. 5C.

A stacked wafer level CSP (WLCSP: Wafer Level Chip Size Package) is formed by stacking the unit semiconductor chip 31a having the outer protruding lead manufactured in FIG. 4H and the unit semiconductor chip 31a manufactured in FIG. 3D.

At this time, the unit semiconductor chip 31a having the external protruding lead is positioned at the bottom thereof, and the side surface of the semiconductor chip 31a stacked on the wafer and the bonding pad and finally laminated on the metal layer 35 exposed to the outside. Are connected to each other.

The semiconductor package of the present invention and its manufacturing method as described above have the following effects.

First, since the package is a lead type rather than a ball grid array type, solder joint reliability is excellent.

Second, since it is a chip size package (CSP) (wafer level package), it is possible to reduce the process time required to manufacture the package.

Third, it is easy to respond to chip size change by applying a wafer level manufacturing process.

Fourth, since the FAB process is manufactured, it is easy to apply a fine pitch.

Fifth, it is easy to standardize the outer protruding lead.

Claims (7)

A plurality of bonding pads arranged in one direction on a central portion of the upper surface of each of the plurality of unit semiconductor chips; Conductive layers formed on the plurality of unit semiconductor chips excluding the bonding pads and lower surfaces of the plurality of unit semiconductor chips; A lead that partially contacts the conductive layer on both sides of the bonding pad of the first unit semiconductor chip of the plurality of unit semiconductor chips in which the bonding pad and the conductive layer are formed; And a plurality of unit semiconductor chips which are sequentially stacked such that a conductive layer having bonding pads of each unit semiconductor chip is formed on a lower surface of the first and the plurality of unit semiconductor chips. The semiconductor package of claim 1, wherein the lead comprises a base metal layer in contact with the conductive layer and a solder lead layer formed on the base metal layer. The first bonding pad is arranged in a central portion of the upper surface of the first semiconductor chip in one direction, and has a first conductive layer on the entire surface except the first bonding pad and the lower surface of the first semiconductor chip, and the first bonding pad A first step of forming a first unit semiconductor chip having leads protruding outwardly and partially in contact with the first conductive layers on both sides; A plurality of unit semiconductor chips having a plurality of second bonding pads arranged in one direction on a central portion of the upper surface of the second semiconductor chip, and having a second conductive layer on the entire surface except for the lower surface of the second bonding pad and the second semiconductor chip. Forming the second step, A second stacking layer formed on the lower surface of the first unit semiconductor chip formed by the first step such that the second bonding pad and the second conductive layer of one unit semiconductor chip of the plurality of unit semiconductor chips formed by the second step contact each other; 3 steps, A fourth layer laminated on the bottom surface of the stacked unit semiconductor chip formed by the third step such that the second bonding pad and the second conductive layer of one of the plurality of unit semiconductor chips formed by the second step contact each other; A method of manufacturing a semiconductor package, characterized in that it comprises a step. The method of claim 3, wherein the first step of forming the first unit semiconductor chip is performed. Forming a plurality of first bonding pads on a predetermined portion of the wafer, Swinging a predetermined thickness of the wafer with the first bonding pad in the center, Forming a first conductive layer on the sawed wafer except for the first bonding pad, Forming a first photoresist pattern on the sawed wafer and the first conductive layer adjacent thereto and on the first bonding pad and the first conductive layer adjacent thereto; Sequentially forming a base metal layer and a solder lead layer on the front surface; Etching the base metal layer and the solder lead layer using a second photoresist pattern that exposes the first bonding pad and the solder lead layer over the adjacent region and the solder lead layer over the sawed wafer; Removing the first and second photoresist patterns to form protruding leads; And grinding the lower surface of the wafer and the first conductive layer under the sawed wafer to form a first unit semiconductor chip. The method of claim 3, wherein the second step of forming a plurality of the unit semiconductor chip Forming a plurality of second bonding pads on a predetermined portion of the wafer, Swinging a predetermined thickness of the wafer with the second bonding pad at the center; Forming a second conductive layer on the sawed wafer except for the second bonding pad, And forming a plurality of unit semiconductor chips by polishing the lower surface of the wafer and the second conductive layer under the sawed wafer to form a plurality of unit semiconductor chips. The method of claim 4, wherein the base metal layer is formed by a sputtering process, and the solder lead layer is formed by electroplating. 5. The method of claim 4, wherein the height of the external protrusion lead is adjusted by adjusting a height of the first photoresist pattern.