KR20040061608A - Method for fabricating stacked package - Google Patents

Method for fabricating stacked package Download PDF

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Publication number
KR20040061608A
KR20040061608A KR1020020087889A KR20020087889A KR20040061608A KR 20040061608 A KR20040061608 A KR 20040061608A KR 1020020087889 A KR1020020087889 A KR 1020020087889A KR 20020087889 A KR20020087889 A KR 20020087889A KR 20040061608 A KR20040061608 A KR 20040061608A
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KR
South Korea
Prior art keywords
bonding pad
semiconductor chip
package
bonding
single package
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Application number
KR1020020087889A
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Korean (ko)
Inventor
최신
Original Assignee
주식회사 하이닉스반도체
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Priority to KR1020020087889A priority Critical patent/KR20040061608A/en
Publication of KR20040061608A publication Critical patent/KR20040061608A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE: A method for fabricating a stacked package is provided to embody a large-capacity memory by stacking a package of a wafer-level chip size on a semiconductor chip, and to fabricate high-integrated memory module and shorten an electrical junction path by reducing a mounting area. CONSTITUTION: The first semiconductor chip(300) has the first bonding pad(302). An insulation layer is formed on the first semiconductor chip, exposing the first bonding pad. A metal interconnection is formed on the insulation layer, covering the first bonding pad. A single package is formed on the insulation layer, including both a metal interconnection covering the first bonding pad and a ball land connected to the metal interconnection. The second semiconductor chip having the second bonding pad is prepared. Each single package is placed on the second semiconductor chip in both directions with respect to the second bonding pad. The second bonding wire electrically connects the second bonding pad with the ball land of the single package. The bonding wire and the second semiconductor chip are covered with a molding material(306). Conductive balls(308) are attached to the ball land.

Description

적층 패키지의 제조 방법{METHOD FOR FABRICATING STACKED PACKAGE}Manufacturing method of laminated package {METHOD FOR FABRICATING STACKED PACKAGE}

본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는 웨이퍼 상태에서 반도체 칩 마운트(mount), 와이어 본딩 및 쏘잉 공정을 진행하여 적층 패키지를 제조하는 방법에 관한 것이다.The present invention relates to a semiconductor package, and more particularly, to a method of manufacturing a laminated package by performing a semiconductor chip mount, wire bonding and sawing process in a wafer state.

적층 패키지는 IT 분야의 시스템들이 고기능의 소형화되고 이동가능하게 되는 환경에 적용하려는 것으로서, 웨이퍼 레벨 칩을 사용하여 메모리 칩 적층을 통한 대용량, 고집적화 기술로 공정을 단순화하고 저비용으로 대용량화를 추구할 수 있다.The stack package is intended to be applied to the environment in which IT systems are miniaturized and mobile with high performance. The wafer-level chip can be used to simplify the process with high-capacity and high-integration technology through memory chip stacking, and to pursue high-capacity at low cost. .

도 1은 종래 기술에 따른 적층 패키지의 제조 방법을 설명하기 위한 단면도이다.1 is a cross-sectional view illustrating a method of manufacturing a laminated package according to the prior art.

종래 기술에 따른 적층 패키지의 제조 방법은, 도 1에 도시된 바와 같이, 단품의 패키지를 2개 이상 적층 시킨다.In the method of manufacturing a laminated package according to the prior art, two or more packages of a single product are laminated as shown in FIG. 1.

상기 단품의 패키지 구조는 반도체 칩(10)(20)과, 반도체 칩(10)(20)이 안착되며, 다수의 이너 리드(3)(7)가 구비된 리드프레임(1)(5)과, 반도체 칩(10)(20)과 이너 리드(3)(7) 간을 전기적으로 연결시키는 본딩와이어(12)(22)와, 반도체 칩(10)(20) 및 본딩와이어(12)(22)을 덮는 몰딩체(32)(30)로 구성된다. 이때, 미설명된 도면 부호 34, 36은 리드가 연장된 형태로 리드와 차별화하여 아웃리드라 칭한다.The package structure of the single product includes a lead frame (1) 5 and a semiconductor chip 10 (20), a semiconductor chip (10) 20, and a plurality of inner leads (3) (7). Bonding wires 12 and 22 electrically connecting the semiconductor chips 10 and 20 to the inner leads 3 and 7, and the semiconductor chips 10 and 20 and the bonding wires 12 and 22, respectively. It is composed of a molding body 32, 30 covering (). In this case, reference numerals 34 and 36 which are not described are referred to as outleads to differentiate the lead from the lead in an extended form.

그러나, 종래의 기술은 실장 면적이 넓고 높이 또한 높아 경박단소화를 추구하는 패키지 기술에 역행한다. 또한, 제조 공정이 복잡하고, 패키지 간의 전기적 접합 경로가 길어서 고속 디바이스 제품에 부적합한 문제점이 있었다.However, the conventional technique is contrary to the package technique that pursues light and small size with a large mounting area and high height. In addition, the manufacturing process is complicated, and the electrical bonding path between packages is long, which is not suitable for high-speed device products.

이에 본 발명은 상기 종래의 문제점을 해결하기 위해 안출된 것으로, 실장 면적을 최소화하여 경박단소에 적합하고 전기적 경로를 줄여 고속의 디바이스 제품에 적합하도록 한 적층 패키지의 제조 방법을 제공함에 그 목적이 있다.Accordingly, an object of the present invention is to provide a manufacturing method of a laminated package that is suitable for light and thin components by minimizing the mounting area and to reduce the electrical path so as to be suitable for high-speed device products. .

도 1은 종래 기술에 따른 적층 패키지의 제조 방법을 설명하기 위한 단면도.1 is a cross-sectional view for explaining a method for manufacturing a laminated package according to the prior art.

도 2a 내지 도 2g는 본 발명에 따른 단품의 패키지 제조 과정을 설명하기 위한 단면도.Figures 2a to 2g is a cross-sectional view for explaining a package manufacturing process of a single unit according to the present invention.

도 3 내지 도 6은 본 발명에 따른 적층 패키지의 제조 방법을 설명하기 위한 단면도.3 to 6 are cross-sectional views for explaining a method for manufacturing a laminated package according to the present invention.

상기 목적을 달성하기 위한 적층 패키지의 제조 방법은 제 1본딩 패드를 구비한 제 1반도체 칩과, 제 1반도체 칩 상에 형성되며 제 1본딩 패드를 노출시키는 절연막과, 절연막 상에 제 1본딩 패드를 덮는 금속 배선 및 금속 배선과 연결되는볼랜드를 구비한 단품 패키지를 각각 제공하는 단계와, 제 2본딩 패드를 구비한 제 2반도체 칩을 제공하는 단계와, 제 2반도체 칩 상에 제 2본딩 패드를 기준으로 하여 양방향에 각각의 단품 패키지를 안착시키는 단계와, 제 2본딩 패드와 단품 패키지의 볼랜드를 전기적으로 연결시키는 제2본딩와이어를 형성하는 단계와, 본딩와이어 및 제 2반도체 칩을 덮는 몰딩체를 형성하는 단계와, 볼랜드에 도전성 볼을 부착시키는 단계를 포함한 것을 특징으로 한다.In order to achieve the above object, a method of manufacturing a laminated package includes a first semiconductor chip having a first bonding pad, an insulating film formed on the first semiconductor chip and exposing the first bonding pad, and a first bonding pad on the insulating film. Providing a single package having a metal wiring covering the metal wiring and a ball land connected to the metal wiring, providing a second semiconductor chip having a second bonding pad, and a second bonding pad on the second semiconductor chip. Seating each unit package in both directions, forming a second bonding wire electrically connecting the second bonding pad and the borland of the unit package, and a molding covering the bonding wire and the second semiconductor chip. Forming a sieve and attaching conductive balls to the ball lands.

본 발명에서는 실장면적을 최소화하기 위하여 볼 그리드 어레이 타입의 웨이퍼 레벨 칩 규모 패키지를 형성한다.In the present invention, a wafer level chip scale package of a ball grid array type is formed to minimize the mounting area.

이하, 본 발명의 바람직한 실시예를 첨부된 도면을 참조하여 상세히 설명하면 다음과 같다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 2a 내지 도 2g는 본 발명에 따른 단품의 패키지 제조 과정을 설명하기 위한 단면도이다.2A to 2G are cross-sectional views illustrating a manufacturing process of a single piece product according to the present invention.

먼저, 단품의 패키지 제조 과정을 알아보면 다음과 같다.First, the manufacturing process of a single product is as follows.

도 2a에 도시된 바와 같이, 웨이퍼(100) 위에 각각의 본딩패드(102)를 노출시키는 제 1절연막(104)을 형성한 다음, 도 2b에 도시된 바와 같이, 상기 구조를 덮되, 본딩 패드(102)를 노출시키는 제 2절연막(106)을 형성한다.As shown in FIG. 2A, a first insulating film 104 is formed on the wafer 100 to expose each bonding pad 102. Then, as shown in FIG. 2B, the structure is covered, but the bonding pad ( A second insulating film 106 exposing the 102 is formed.

이어, 도 2c에 도시된 바와 같이, 상기 결과의 웨이퍼 상에 제 2절연막(106) 및 본딩 패드(102)를 덮는 제 1금속 배선(108)을 형성한다. 그런 다음, 상기 제 1금속 배선(108)을 포함한 웨이퍼 전면에 제 1감광막(110)을 도포한다.Next, as shown in FIG. 2C, a first metal wiring 108 covering the second insulating film 106 and the bonding pad 102 is formed on the resulting wafer. Thereafter, the first photosensitive film 110 is coated on the entire surface of the wafer including the first metal wire 108.

이 후, 도 2d에 도시된 바와 같이, 상기 제 1감광막을 노광 및 현상하여 본딩 패드와 대응된 부분을 노출시키는 제 1감광막 패턴(110a)을 형성한다.Thereafter, as illustrated in FIG. 2D, the first photoresist layer is exposed and developed to form a first photoresist layer pattern 110a exposing portions corresponding to the bonding pads.

이어, 도 2e에 도시된 바와 같이, 상기 감광막 패턴(110a)를 마스크로 하고 상기 웨이퍼 전면에 스퍼터링 공정에 의해 구리(Cu)막을 증착하고 나서, 제 1감광막 패턴(110a)의 노출된 부분에 잔류되는 구리(Cu) 패턴(112)을 형성한다.Subsequently, as shown in FIG. 2E, a copper (Cu) film is deposited on the entire surface of the wafer by using the photoresist pattern 110a as a mask, and then remains on an exposed portion of the first photoresist pattern 110a. A copper (Cu) pattern 112 is formed.

그런 다음, 제 1감광막 패턴을 제거한 다음, 도 2f에 도시된 바와 같이, 상기 구리(Cu) 패턴(112)을 포함한 웨이퍼 전면에 제 3절연막(114)을 형성한다.Thereafter, after removing the first photoresist pattern, a third insulating layer 114 is formed on the entire surface of the wafer including the copper (Cu) pattern 112.

이 후, 도 2g에 도시된 바와 같이, 상기 제 3절연막을 건식 식각하여 구리(Cu)패턴(112)을 노출시킨다. 상기 노출된 구리 패턴(112)에 볼랜드(116)가 형성된다. 도면부호Ⅱ는 패키징 공정이 완료된 웨이퍼 레벨 웨이퍼를 나타낸 것이다.Thereafter, as illustrated in FIG. 2G, the third insulating layer is dry etched to expose the copper (Cu) pattern 112. A ball land 116 is formed on the exposed copper pattern 112. Reference numeral II shows a wafer level wafer for which a packaging process has been completed.

이어, 상기 결과의 웨이퍼의 스크라이브라인영역에 쏘잉 공정을 진행하여 단품의 패키지(Ⅲ) 제조를 완료한다. 이때, 상기 스크라이브라인영역은 적층되는 반도체 칩과 와이어 본딩으로 전기적으로 결선될 우려가 있으므로 충분히 넓어야 하며, 이를 위해 블레이드를 이용하여 같은 라인에 2회 정도의 쏘잉 공정을 진행한다.Subsequently, a sawing process is performed on the resulting scribe brine region to complete the manufacture of the package III. In this case, the scribe brine region should be sufficiently wide because the semiconductor chip and the wire bonding may be electrically connected. To this end, the sawing process is performed twice in the same line using a blade.

그런 다음, 상기 쏘잉 공정이 완료되면, 컬럼(column)별로 분리되는 것을 방지하기 위해 고정틀(미도시)을 웨이퍼 가장자리 면에 붙인다. 고정틀은 둥근 금속 프레임, 접착부는 테이프 형태로 접합을 완료한다.Then, when the sawing process is completed, a fixing frame (not shown) is attached to the wafer edge surface to prevent separation by column. The fixing frame is a round metal frame and the bonding part is completed in the form of tape.

도 3 내지 도 6은 본 발명에 따른 적층 패키지의 제조 방법을 설명하기 위한 단면도이다.3 to 6 are cross-sectional views illustrating a method of manufacturing a laminated package according to the present invention.

본 발명에 따른 적층 패키지의 제조 방법은, 도 3에 도시된 바와 같이, 제 1반도체 칩(300) 상에 제 1본딩 패드(302)를 기준으로 좌우 위치에 각각의 단품의 패키지(Ⅲ)를 안착시킨다. 이때, 미설명된 도면부호 301은 테이프를 나타낸 것으로서, 제 1반도체 칩과 단품의 패키지 사이를 접착시키려는 것이다.According to the manufacturing method of the multilayer package according to the present invention, as shown in FIG. 3, the package III of each single piece is placed on the first semiconductor chip 300 in the left and right positions with respect to the first bonding pad 302. Settle down. In this case, reference numeral 301, which is not described, refers to a tape, and is intended to bond the first semiconductor chip and the single package.

이어, 도 4에 도시된 바와 같이, 상기 제 1본딩 패드(302)와 각각의 단품의 패키지(Ⅲ)내의 볼랜드를 전기적으로 연결시키는 제 1본딩와이어(304)를 형성한다.Next, as shown in FIG. 4, a first bonding wire 304 is formed to electrically connect the first bonding pad 302 and the ball lands in the package III of each unit.

그런 다음, 도 5에 도시된 바와 같이, 단품 패키지(Ⅲ)의 볼랜드에 플럭스를 도포한 다음, 제 1본딩 와이어(304) 및 제 1반도체 칩(300)을 덮는 몰딩체(306)를 형성한다.Then, as shown in FIG. 5, flux is applied to the borland of the unit package III, and then a molding body 306 covering the first bonding wire 304 and the first semiconductor chip 300 is formed. .

이 후, 도 6에 도시된 바와 같이, 상기 플럭스가 도포된 볼랜드에 도전성 볼(308)을 부착시킴으로서, 본 발명에 따른 적층 패키지(Ⅳ) 제조를 완료한다.Thereafter, as shown in Figure 6, by attaching the conductive ball 308 to the flux-coated ball land, the manufacturing of the laminated package (IV) according to the present invention is completed.

이상에서와 같이, 본 발명에서는 반도체 칩 위에 웨이퍼 레벨 칩 규모 패키지를 적층시켜 메모리의 대용량화를 구현할 수 있다.As described above, in the present invention, a wafer-level chip scale package is stacked on a semiconductor chip to realize a large memory capacity.

또한, 본 발명은 기존의 적층 방식에 비해 실장 면적이 작음으로써, 고집적화된 메모리 모듈 제조가 가능하며, 전기적 접합 경로가 짧아 디바이스의 고속화에 대응할 수 있다.In addition, the present invention has a smaller mounting area than a conventional stacking method, and thus, highly integrated memory modules can be manufactured, and a short electrical junction path can correspond to high speed devices.

한편, 본 발명은 리드프레임을 사용하지 않고 미소량의 몰딩제로 몰딩하기 때문에 패키지를 경량화할 수 있다.On the other hand, since the present invention is molded with a small amount of molding agent without using a lead frame, the package can be reduced in weight.

기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.

Claims (1)

제 1본딩 패드를 구비한 제 1반도체 칩과, 제 1반도체 칩 상에 형성되며 상기 제 1본딩 패드를 노출시키는 절연막과, 상기 절연막 상에 상기 제1본딩 패드를 덮는 금속 배선 및 상기 금속 배선과 연결되는 볼랜드를 구비한 단품 패키지를 제공하는 단계와,A first semiconductor chip having a first bonding pad, an insulating film formed on the first semiconductor chip and exposing the first bonding pad, a metal wiring covering the first bonding pad on the insulating film, and the metal wiring; Providing a single package having a borland connected thereto, 제 2본딩 패드를 구비한 제 2반도체 칩을 제공하는 단계와,Providing a second semiconductor chip having a second bonding pad, 상기 제 2반도체 칩 상에 상기 제 2본딩 패드를 기준으로 하여 양방향에 각각의 단품 패키지를 안착시키는 단계와,Mounting each single package on both sides of the second semiconductor chip with respect to the second bonding pad; 상기 제 2본딩 패드와 상기 단품 패키지의 볼랜드를 전기적으로 연결시키는 제2본딩와이어를 형성하는 단계와,Forming a second bonding wire electrically connecting the second bonding pad and the ball land of the unit package; 상기 본딩와이어 및 제 2반도체 칩을 덮는 몰딩체를 형성하는 단계와,Forming a molding to cover the bonding wires and the second semiconductor chip; 상기 볼랜드에 도전성 볼을 부착시키는 단계를 포함한 것을 특징으로 하는 적층 패키지의 제조 방법.And attaching conductive balls to the ball lands.
KR1020020087889A 2002-12-31 2002-12-31 Method for fabricating stacked package KR20040061608A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100886711B1 (en) * 2007-07-27 2009-03-04 주식회사 하이닉스반도체 Semiconductor package and method of manufacturing theereof
KR100910233B1 (en) * 2008-01-02 2009-07-31 주식회사 하이닉스반도체 Stacked wafer level package
US8847377B2 (en) 2008-01-02 2014-09-30 SK Hynix Inc. Stacked wafer level package having a reduced size

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100886711B1 (en) * 2007-07-27 2009-03-04 주식회사 하이닉스반도체 Semiconductor package and method of manufacturing theereof
KR100910233B1 (en) * 2008-01-02 2009-07-31 주식회사 하이닉스반도체 Stacked wafer level package
US8847377B2 (en) 2008-01-02 2014-09-30 SK Hynix Inc. Stacked wafer level package having a reduced size

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