KR100376904B1 - Video decoding device to control encoded video data - Google Patents

Abstract

An MPEG video decoder is described that can prevent the buffer for storing a video stream from overflowing and / or underflowing. The video decoding apparatus decodes a coded video bit stream comprising a series of pictures to produce a decoded picture. The video decoding apparatus includes a bit buffer for temporarily storing a video bit stream; A decoding circuit for receiving the video bit stream output from the bit buffer to generate a decoded picture and decoding the video bit stream, and supplying the decoding circuit from the bit buffer to the decoding circuit based on the amount of data of the video bit stream stored in the bit buffer. Video bit stream control circuitry for controlling the amount of video bit stream.

Description

Video decoding device capable of controlling encoded video data

The present invention generally relates to a decoder for decoding encoded video data. In particular, the present invention relates to an improved video decoder for controlling encoded video data stored in a buffer.

Personal computers, as well as business and home entertainment systems that handle vast amounts and various forms of multimedia information, must digitally process recorded video and audio information. This high speed information processing can be achieved by data compression and decompression which directly affects the processing speed. The "MPEG" specification is one of these data compression and decompression techniques to improve processing speed. The MPEG standard is currently being standardized by the MPEG Committee (ISO / IEC / JTC1 / SC29 / WE11) under the International Organization for Standardization (ISO) / International Electrotechnical Commission (IEC).

The MPEG standard consists of three parts. Part 1 (ISO / IEC IS 11172-1: MPEG system part) defines a multiplex configuration and synchronization system of video data and audio data. Part 2 (ISO / IEC IS 11172-2; MPEG video part) defines a high efficiency coding system of video data and a format for video data. The three part (ISO / IEC IS 11172-3: MPEG audio part) defines a high efficiency coding system of audio data and a format for the audio data.

Video data dealing with the MPEC video portion includes moving pictures each consisting of tens of frames per second (eg 30 frames). The video data includes a sequence comprising a plurality of groups of pictures (GOP), a GOP containing a plurality of pictures, a plurality of slices within each picture, and a plurality of macroblocks within each slice. ) And a six-layered configuration of multiple blocks in each macroblock.

Recently, there are two MPEG standards, MPEG-1 and MPEG-2, which differ mainly in the encode rate at which video and audio data are encoded. In MPEG-1, a frame is associated with a picture. In MPEG-2, a frame or field is associated with a picture. A configuration in which a frame is associated with a picture is called a frame configuration, and a configuration in which a field is associated with a picture is called a field configuration.

In MPEG, a compression technique called intra-frame prediction is used. Interframe prediction compresses interframe data based on chronological correlation among frames. Interframe prediction includes bidirectional prediction. Bidirectional prediction uses both forward prediction for predicting the current playback picture (or picture) from past playback pictures (or pictures), and backward prediction for predicting the current playback picture from future playback pictures.

Bidirectional prediction uses an intra-coded (I) picture Predictive-coded (P) picture and a Bidirectionally-coded (B) picture. I-pictures are generated independently regardless of past and future playback pictures. P-pictures are generated by forward prediction (prediction from past decoded 1- or P-pictures). B-pictures are reproduced by bidirectional prediction. In bidirectional prediction, a B-picture is generated by prediction of one of the following three predictions.

(1) Forward prediction: prediction from past decoded I- or P-prediction.

(2) backward prediction: prediction from future decoded I- or P-prediction.

(3) Bidirectional prediction: prediction from past and future decoded I- or P-predictions.

I-pictures are created without past or future pictures, but all P-pictures are created with reference to past pictures, and all B-pictures are created with reference to past or future pictures.

In interframe prediction, first an I-picture is generated periodically. Subsequently, one frame before the I-picture is generated as a P-picture. This P-picture is generated by prediction in one direction (forward) from past to present. Next, frames located before the I-picture and after the P-picture are generated as B-pictures. At this time, a B-picture is generated and an optimal prediction structure is selected from forward prediction, reverse prediction and bidirectional prediction. In general, in a continuous picture, the current picture is similar to the picture before and after and only partially different. In this regard, it is assumed that the previous frame (e.g., I-picture) and the next frame (e.g., P-picture) are almost identical. If there is a slight difference (B-frame data) between both frames, this difference is extracted and compressed. Thus, interframe data can be compressed based on temporal correlation among successive frames.

The stream of video data encoded according to the MPEG video standard in this manner is called an MPEG video bit stream (hereinafter referred to as a "video stream"). MPEG-1 is mainly associated with storage media such as Compact Disk (CD) and Compact Disk-Read Only Memory (CD-ROM), while MPEG-2 includes MPEG-1 and is used for a wide range of applications.

The decoder using the storage medium should have three special playback functions as follows.

(1) A function of displaying (or playing back) a moving image at a faster speed than normal playback (this function is hereinafter referred to as "fast playback").

(2) A function that displays animation at a slower speed than the normal playback speed (this function is hereinafter referred to as "slow playback").

(3) A function of displaying moving pictures in frame-to-frame (this function is hereinafter referred to as "frame-to-frame advance playback").

The fast playback function of the forward mode allows the user to watch the video quickly. Fast forward playback or fast reverse playback allows the user to find the desired moving picture. Slow playback and frame-to-frame advance playback allow the user to watch the video carefully.

1 is a block circuit diagram showing a conventional MPEG video decoder having a high speed playback function. The MPEG video decoder 101 includes a bit buffer 102, a picture header decoder 103, an MPEG video decode core circuit (hereinafter referred to as a “decode core circuit” 104), a bit stream skip circuit 105, and a control core circuit 106. The control core circuit 106 controls the independent circuits 102-105.

The bit stream read from the recording medium 100 such as a video CD by a data recorder (not shown) is supplied to the bit buffer 102 through the bit stream skip circuit 105. The bit buffer 102 is a ring buffer provided with random access memory (RAM) having a first-in-first-out (FIFO) configuration, and continuously stores a bit stream. The picture header decoder 103 detects a picture header at the head of each picture included in the bit stream stored in the bit buffer 102. Based on the detected picture header, the control core circuit 106 controls the bit buffer 102 in a manner that reads a bit stream corresponding to one picture per frame period. Each moving picture is composed of 30 frames per second in MPEG-1, and one frame is 1/30 second.

The decode core circuit 104 receives each picture read from the bit buffer 102 and decodes this picture based on the MPEG video portion. Decode core circuitry 104 subsequently supplies data of individually decoded pictures as video output to display 107.

The bit buffer 102 temporarily stores I, P, and B-pictures with different amounts of data. The data amount of the i-picture is about 30 Kbytes, the data amount of the P-picture is about 10-15 Kbytes, and the data amount of the B-picture ranges from 0 to about 6 Kbytes. In the normal playback mode, the bit rate R _B of the bit stream is constant. The decode core circuit 104 performs data decoding on each of these pictures, and the decoding time varies according to the data amount of the independent picture. The bit stream is sent directly to the decode core circuit 104, and the decode core circuit 104 cannot decode all the pictures. The bit buffer 102 functions as a buffer memory for storing bit streams, and allows the decode core circuit 104 to decode I, P, and B-pictures regardless of the amount of data.

The bit stream skip circuit 105 has a first node 105a for transmitting the video stream directly to the bit buffer 102 in the normal playback mode and a second mode for skipping the video stream in the first playback mode ( 105b). The control core circuit 106 selectively switches the connection to the first node 105a and the connection to the second node 105b in accordance with the playback speed to intermittently transmit the video stream to the bit buffer 102. That is, if the bit stream skip circuit 105 is set to the second node 105b, the video stream is skipped without being sent to the bit buffer 102. As a result, the video stream to be sent to the bit buffer 102 is sieved (ie, reduced) by the skipped amount.

In the normal playback mode, the bit rate R _B of the video stream to be supplied is constant. Overflow should be prevented when the data amount of the video stream is large for one picture, and underflow should be prevented when the data amount is small, so that the occupancy (or remaining amount) of the video stream in the bit buffer 102 should be properly controlled. The MPEG video portion defines the MPEG video decoder and defines the control of occupancy.

2 is a graph showing the relationship between the occupancy and time of the video stream in the bit buffer 102 in the normal playback mode. Occupancy B _M rises with the bit rate R _B of the video stream indicated by the slope of the graph. The bit rate R _B of the video stream is defined by equation (1) below.

Where BR is the bit rate of the sequence header provided at the head of the sequence.

The capacity B of the bit buffer 102 is defined by the following equation (2).

Where VBS is the Video Buffering Verifier (VBV) buffer size of the sequencer header.

The data amount X of the video stream to be supplied to the bit buffer 102 within one frame period is defined by the following equation (3).

Here, R _P is the picture rate of the video stream defined by the picture rate of the sequence header. The video stream for one picture is read from the bit buffer without being stopped for one frame period and decoded by the decode core circuit 104. The occupancy amount Bm immediately after continuous reading of the video stream is defined by the following equation (4). Occupancy amount Bm is represented by "B ₀ to B ₆ " as shown in FIG.

Defining the occupancy amount Bm to satisfy equation (4) prevents overflow and underflow of the bit buffer 102. In other words, the occupancy amount Bm exceeding the threshold indicated by B-X indicates that the bit buffer 102 is more likely to overflow. In the normal playback mode, the bit rate R _B , picture rate R _P and capacity B are defined to satisfy equation (4). In addition, setting the capacity B of the bit buffer 102 as defined in equation (2) prevents the overflow and underflow of the bit buffer 102.

In the fast playback mode, the bit rate of the video stream increases with the playback speed. If the playback speed in the fast playback mode is n times the normal playback speed, the bit rate of the video stream is n times the bit rate (R _B = n × R _B ) at the normal playback speed. Increasing the bit rate of the video stream causes the bit buffer 102 to overflow. To prevent this overflow, in the high speed playback mode, the control core circuit 106 controls the video stream skip circuit 105 according to the playback speed in order to flush out the video stream to be transmitted to the bit buffer 102. As a result, the bit rate of the video strip becomes substantially the same as the bit rate R _B in the normal playback mode, thereby preventing the overflow of the bit buffer 102.

However, according to the conventional MPEG video decoder 101, the capacity B of the bit buffer 102 is set as in Equation (2) in the normal playback mode, and the bit buffer 102 is provided in the following two cases. Can overflow.

Case 1: The bit rate R _B of the video stream read from the recording medium is not synchronized with the bit rate of the video output, and the line bit rate R _B is greater than the later bit rate.

Case 2: The decode core circuit 104 does not decode a video stream in accordance with the MPEG standard.

Assume the bit buffer 102 overflows and the decode core circuit 104 decodes any picture. Subsequently, some of the video stream of the picture to be decoded still remain in the bit buffer 102 but are overwritten with the newly supplied video stream.

As a result, the residual video stream of this picture is destroyed and lost. This makes it impossible for the decode core circuitry 104 to complete the picture decoding, so that no video output of this picture is produced.

P-pictures are generated by referring to past or future I- or P-pictures. On the other hand, an I-picture is generated without referring to a past picture or a future picture. When the video stream of an I- or P-picture is destroyed due to overflow of the bit buffer 102, the decode core circuit 104 may P- and B until the next I-picture is supplied from the bit buffer 102. -The picture cannot be decoded. It is clear that the overflow of the bit buffer 102 disables the decoding of multiple pictures and causes some frames to be dropped from the video to be displayed. This frame dropping degrades the quality of the display of moving pictures and moving pictures of jerkey motion. The final moving picture does not look satisfactory to the user.

In the fast playback mode, controlling the video stream skip circuit 105 with the control core circuit 106 is extremely complex. Therefore, the control core circuit 106 must use a microcomputer, which inevitably increases the manufacturing cost and increases the overall apparatus.

Moreover, the control core circuit 106 controls the video stream skip circuit 105 according to the playback speed in the fast playback mode. According to this control, the video stream skip circuit 105 skips the video stream from the node 105b regardless of the picture. This causes the video stream steep circuit 105 to send a video stream of the interrupted picture to the bit buffer 102. If the supply of an I- or P-picture falls, the decode core circuit 104 cannot decode both the P-picture and the B-picture until the next I-picture is transmitted. If the video stream of the I-picture is not blocked, decode core circuitry 104 may decode the I-picture. I-pictures are included in a video stream at a rate of about one or two frames per second. Therefore, in fast reproduction, which is two to four times faster than normal reproduction, the number of undecipherable pictures increases so that certain frames are dropped from the moving image. (This high speed playback is hereinafter referred to as "2x high speed playback or 4x high speed playback".) This frame dropping causes the moving picture to be displayed on the screen of the display 107 at a rate of one or two frames per second. . Therefore, such high-speed playback becomes the same as frame-to-frame advance playback, degrading the picture quality of the moving picture so that the moving picture is displayed in a Jurkey operation. As a result, this final moving image does not seem satisfactory to the user.

For example, a video CD player using a video CD as a recording medium plays back a moving picture by a track jumping system. This system allows the optical pickup of a video CD player to intermittently scan tracks on a video CD and some tracks to be skipped. The pickup repeats the operation of reading a predetermined amount of video stream from a given recording track and jumping to another recording track. When an I-picture is accidentally included in a video stream, the I-picture is decoded. According to this system, it is not possible to decode all the I-pictures in the video stream, producing an undecipherable I-picture. In high speed reproduction of 2 to 4 times, moving pictures are displayed at a rate of 0.1 to 0.5 frames per second. The number of I-pictures contained in a video stream read at one time is not constant, and the I-picture cannot be read in some cases. In other words, the reproduced moving image cannot have a constant time interval between frames, and the image quality is very bad.

To improve this disadvantage, the I-picture scanning system is defined according to the Video CD v2.0 specification. This scanning system defines that an I-picture contains information of a recording track stored in a video stream. This information is called "injection information". This scanning information is used to allow all I-pictures in the video system to be decoded to control the optical pickup with the video CD player. However, in the 2X to 4X fast playback mode, moving pictures can only be displayed at a rate of 1 or 2 frames per second.

In addition to the three types of I-, P- and B- pictures, a D-picture as a fourth picture has also been defined. The D-picture contains a DC (Drect Current) component of the Discrete Cosine Transform (DCT) coefficients and is in a different sequence than the I, P, and B-pictures. This D-picture is used to perform fast forward playback which allows the user to find a desired moving picture. Since the D-picture contains almost no video streams, even when the D-picture is used during 2 to 4 times high speed playback or ultra high speed playback, the obtained moving picture does not exhibit slow motion and has high picture quality.

There is another problem with slow playback and frame-to-frame advance playback. In general, the bit rate of the video stream during slow playback, and frame-to-frame advance playback are the same for normal playback. Therefore, in slow playback and frame-to-frame advance playback, the control core circuit 106 reduces the number of pictures to be read from the bit buffer 102 per unit time, so that the number of frames of the moving picture to be displayed on the display 107. Decreases. To prevent overflow and underflow of the bit buffer 102, the MPEG video decoder 101 reads the video stream from the recording medium, and whenever a picture is read from the bit buffer 102, the bit buffer 102 To feed. This process requires frequent iterations of reading the video stream. Frequently reading the video stream from the video CD by the video CD player not only requires complicated control of the drive unit for optical pickup, for example, but also increases the mechanical load on the drive unit and their possibility of malfunction.

As already mentioned, the bit buffer 102 can underflow even if the occupancy is properly controlled. For example, if a video CD player is used as an external device, scratching on the disc and vibration of the disc make reading of the video stream recorded on the disc impossible. In this case, the video stream will not be sent to the bit buffer 102, resulting in underflow. This underflow is stored as a new video stream to be transmitted to the bit buffer 102. During the underflow, the decode core circuitry 104 is forced to stop the decoding operation so that no video output is produced. As a result, some frames are dropped from the moving picture displayed on the screen of the display 107. This frame dropping degrades the image quality of the moving image and causes the moving image to be displayed in a Jerky operation. Thus, the final moving image does not appear satisfactory to the user.

Broadly speaking, the present invention relates to an MPEG video decoder capable of preventing the buffer storing the video stream from overflowing and / or underflowing. The invention can be implemented in a variety of ways, including methods, systems, and apparatus.

According to an embodiment of the invention, a video decoding apparatus for decoding a coded video bit stream, comprising a series of pictures for generating a decoded picture, comprises: a bit buffer for temporarily storing a video bit stream: from a bit buffer. Decoding circuitry for receiving the video bit stream output and decoding the video bit stream to generate a decoded picture; And a video bit stream control circuit for controlling the amount of video bit stream to be supplied from the bit buffer to the decoding circuit based on the data amount of the video bit stream stored in the bit buffer. The control circuitry operates to skip a portion of the video bit stream to prevent the video bit stream from being supplied from the bit buffer to the decoding circuit as long as the data amount exceeds the threshold and is stored in the bit buffer. Optionally, the video bit stream control circuit changes the threshold in proportion to the playback speed for the decoded picture. Moreover, the portion of the video bit stream to be skipped may be selected based on the type of each picture and / or the amount of data for each picture.

According to another embodiment of the present invention, a video decoding apparatus for decoding a coded video bit stream including a series of pictures to generate a decoded picture, the video decoding apparatus is a bit buffer for temporarily storing the video bit stream ; Decoding circuitry for receiving the video bit stream output from the bit buffer and decoding the video bit stream to produce a decoded picture; And an operation control circuit for controlling the decoding operation of the decoding circuit based on the read operation of the bit buffer and the data amount of the video bit stream stored in the bit buffer. The operation control circuit is configured to prohibit the read operation of the bit buffer and the decoding operation of the decoding circuit for supplying the already decoded picture for a period from the time when the underflow of the bit buffer occurs to the time when the underflow is released. It works.

BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be best understood with reference to the accompanying drawings and the detailed description of the preferred embodiments, together with the objects and advantages of the invention.

First embodiment

A first embodiment of the present invention will now be described with reference to the accompanying drawings. The video decoder according to the first embodiment has a high speed playback function and conforms to the MPEG standard. As shown in FIG. 3, the MPEG video decoder 1 according to the first embodiment includes a bit buffer 2, a picture header detector 3, an MPEG video decode core circuit 4, and a video stream determination circuit 5 ), A picture skip circuit 6 and a control core circuit 7. These circuits 3 to 7 are well mounted on one large scale integrated (LSI) chip.

The control core circuit 7 controls the independent circuits 2 to 6. The video stream read from the recording medium 100 such as a video CD by a data reader (not shown) is supplied to the bit buffer 2. The bit buffer 2 is a ring buffer having a random access memory (RAM) having a FIFO configuration for continuously storing video streams. The bit buffer 2 is formed by the decode core circuit 4 having I, P, and B pictures. It serves as a buffer memory to decode all pictures irrespective of the data amount of.

The picture header detector 3 detects a picture header at the head of each picture included in the video stream stored in the bit buffer 2. The picture header specifies the picture type of one of the I, P, and B pictures. In accordance with the detection signal from the picture header detector 3 and the determination signal of the determination circuit 5 to be described later, the control core circuit 7 performs a bit in a manner of reading a video stream corresponding to the appropriate number of pictures per frame period. The buffer 2 is controlled. The video stream of each picture read from the bit buffer 2 is transmitted to the decode core circuit 4 via the picture skip circuit 6.

The decode core circuit 4 receives the video stream of each picture and decodes it appropriately for the MPEG video portion to generate a video output signal picture by the picture. This video output signal is supplied to a display 8 connected to the MPEG video decoder 1.

The picture skip circuit 6 has a first node 6a and a second node 6b, and selectively switches the connection to the nodes 6a and 6b under the control of the control core circuit 7. When the picture skip circuit 6 is set in the first node 6a, the picture is transferred from the bit buffer 2 to the decode core circuit 4. On the other hand, when the picture skip circuit 6 is set in the second node 6b, the picture is skipped without being transferred to the bit buffer 2. As a result, the video stream to be transmitted to the decode core circuit 4 is subtracted by the picture skip circuit 6 in units of pictures.

The video stream determination circuit 5 changes the threshold value Bthn of the occupancy amount Bm of the picture (video stream) in the bit buffer 2 in accordance with the refresh rate signal n supplied from the external input device 200. Then, the actual occupation amount Bm and the threshold value Bthn are compared. The reproduction high speed signal n is displayed at a magnification with respect to the normal reproduction speed. For example, in the double speed reproduction mode, the magnification n = 2 and the threshold Bthn becomes Bth2. In the normal reproduction mode, the magnification n = 1 and the threshold Bthn becomes Bth1. When the occupancy amount Bm of the bit buffer 2 is not larger than the threshold Bthn, the judging circuit 5 has no fear that the bit buffer 2 will overflow, and the occupancy amount is also normal. In accordance with this determination, the control core circuit 7 controls the bit buffer 2 in such a manner as to read a video stream for one picture. In addition, the control core circuit 7 sets the picture skip circuit 6 in the first node 6a so that the picture is transmitted to the decode core circuit 4.

When the occupation amount Bm of the bit buffer 2 exceeds the threshold Bthn, the determination circuit 5 determines that the bit buffer 2 may overflow. In accordance with this determination, the control core circuit 7 reads the appropriate number of video streams of the picture so that the bit buffer 2 is set in such a manner that the occupancy amount Bm of the bit buffer 2 is set to be smaller than the threshold Bthn. ). In addition, the control core circuit 7 sets the picture skip circuit 6 at the first node 6b to skip the appropriate number of pictures.

Article 4 is a graph showing the relationship between the occupancy and time of the video stream in the bit buffer 2 of the first embodiment. The occupancy amount Bm in the normal reproduction mode rises according to the bit rate R _B of the video stream representing the slope of the graph. The bit rate (R _B ), picture rate (R _P ), and capacity (B) for the MPEG video decoder 1 of the present embodiment are also the same as those for the conventional MPEG video decoder 101. 4), 0 < Bm < B-X = B-(R _B / R _P ). The capacity B is defined by equation (2) B = 16 x 1024 x VBS. This prevents the bit buffer 2 from overflowing or underflowing when the picture skip circuit 6 is switched to the first node 6a under ideal conditions.

Immediately after continuously reading one picture of data from the bit buffer 2, the occupancy amount Bm represented by B ₀ to B ₄ is defined based on the threshold value Bth1 to satisfy the following expression (5).

The threshold Bth1 is set according to the following expression (6) in accordance with equation (4).

In practice, even when the capacitor B is set as in Equation (2), the bit buffer 2 may overflow in two cases when the picture skip circuit 6 set in the first node 6a is maintained. Can be.

Case 1: The bit rate R _B of the video stream read from the recording medium is not synchronized with the bit rate of the video output, and the line bit rate R _B is greater than the later bit rate.

Case 2: The decode core circuit 4 does not decode the video stream to conform to the MPEG standard.

First, when the occupation amount Bm of the bit buffer 2 exceeds the threshold, the decision circuit 5 determines that the bit buffer 2 may overflow. The control core circuit 7 then controls the bit buffer 2 in such a way that a video stream of an appropriate amount of pictures is read out of the bit buffer 2 to set the occupancy Bm smaller than the threshold Bth1. do. Moreover, the picture skip circuit 6 is switched to the second node 6b to skip all read pictures. Therefore, the first embodiment can prevent the bit buffer from overflowing in the case 1 and case 2 modes in the normal playback mode.

The occupancy amount Bm in the fast playback mode increases in accordance with the bit rate nx R _B of the video stream representing the slope of the graph. For example, the occupancy amount Bm in the double speed reproduction mode rises along the graph whose slope is the bit rate (2 × R _B ). However, in the fast playback mode, the occupancy amount Bm represented by (B ₀ to B ₄ ) immediately after the continuous reading of one picture of data from the bit buffer 2 is _equal to the threshold value (7) below. Bthn).

The threshold Bthn is set as shown in the following equation (8).

When the occupation amount Bm exceeds the threshold Bthn in the fast regeneration mode, the judging circuit 5 determines that the bit buffer 2 may overflow. For example, when the occupancy Bm exceeds the threshold Bth2 [= B-(2 x R _B / R _F )] in the double speed regeneration mode and the occupancy Bm is the threshold in the triple speed regeneration mode. If (Bth3 [= B-(3 x R _B / R _P )] is exceeded, an overflow will occur. According to the determination signal, the control core circuit 7 determines that an appropriate number of pictures of the video stream are the bit buffer ( The bit buffer 2 is controlled in such a manner that it is read out from 2) and skipped so that the occupancy amount Bm is set to be smaller than the threshold value Bthn.This control overflows at 2 when the bit buffer 2 is in the fast playback mode. In the normal playback mode and the fast playback mode, the control core circuit 7 can easily control the bit buffer 2 and the picture skip circuit 6 based on the threshold value. There is no need to use a microcomputer for the control core circuit 7. Moreover, in this embodiment one LSI Mounting of the independent circuits (3 to 7) on to reduce the production cost, and contributes to miniaturization of the entire device.

The overflow of the bit buffer 2 must in particular be eliminated while the decode core circuit 4 decodes any picture. As already mentioned in the related art, assume that the bit buffer 2 overflows, and the decode core circuit 4 decodes any picture. Then, some video streams of the picture to be decoded still remain in the bit buffer 102 but are overwritten with the newly supplied video stream. As a result, the residual video stream of this picture is destroyed and lost. Therefore, it is impossible for the decode core circuit 4 to complete decoding of the picture, so that the video output of the picture is not generated.

Therefore, according to this embodiment, the decision circuit 5 uses the bit buffer when the picture header decoder 3 detects the picture header to determine whether sufficient space (nx X = nx R _B / R _P ) is secured. (2) Free sympathy in search. If the judging circuit 5 determines that there is enough space, the control core circuit 7 skips the picture read from the bit buffer 2 through the picture skip circuit 6 based on the picture header. Next, the decision circuit 5 searches the free space in the bit buffer 2 again when the picture header detector 3 detects the next picture header. The time required for these judgment and skipping processes is considerably shorter than the time required for the judgment process by the decode core circuit 4. Therefore, no problem occurs even when the decoding process is started after sufficient space is secured in the bit buffer 2.

The free space in the bit buffer 2 is searched because the amount of picture data is not constant. The amount of data for one picture is in the range of 1 to 40 bytes, and this amount is found when the decode core circuit 4 finishes decoding. Moreover, the time for decoding one picture varies depending on the data amount of the picture and the operating speed of the decode core circuit 4, which is normally about 1/3 to 4/3 of one frame. If the data amount of the picture is 0 bytes, for example, the occupancy amount Bm of the bit buffer 2 before the reading of this punch is not different from that after the picture reading. Therefore, picture skipping of 0 bytes makes it impossible to prevent the overflow of the bit buffer 2. In other words, if the bit buffer 2 has sufficient free sympathy for the amount of data supplied in one frame period, overflow of the bit buffer 2 can be prevented regardless of the amount of data of the read picture.

The data amount of the video stream to be supplied to the bit buffer 2 in one frame period is nx X = nx R _B / R _P. Therefore, the overflow of the bit buffer 2 can be prevented when the bit buffer 2 has free space equal to or larger than this data amount. This free space is obtained by subtracting the threshold Bthn from the capacity B of the bit buffer 2 as defined by equation (8). Therefore, when the occupation amount Bm is not larger than the threshold Bthn, the determination circuit 5 determines that sufficient free space is secured in the bit buffer 2. That is, as shown by equation (2), setting the threshold value Bthn can surely prevent the bit buffer 2 from overflowing.

According to the first embodiment, it is determined that the bit buffer 2 may overflow before the decode core circuit 4 starts decoding any picture.

In particular, the determination of the overflow of the bit buffer 2 is made when the picture header detector 3 detects the picture header, and it is determined whether or not to skip the picture according to the determination. This method can prevent the video stream of the decode core circuit 4 from being interrupted during transmission, and allow the decode core circuit 4 to decode not only I-pictures but also P-pictures and B-pictures. As a result, the occurrence of frame dropping will be reduced. In high speed playback, which is twice or four times faster than normal playback, it is possible to display pictures at a rate of several frames per second. Therefore, it is possible to achieve a moving picture showing natural operation in the high speed playback mode, and to significantly improve the picture quality.

Second embodiment

A second embodiment of the present invention will now be described with reference to FIGS. 3 to 5. The MPEG video decoder according to the second embodiment has the same general configuration as that of the first embodiment.

However, in this embodiment, the video stream determination circuit 5 uses two threshold values B2th and B2th to satisfy the condition defined by equation (9).

The thresholds B2thn and B3thn are set in accordance with the reproduction speed in the first embodiment, and are also set based on the result of actually checking the image quality of the moving image to be displayed on the display 8. The determination circuit 5 compares the threshold values B2thn and B3thn with the occupancy amount Bm of the bit buffer 2, and determines which of the following three cases (C1 to C3).

If C1 (Bm <B3thn):

When the occupancy amount Bm of the bit buffer 2 does not exceed the threshold value B3thn, the decision circuit 5 determines that the bit buffer 2 does not overflow and is normal. In accordance with this determination, the control core circuit 7 controls the bit buffer 2 in a manner of reading video data of one picture from the bit buffer 2. Moreover, the control core circuit 7 switches the picture skip circuit 6 to the first node 6a for transmitting the video stream of the picture to the decode core circuit 4.

Case 2 (B2thn <Bm):

When the occupation amount Bm exceeds the threshold B2thn, the judging circuit 5 sets a first flag as long as the picture read from the bit buffer 2 is an I- or P-picture. In the case where the first flag is set and the picture read after the I- or P-picture is a B-picture, the control core circuit 7 selects the B-picture even when the occupancy amount Bm becomes smaller than the threshold value B3thn. Skip it.

Case 3 (B3thn <Bm <B2thn):

If the occupation amount Bm is larger than the threshold B3thn but not larger than the threshold B2thn, the determination circuit 5 sets the second flag as long as the read picture is a P-picture. If the second flag is set and the picture reading after the P-picture is a B-picture, the control core circuit 7 skips the B-picture even when the occupation amount Bm becomes smaller than the threshold value B3thn. .

5 is a graph showing the relationship between the occupancy amount and time of a video stream in the bit buffer 2 according to the second embodiment. If the occupancy amount Bm is larger than the threshold value B3thn, if there is a read B-picture, the B-picture is skipped without decoding (see * 1 in Fig. 5). When the occupancy amount Bm after the skipping of the B-picture is still larger than the threshold value B3thn, the I- or P-picture readout after the B-picture is decoded (see * 2).

When the occupancy Bm is larger than the threshold Bthn, if there is a read I- or P-picture, this picture is decoded (see * 3 in the figure). Even after the decoding of the I- or P-picture, if the occupancy amount Bm is still larger than the threshold value B3thn, the B-picture read after the I- or P-picture is skipped without being decoded (see * 4). The skipping of this B-picture is repeated until the occupancy amount Bm becomes smaller than the threshold value B3thn (see * 5).

The reason why a B-picture is preferentially skipped for an I- or P-picture is that the importance of the data of the B-picture generated by bidirectional prediction is lower than the importance of the data of the I- and P-picture. Skipping of B-pictures that is preferential for I- or P-pictures causes the I- and P-pictures to be decoded as much as possible. Therefore, the number of frames dropped from the moving image to be displayed is smaller than in the first embodiment. Therefore, it is possible to obtain a moving picture showing natural movement with better picture quality in the high speed playback mode.

When the occupation amount Bm becomes larger than the threshold value B2thn, this picture is decoded if there is an I- or P-picture to be read out, and the judging circuit 5 sets the first flag (see * 6 in the figure). . When the first flag is set and the B-picture after the I- or P-picture is read, this B-picture is also skipped when the occupancy amount Bm becomes smaller than the threshold value B3thn (see * 7). Prior skipping of the B-picture read after the I- or P-picture can free up more free space in the bitbuffer 2 to prevent overflow.

When the occupancy Bm is larger than the threshold B3thn but smaller than the threshold B2thn, if there is a read B-picture, the picture is decoded, and the judging circuit 5 determines the second flag (* in the figure). 8). When the second flag is set and the B-picture is read after the P-picture, the B-picture is skipped even when the occupancy amount Bm becomes smaller than the threshold value Bthn (see * 9). Priority skipping of the B-picture read after the P-picture can reduce the occupancy amount Bm to prevent the bit buffer 2 from overflowing. This overflow protection configuration eliminates overflow of the bit buffer 2.

When the occupation amount Bm is larger than the threshold B3thn but smaller than the threshold B2thn, if there is an I-picture read out, this picture is decoded, and the judging circuit 5 does not set the second flag. (Refer to ※ 10 of drawing). When the second flag is not set, and when the occupancy amount Bm is smaller than the threshold value B3thn, the B-picture reading after the I-picture is decoded without skipping.

The first and second flags are set in the manner described above to form a condition for skipping a B-picture after reading an I-picture that is different from a condition for skipping a B-picture after reading a P-picture. . This will be described later in more detail. The data amount of the I-picture is two to three times that of the P-picture. Therefore, the degree of reduction of the occupancy amount Bm after the reading of the I-picture is larger than after the reading of the P-picture. In other words, the probability of overflow of the bit buffer 2 after the reading of the I-picture is smaller than after the reading of the P-picture. In contrast, the reference value or threshold B2thn for setting the first flag according to the I-picture is set higher than the reference value or threshold B3thn for setting the second flag according to the P-picture. Thus, the condition for skipping a B-picture after reading an I-picture is more relaxed than the skipping condition after reading a P-picture. Even if the occupation amount Bm is smaller than the threshold value B3thn, the number of B-pictures to be skipped in vain to prevent the overflow of the bit buffer 2 becomes small. In other words, the number of B-pictures to be decoded increases.

The following shows the simulation result in the fast playback mode according to the second embodiment. A1 and A2 represent GOP configuration forms of reading a video stream from a recording medium.

[1] In the double speed playback mode: for the A1 type, all I- and P-pictures can be decoded such that moving pictures are displayed at a full rate of 30 frames, and all I- and P-pictures and certain B-pictures are moving pictures. It can be decoded to be displayed at a rate of 25 or more frames per second.

[2] In the 4x playback mode: For both A1 and A2 types, the I-picture and subsequent three to four P-pictures are decodable such that the moving picture is displayed at a rate of 15 frames or more per second.

Third embodiment

A third embodiment of the present invention will be described with reference to FIG. In order to avoid repeated description of the detailed description, the same elements and symbols as those in the first embodiment are denoted.

6 illustrates an MPEG video decoder 11 according to this embodiment with special playback functions including fast playback, slow playback, and frame-to-frame advance playback. The MPEG video decoder 11 includes a bit buffer 2, a picture header detector 3, an MPEG video decode core circuit 4, a video stream determination circuit 5, a picture skip circuit 6 and a control core circuit 7 In addition, it includes a picture header detector / data amount analyzer 12 and first and second registers 13 and 14. These circuits 3 to 7, and 12 to 14 are mounted on one LSI chip.

The control core circuit 7 controls the independent circuits 2 to 6 and 12 to 14. The video stream read from the recording medium 100 such as a video CD is sent to the bit buffer 2 through the picture header decoder / data amount divider 12. The analyzer 12 has two functions:

(1) A function of detecting a picture head located at a head of each picture included in a video stream, and determining each type (I, P or B) based on the picture header.

(2) A function of analyzing the data amount of each picture based on the detected picture header.

The first and third registers 13 and 14 are each composed of a RAM having a FIFO configuration. The first register 13 sequentially stores the picture headers detected by the analyzer 12. Subsequently, the GOP configuration of the video stream stored in the bit buffer 2 is registered in the first register 13. The second register 14 sequentially stores information on the data amount of each picture analyzed by the analyzer 12.

The video stream determination circuit 5 has the following two functions:

(1) A function of comparing whether the occupancy amount Bm of the bit buffer 2 and the threshold values B3thn and B2thn is applicable to determine whether any of the cases C1 to C3 are applicable.

(2) Select the type of picture to be skipped based on the GOP structure registered in the first register 13, the data amount of each picture registered in the second register 14, and the result of the determination in (1) above. Function.

Unlike the first and second embodiments, according to the third embodiment, before the video stream is supplied to the bit buffer 2, the analyzer 12 finds the GOP configuration and the data amount of each picture. This feature makes it possible for the bit buffer 2 to determine whether the video stream will overflow before being fed to the bit buffer 2. Therefore, it is possible to select the optimal shape of the picture to be skipped based on the GOP configuration and the data amount of each picture. For example, this can prevent unnecessary skipping of B-pictures. That is, the number of B-pictures to be supplied to the decode core circuit 4 increases while preventing the bit buffer 2 from overflowing. Therefore, it is possible to obtain a moving picture showing natural movement in the high speed playback mode, thereby improving the picture quality.

Moreover, the control core circuit 7 will know the number of pictures to be stored in the bit buffer 2 and the exact data amount of each picture to determine the exact occupancy amount Bm of the bit buffer 2. The control core circuit 7 can also determine the exact extent of the reduction in the occupancy amount Bm after the reading of any picture. For example, in slow playback and frame-to-frame advance playback, the control core circuit 7 monitors the occupancy amount Bm and only when the bit buffer 2 can overflow or underflow more, the recording medium 100 ) Read the video stream. In this way, the number of pictures to be read from the bit buffer 2 per unit time is reduced, and thus the number of frames of the moving picture appearing on the display 8 is reduced. Thus, the number of operations of the drive unit serving to read the video stream from the recording medium can be reduced. This result makes it possible, for example, to simply control the drive unit for optical pickup of the video CD player using the video CD as the recording medium 100. It is also possible to reduce the occurrence of mechanical loads and malfunctions on the drive unit.

Fourth embodiment

A fourth embodiment of the present invention will now be described with reference to FIG. The same reference numerals and symbols are given to the same parts as the elements of the third embodiment, and detailed description thereof is omitted. 7 shows an MPEG video decoder 21 with a special playback function. The MPEG video decoder 21 includes a bit buffer 2, a picture header detector 3, an MPEG video decode core circuit 4, a video stream determination circuit 5, a picture skip circuit 6, and a control core circuit 7 ), A picture buffer detector / data amount analyzer 12 and a frame buffer 22 in addition to the first and second registers 13 and 14.

The control core circuit 7 controls the independent circuits 2 to 6, 12 to 14, and 22. The frame buffer 22 which shares one RAM with the bit buffer 2 has three storage areas, namely a forward reference area 22a, a backward reference area 22b and a B-picture storage area 22c. These areas 22a to 22c are called plans. The arrangement of the frame buffer 22 and the bit buffer 2 in one RAM reduces the number of necessary elements, contributing to reducing the cost of the MPEG video decoder 21.

Decoded data (or video data) of an independent picture generated by the decode core circuit 4 is transmitted to the relevant areas 22a to 22c. Decoded data of the independent pictures of the regions 22a to 22c are transmitted to the decode core circuit 4. The forward reference region 22a stores decoded data of future I- or P-pictures used in the backward prediction executed by the decode core circuit 4. The backward reference region 22b stores decoded data of past I- or P-pictures used in the forward prediction executed by the decode core circuit 4. The B-picture storage area 22c stores decoded data of the B-picture. Decoded data stored in one of the areas 22a to 22c is output to the display 8.

The decoded I- or P-pictures stored in the forward reference region 22a and backward reference region 22b are used as basic data for forward prediction decoding or backward prediction decoding. For this purpose, the decoded I- or P-picture is stored and kept in the relevant storage area until the required predictive decoding process is completed and the picture is no longer needed. Decoded B-pictures are not used as basic data and become unnecessary when supplied to the display 8.

In the case where the MPEG video decoder and the MPEG audio decoder are mounted on one LSI chip, the audio bit buffer for the MPEG audio decoder can be arranged independently with the frame buffer 22 and the video bit buffer 2 in one RAM. . For example, a 4M DRAM for a video CD may have a capacity of 52 kbytes of video bit buffer 2, a capacity of 148.5 kbytes of each region 22a through 22c, a capacity of 6.5 kbytes of audio bit buffer, and an 8 kbyte of user. Has a capacity for the area. The user area is used as, for example, a sector buffer specified in the Video CD v2.0 standard.

Since a moving picture showing sufficiently natural movement can be simply obtained by using the decoded data of I- and P-pictures during high-speed reproduction of 4x speed reproduction or more, the B-pictures are unnecessary and can be skipped altogether. Since moving pictures showing sufficiently natural movement can be simply obtained by using the decoded data of I-pictures at high speed reproduction of 8 times or more, the P- and B-pictures may be unnecessary or skipped altogether. It can be clearly seen that the B-picture storage area 22c becomes unnecessary during high-speed reproduction of 4x or higher reproduction.

Therefore, in the fourth embodiment, the unnecessary B-picture storage area 22c in the fast playback mode can be used to replenish the bit buffer 2. This method allows the storage area 22c to be used as an expansion memory for the bit buffer 2. Therefore, in the mentioned 4M DRAM, the capacity of the bit buffer 2 is about 200 kbytes (= 52 kbytes (capacity of the bit buffer 2) + 148.5 kbytes (B-picture storage), which is almost four times the capacity of the conventional bit buffer. Capacity of region 22c)]. Simulation in the fast playback mode using the bit buffer 2 as the expansion capacity has confirmed that a moving picture showing natural movement can be achieved up to a 30x playback speed. The expansion of the capacity of the bit buffer 2 can also prevent the bit buffer 2 from overflowing in the high speed playback mode above the 4x speed.

Fifth Embodiment

A fifth embodiment of the present invention is described with reference to FIGS. 7, 8A, 8B and 9. The MPEG video decoder according to the fifth embodiment has the same configuration as that of the fourth embodiment. The decode core circuit 4 decodes two I- or P-pictures to fit the MPEG video portion within one frame period, and generates two video outputs. The decode core circuit 4 has one output of one of the two video outputs generated within one frame period, i.e., the second video output obtained by later decoding rather than the first video output obtained by the first decoding on the display 8. Feed only. The first video output is used as intermediate data for forward prediction.

As set in the fourth embodiment, the B-picture storage area 22c in the frame buffer 22 is unnecessary. Therefore, according to this embodiment, the control core circuit 7 controls the decode core circuit 4 and the frame buffer 22 to store the first video output in the storage area 22c. This eliminates the need to provide a frame buffer for storing the first video output separately from the frame buffer 22.

The operation of the fifth embodiment will now be described with reference to FIGS. 8A, 8B and 9. Assume a video stream having a GOP layer (I, P, B, B, P, B, P, I) read from the recording medium 100 as shown in FIG. 8A. 8B shows a picture to be decoded by the decode core circuit 4, a picture to be displayed on the display 8 and a picture to be skipped through the picture skip circuit 6 within each one frame period.

9 is a graph showing the relationship between the occupancy amount Bm and the time of the bit buffer 2 corresponding to FIGS. 8A and 8B. After the I-picture 10 is decoded, the P-picture P1 is read from the bit buffer 2 and decoded. Even if the P-picture P1 is read, when the occupancy amount Bm is less than the threshold value R3thn, the two B-pictures B2 and B3 which are subsequently read after the P-picture P1 are skipped without being decoded. . When the occupation amount Bm is still larger than the threshold value B3thn, the P-picture P4 to be read next is decoded. At this time, the pre-decoded P-picture P1 (or the first video output) is not displayed on the display 8 but as intermediate data to generate the video output of the P-picture P4 through forward prediction. Used. Thus, the decoded P-picture P1 (or the first video output) is displayed. These processes are executed in one frame period. Within the next one frame period, the B-picture B5 is decoded and displayed.

Therefore, even if the bit buffer 2 is prevented from overflowing, the number of undecipherable P-pictures increases. Thus, the number of undecipherable B-pictures also increases. Therefore, a moving picture showing natural movement in the fast playback mode can be obtained, and the picture quality can be improved.

Sixth embodiment

A sixth embodiment of the present invention is described with reference to FIGS. 10 and 11. The same reference numerals and symbols are attached to the same elements as those of the first embodiment, and detailed descriptions thereof are omitted. 10 shows a block diagram of an MPEG video decoder 31 having a special playback function. The MPEG video decoder 31 carries the picture header detector 3, the MPEG video decode core circuit 4, the picture skip circuit 6, the control core circuit 7, the bit buffer 33 and the overflow detector 34. Include.

The control core circuit 7 controls the independent circuits 3, 4, 6, 33 and 34. The bit buffer 33 is composed of a RAM having a FIFO configuration and stores video streams sequentially. The capacity (buffer size) BA of the bit buffer 33 is defined by the following expression (10).

Where B is the capacity defined by equation (2), 1024 x VBS, as described in the related art section, and X is the data amount, R _B / R _P and ΔB is a suitable margin.

The overflow detector 34 detects the occupancy amount Bm of the video stream in the bit buffer 33 and compares the occupancy amount Bm with the first threshold value Bth1 and the second threshold value Bth2. The first threshold Bth1 is set to the same value as the capacity B. The second threshold Bth2 is set to a value obtained by adding the capacity B to the data amount X.

The video decoder 31 will be described with reference to the flowchart shown in FIG. If it is determined in step 1 that the overflow detector 5 occupancy amount Bm is greater than the first threshold value Bth1, the flow advances to step 2. If it is determined in step 1 that is not the case, the flow moves to step 3. If the overflow detector 5 determines in step 2 that the occupation amount Bm is greater than the second threshold Bth2, the flow advances to step 5. If not in step 2, the flow proceeds to step 4.

If the shape of the picture determined by the picture header detector 3 in step 4 is a B-picture, the flow advances to step 5. If the picture is an I-picture or a P-picture, the flow goes to step 3. In step 5, the picture skip circuit 6 skips the picture, and the flow then returns to step 1. In step 3, the picture skip circuit 6 sends the picture to the decode core circuit 4, and the flow then returns to step 1.

According to the sixth embodiment, as apparent from the above, if the occupancy amount Bm does not exceed the threshold Bth1, the picture read from the bit buffer 33 is decoded to the decode core circuit 4 regardless of its form. Is sent. If the occupancy Bm is between the first and second thresholds Bth1 and Bth2, the I- or P-picture is sent to the decode core circuit 4 and the B-picture is for the I- or P-picture. It is skipped first. Skipping of B-pictures that is preferential for I- or P-pictures suppresses the possibility of causing overflow of the bit buffer 33. Skipping of B-pictures does not affect continuous data decoding by the decode core circuit 4.

When the occupation amount Bm becomes larger than the threshold Bth2, the I, P and B-pictures are skipped. As a result, the occupancy amount Bm of the bit bufty 33 is reduced so that the overflow of the bit buffer 33 does not occur.

The capacity BA of the bit buffer 33 includes the margin ΔB in this embodiment, and the bit buffer 33 can overflow. The larger the margin ΔB, the less the risk that the bit buffer 33 will overflow. However, in this case, since the capacity BA is increased, the cost efficiency deteriorates. It is preferable to set the margin ΔB to an appropriate value obtained from experiments processing various video streams actually performed.

Seventh embodiment

A seventh embodiment of the present invention will now be described with reference to FIGS. 12 and 13. Fig. 12 shows a block circuit diagram of the MPEG video decoder 41 according to this embodiment. The MPEG video decoder 41 includes a bit buffer 2, a picture header detector 3, a decode core circuit 4, and a control core. Circuit 7, frame buffer 22 and underflow detector 42. The picture header detector 3 and the decode core circuit 4 have the same configuration as that of the first embodiment. The bit buffer 2 and the frame buffer 22 have the same configuration as that of the fourth embodiment.

The underflow detector 22 compares the occupancy amount Bm of the bit buffer 2 with the threshold value Bth3 and detects whether the bit buffer 2 underflows. The threshold Bth3 is set to a value obtained by multiplying the bit rate R _B by vbv (video buffering air) delay value VD. This vbv delay value VD is defined by the picture header.

The control core circuit 7 controls the decode core circuit 4 and the bit buffer 2 based on the shape of the picture read out from the bit buffer 2 and the comparison and detection result by the underflow detector 2. .

The operation of the MPEG video decoder 41 will be discussed with reference to the flowchart shown in FIG. If the underflow detector 42 determines in step 11 that the occupation amount Bm is less than the threshold Bth3, the flow moves to step 12. If in step 11 it is not, the flow skips step 13. The occupation amount Bm smaller than the threshold Bth3 suggests that the bit buffer 2 is likely to underflow when a picture is read from the bit buffer 2.

An error process is performed in step 12. In particular, the control core circuit 7 stops picture reading from the bit buffer 2, and at the same time repeatedly outputs a picture before picture reading is stopped, and does not output a picture to be decoded when picture reading is stopped. The decode core circuit 4 is controlled. The flow then returns to step 11. This error process increases the occupancy amount Bm, making the bit buffer 2 less likely to underflow.

In step 13, the next picture is read from the bit buffer 2 and decoded by the decode core circuit 4 to produce a video output. The flow then proceeds to step 1.

If the underflow detector 42 determines in step 14 that the bit buffer 2 does not underflow, the flow returns to step 11. On the other hand, if it is determined that an underflow occurs, the flow moves to step 15. In other words, when the decoding of one picture by the decode core circuit 14 ends well, the flow returns to step 11 and the flow proceeds to step 15 when the bit buffer 2 underflows during decoding of one picture. do.

In step 15, the error process is performed similar to the process in step 12, and then the flow proceeds to step 16. Performing error processing even in the event of underflow causes the decode core circuit 4 to continuously supply the video output to the display 8 so that the moving picture is continuously displayed on the screen of the displen 8.

If the picture header detector 3 determines in step 16 that the read picture is a B-picture, the flow goes to step 17. If the read picture is a 1-picture or a P-picture, the flow moves to Dean 18. In step 17, the B-picture to be decoded by the decode core circuit 4 is skipped. Skipping of the B-pictures does not affect the continuous decoding process by the decode core circuit 4. After picture skipping, the flow returns to step 11.

If the underflow detector 42 determines that underflow of the bit buffer 2 has been released in step 18, the flow returns to step 13. Underflow is released when the video stream is sent from the data reader (not shown) to the bit buffer 7. After the release of the underflow, decoding of the I- or P-picture that proceeds upon occurrence of the underflow is resumed at step 11. This makes it possible to reproduce I- or P-pictures of high importance and to provide moving pictures which show fewer dropped frames with natural movement. Therefore, the image quality of the obtained moving image is improved.

According to the seventh embodiment, the frame buffer 22 and the bit buffer 2 are provided in one 4M DRAM. Moreover, the frame buffer 22 has three storage areas, namely, the forward reference area 22a, the backward reference area 22b, and the B-picture storage area 22c. The first B-picture decoded by the decode core circuit 4 is transmitted to the B-picture storage area 22c, and at the same time, the second B-picture already stored in the storage area 22c is output to the display 8. . In other words, the second B-picture is overwritten with the first B-picture. Therefore, when an underflow of the bit buffer 2 occurs, the non-redundant write portions of the first B-picture and the second B-picture to which decoding proceeds are simultaneously present in the B-picture storage area 22c so that the display ( The screen of 8) is divided into two parts. However, when the importance of a B-picture is low, segmentation of the screen can be avoided by skipping the B-picture in decoding, as discussed above.

The I- or P-picture decoded by the first decode core circuit 4 is transmitted to the forward reference region 22a, and the first I- or B-picture, or B-, already stored in the backward reference region 22b. The decoded B-pictures stored in the picture storage area 23c are selectively output to the display 8. If the third I- or P-picture decoded by the decode core circuit 4 is transmitted to the reverse reference region 22b, the fourth I- or P-picture already stored in the forward reference region 22a, or B- The decoded B-picture stored in the picture storage area 22c is output to the display 8. Therefore, the first I- or P-picture is not overwritten with any of the second I- or P-picture, the third I- or P-picture, and the fourth I- or P-picture. Moreover, the decoding of the first or third I- or P-picture which proceeds upon occurrence of the underflow of the bit buffer 2 is resumed after the underflow is released. Subsequently, the fully decoded first or third I- or P-picture is stored in forward reference region 22a or reverse reference region 22b. Thus, the first or third I- or P-picture can also be displayed on the display 8, thereby providing a moving picture showing natural movement.

Although the seventh embodiment of the present invention has been described, it will be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the scope or spirit of the invention. In particular, it should be understood that the present invention can be implemented in the following forms.

The present invention is suitable for high speed playback including I-, P- and B-pictures as well as D-pictures.

Equation (8), Bthn = B-nx X-(nx R _B / R _P ) The coefficient m can be changed to a value larger than the magnification n of the normal reproduction speed. For example, the coefficient n is set larger than "2"(n> 2) at the double speed reproduction. In this case, if the coefficient n is set too large, the number of frames to be dropped from the moving image to be displayed increases. In contrast, it is best to set the value of the coefficient n equal to the magnification n, and preferably, the coefficient n should be adjusted to suppress the number of frames to be dropped.

The first embodiment and the second embodiment may be merged. Similarly, the second and seventh embodiments can also be merged. In addition, the sixth and seventh embodiments may also be merged.

In the first to seventh embodiments, the signal processing of the independent circuits 4, 6, 7, 34 and 42 can be replaced by software-based signal processing which is achieved using the CPU.

The frame buffer 22 may be provided separately from the bit buffer 2 of the fourth embodiment.

A frame buffer for storing the first video output of the first decode I- or P-picture may be provided separately from the frame buffer 22 of the fifth embodiment.

In the sixth embodiment, the second threshold Bth2 and the operation related to this threshold can be omitted.

Recording media usable in the present invention include not only video CDs but also all forms of digital recording media such as CD-ROMs, hard disks, and video tapes.

The present invention is suitable for video CD players as well as players for storage media such as video tape recorders (VTR) and digital video discs (DVD) using the MPEG system.

Therefore, the present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details, but may be modified within the scope of the appended claims.

1 is a block circuit diagram showing a conventional MPEG video decoder.

2 is a graph showing the relationship between the occupancy and time of a video stream in a conventional bit buffer.

3 is a block circuit diagram showing an MPEG video decoder according to the first and second embodiments of the present invention.

4 is a graph showing the relationship between the occupancy and time of a video stream in a bit buffer according to the first embodiment.

5 is a graph showing the relationship between the occupancy and time of a video stream in a bit buffer according to the second embodiment.

6 is a block circuit diagram showing an MPEG video decoder according to a third embodiment of the present invention.

7 is a block circuit diagram showing an MPEG video decoder according to the fourth and fifth embodiments of the present invention.

8A is a diagram for explaining a GOP configuration of a video stream, and FIG. 8B is a diagram for explaining a picture to be processed every one frame period.

9 is a graph showing the relationship between the occupied amount and time of a video stream in a bit buffer according to the fifth embodiment.

10 is a block circuit diagram showing an MPEG video decoder according to a sixth embodiment of the present invention.

11 is a flowchart for explaining the operation of the sixth embodiment.

12 is a block circuit diagram showing an MPEG video decoder according to a seventh embodiment of the present invention.

13 is a flowchart for explaining the operation of the seventh embodiment.

Explanation of symbols for the main parts of the drawings

1, 11, 21, 31: MPEG video decoder 2, 33: bit buffer

3: picture header detector

4: MPEG video decode core circuit 5: video stream determination circuit

6: picture skip circuit 6a, 6b: node

7: control core circuit 8: display

12: Picture header detector / data quantity analyzer 13, 14: register

22: frame buffer 22a: forward reference area

22b: backward reference area 22c: B-picture storage area

34: overflow detector 42: underflow detector

Claims (23)

A video decoding apparatus for generating a decoded picture by decoding a coded video bit stream having a plurality of reproduction modes and including a series of pictures, A bit buffer for temporarily storing all the video bit streams regardless of a playback mode; Decoding circuitry for receiving the amount of the video bit stream output from the bit buffer to a threshold and decoding the video bit stream to generate the decoded picture; And Controlling the amount of all the video bit streams to be provided from the bit buffer to the decoding circuit based on the data amount of all the video bit streams stored in the bit buffer, operatively connected to the bit buffer and the decoding circuit. Video bit stream control circuit The control circuit includes Determine whether the amount of data stored in the bit buffer exceeds the threshold, wherein the threshold is predetermined by the amount of the video bit stream that can be optimally stored in the bit buffer; As long as the amount of data stored in the bit buffer exceeds the threshold, it is operable to skip portions of all the video bit streams to prevent portions of all the video bit streams from being supplied from the bit buffers to the decoding circuit. Video decoding apparatus. The video decoding apparatus of claim 1, wherein the video bit stream control circuit changes the threshold value in proportion to a reproduction speed of the decoded picture. The video decoding apparatus of claim 2, wherein the video bit stream control circuit is operable to skip a part of the video bit stream on a picture basis as long as the amount of data stored in the bit buffer exceeds the threshold. . 3. The video bit stream control circuitry of claim 2, wherein the video bit stream control circuitry comprises a Video Buffering Verifier (VBV) buffer size, bit rate and picture rate defined by a sequence header included in the video bit stream, and a normal playback speed. And varying the threshold based on a multiplier of the actual playback rate for. A video decoding apparatus for generating a decoded picture by decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture, and a B-picture. A bit buffer for temporarily storing the video bit stream; Decoding circuitry for receiving the video bit stream output from the bit buffer and decoding the video bit stream to produce a decoded picture; And Operatively connected to the bit buffer and the decoding circuit, for controlling the amount of the video bit stream to be supplied from the bit buffer to the decoding circuit based on the data amount of the video bit stream stored in the bit buffer. Video bit stream control circuit The control circuit includes Determine whether the amount of data stored in the bit buffer exceeds a first threshold, the first threshold being predetermined as the amount of the video bit stream that can be optimally stored in the bit buffer, and determining the decoded picture Change the first threshold in proportion to a playback speed of And to allow the video bit stream of the I-picture and the P-picture to be supplied to the decoding circuit as long as the amount of data stored in the bit buffer exceeds the first threshold, Operate to skip the video bit stream to prevent the video bit stream of the B-picture from being supplied from the bit buffer to the decoding circuit. Video decoding apparatus, characterized in that. 6. The video bit stream control circuit of claim 5, wherein the video bit stream control circuit is further configured to convert the video bit stream stored in the bit buffer after the video bit stream of the I-picture or the P-picture is supplied from the bit buffer to the decoding circuit. And skips the video bit stream of the B-picture to be supplied next, even when the amount of data is less than the first threshold. The method of claim 5, The determining means determines whether the amount of data stored in the bit buffer exceeds the first threshold value and a second threshold value greater than the first threshold value, The video bit stream control circuit controls the B- when the amount of data stored in the bit buffer exceeds the first threshold after the video bit stream of the I-picture or the P-picture is supplied to the decoding circuit. Skips the video bit stream of a picture, and after the video bit stream of the P-picture is supplied to the decoding circuit, when the amount of data stored in the bit buffer exceeds the second threshold value of the B-picture Skipping the video bit stream Video decoding apparatus, characterized in that. 8. The video bit stream control circuitry of claim 7, wherein the video bit stream control circuitry is configured to display a video buffering checker (VBV) buffer size, bit rate and picture rate defined by a sequence header included in the video bit stream, and to reproduce the normal playback speed. And varying the first and second threshold values based on a multiplier of speed. A video decoding apparatus for generating a decoded picture by decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture, and a B-picture. A video bit stream analyzer for determining the shape of each picture included in the video bit stream and for analyzing the data amount of the video bit stream for each picture; A bit buffer for temporarily storing the video bit stream from the video bit stream analyzer; Decoding circuitry for receiving the video bit stream output from the bit buffer and decoding the video bit stream to generate a decoded picture; And Operatively connected to the bit buffer and the decoding circuit, for controlling the amount of the video bit stream to be supplied from the bit buffer to the decoding circuit based on the data amount of the video bit stream stored in the bit buffer. Video bit stream control circuit Including, The control circuit determines whether the amount of data stored in the bit buffer exceeds a threshold value, the threshold is predetermined by the amount of the video bit stream that can be optimally stored in the bit buffer, and the decoded picture And change the threshold in proportion to the playback speed of When the control circuit determines that the amount of data stored in the bit buffer exceeds the threshold, the control circuit operates to selectively skip a portion of the video bit stream on a picture basis such that the video bit stream is the bit buffer. From the supply to the decoding circuit, wherein the portion to be skipped is selected based on the type of each picture and the amount of data for each picture detected by the video bit stream analyzer. Decoding device. 10. The video bit stream control circuitry of claim 9, wherein the video bit stream control circuitry is configured to perform video buffering checker (VBV) buffer size, bit rate and picture rate defined by a sequence header included in the video bit stream, and to actual playback for normal playback speed. And varying the threshold value based on a magnification of the speed. A video decoding apparatus for generating a decoded picture by decoding a coded video bit stream including a series of I-pictures, P-pictures, and B-pictures. A bit buffer for temporarily storing the video bit stream, the bit buffer having a defined capacity by adding a value obtained by dividing a bit rate by a picture rate to a video buffering detector (VBV) buffer size; Decoding circuitry for receiving the video bit stream output from the bit buffer and decoding the video bit stream to generate a decoded picture; And A video operatively connected to the bit buffer and the decoding circuit for controlling the amount of the video bit stream to be supplied from the bit buffer to the decoding circuit based on the amount of data of the video bit stream stored in the bit buffer. Bit stream control circuit Including, The control circuit further comprises a first threshold indicating the amount of data stored in the bit buffer indicating the VBV buffer size, and a second threshold indicating the value obtained by adding the bit rate divided by the picture rate to the VBV buffer size. Determine whether or not The control circuitry is adapted to supply the video bit stream of the I-picture and the P-picture to the decoding circuit as long as the amount of data stored in the bit buffer is between the first threshold and the second threshold. Operate to permit, skipping the video bit stream of the B-picture to prevent the video bit stream of the B-picture from being supplied from the bit buffer to the decoding circuit, and to store the data stored in the bit buffer. Operate to skip a portion of the video bit stream regardless of the shape of the picture as long as the amount exceeds the second threshold. Video decoding apparatus, characterized in that. 12. The video bit stream control circuit of claim 11, wherein the video bit stream control circuit further comprises a picture header detector for determining a shape of a picture based on a picture header included in the video bit stream output from the bit buffer. Decoding device. 12. The video decoding apparatus of claim 11, wherein the bit buffer has a prescribed capacity by adding a value obtained by dividing the bit rate by the picture rate and a margin value to the VBV buffer size. A video decoding apparatus for generating a decoded picture by decoding a coded video bit stream including a series of pictures. A bit buffer for temporarily storing all the video bit streams regardless of a playback mode; Decoding circuitry for receiving the video bit stream output from the bit buffer and decoding the video bit stream to generate the decoded picture; And The read operation of the bit buffer and the decoding circuit based on the data amount of the video bit stream stored in the bit buffer, which is predetermined by the amount of the video bit stream and is below a threshold indicating the possibility of underflow of the bit buffer. An operation control circuit for controlling a decoding operation, wherein the operation control circuit reads the bit buffer when the amount of data is less than the threshold value for a period from when an underflow of the bit buffer occurs to when an underflow is released. Operate to prohibit the decoding operation of the decoding circuit and supply a decoded picture to the bit buffer; Video decoding apparatus comprising a. The readout of the bit buffer according to claim 14, wherein the operation control circuit determines whether the amount of data stored in the bit buffer is less than the threshold value, and as long as the amount of data stored in the bit buffer is smaller than the threshold value. And deactivate the decoding operation of the decoding circuit to supply an already decoded picture. 16. The video decoding apparatus of claim 15, wherein the threshold is set to a value obtained by multiplying the bit rate by the video buffering air delay (VBV) delay value. 15. The apparatus of claim 14, wherein the pictures comprise an I-picture, a P-picture, and a B-picture, and wherein the motion control circuitry is in the form of a picture based on a picture header included in the video bit stream output from the bit buffer. And if the underflow of the bit buffer occurs during decoding of the B-picture, skips the remaining portion of the video bit stream of the B-picture and continues decoding. 15. The apparatus of claim 14, wherein the pictures comprise an I-picture, a P-picture, and a B-picture, and the operation control circuitry is in the form of a picture based on a picture header included in the video bit stream output from the bit buffer. Determine if the underflow of the bit buffer occurs during decoding of the I-picture or the P-picture, interrupt the decoding, and after releasing the underflow, the video of the I-picture or P-picture And a video decoding apparatus for continuously decoding the bit stream. A video decoding apparatus for generating a decoded picture by decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture, and a B-picture. A video bit stream analyzer for determining the shape of each picture included in the video bit stream and for analyzing the data amount of the video bit stream for each picture; A bit buffer for temporarily storing the video bit stream from the video bit stream analyzer; Decoding circuitry for receiving the video bit stream output from the bit buffer and decoding the video bit stream to generate a decoded picture; A video operatively connected to the bit buffer and the decoding circuit, for controlling the amount of the video bit stream to be supplied from the bit buffer to the decoding circuit based on the amount of data of the video bit stream stored in the bit buffer. Bit stream control circuits; And Frame buffer for storing decoded pictures generated by the decoding circuit Including, The control circuit determines whether the amount of data stored in the bit buffer exceeds a threshold value, the threshold is predetermined by the amount of the video bit stream that can be optimally stored in the bit buffer, and the decoded picture Varying the threshold in proportion to the playback speed of When the control circuit determines that the amount of data stored in the bit buffer exceeds the threshold, the control circuit is operative to selectively skip a portion of the video bit stream in each picture such that the video bit stream is the bit. Prevent from being supplied to the decoding circuit from a buffer, wherein the portion to be skipped is selected based on the type of each picture and the amount of data of each picture, detected by the video bit stream analyzer, The frame buffer is A forward reference region for storing a decoded I-picture or P-picture to be used for backward prediction decoding to be executed by the decoding circuit; A backward reference region for storing a decoded I-picture or P-picture to be used for forward predictive decoding to be executed by the decoding circuit; And B-picture storage area for storing decoded B-pictures Including, And the video bit stream control circuit uses the B-picture storage area as the extension memory for the bit buffer when skipping the B-picture in the video stream. 20. The apparatus of claim 19, wherein the decoding circuit continuously generates two decoded I-pictures or P-pictures within one frame period, and the first I-picture or P as a reference picture in forward prediction decoding or backward prediction decoding. -Store the picture, and output a second I-picture or P-picture which is subsequently decoded as a playback picture. A video decoding apparatus for generating a decoded picture by decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture, and a B-picture. A video bit stream analyzer for determining the shape of each picture included in the video bit stream and for analyzing the data amount of the video bit stream for each picture; A bit buffer for temporarily storing the video bit stream from the video bit stream analyzer; Decoding circuitry for receiving the video bit stream output from the bit buffer and decoding the video bit stream to generate the decoded picture; And Operatively connected to the bit buffer and the decoding circuit, for controlling the amount of the video bit stream to be supplied from the bit buffer to the decoding circuit based on the data amount of the video bit stream stored in the bit buffer. Video bit stream control circuit Including, The control circuit determines whether the amount of data stored in the bit buffer exceeds a threshold value, the threshold is predetermined by the amount of the video bit stream that can be optimally stored in the bit buffer, and the decoded picture Varying the threshold in proportion to the playback speed of When the control circuit determines that the amount of data stored in the bit buffer exceeds the threshold, the control circuit is operative to selectively skip a portion of the video bit stream in each picture such that the video bit stream is the bit. Prevent from being supplied to the decoding circuit from a buffer, wherein the portion to be skipped is selected based on the type of each picture and the amount of data of each picture, detected by the video bit stream analyzer, The decoding circuit continuously generates two decoded I-pictures or P-pictures within one frame period, and stores the first I-picture or P-picture as a reference picture in forward prediction decoding or backward prediction decoding, And output a second I-picture or a P-picture to be decoded thereafter as a reproduction picture. A video decoding apparatus for generating a decoded picture by decoding a coded video bit stream including a series of pictures including an I-picture, a P-picture, and a B-picture. A bit buffer for temporarily storing the video bit stream; Decoding circuitry for receiving the video bit stream output from the bit buffer and decoding the video bit stream to generate the decoded picture; And An operation control circuit for controlling a read operation of the bit buffer and a decoding operation of the decoding circuit based on the amount of data of the video bit stream stored in the bit buffer, wherein the operation control circuit is configured to generate an underflow of the bit buffer. The video bit stream output from the bit buffer to supply an already decoded picture by operating to prohibit the read operation of the bit buffer and the decoding operation of the decoding circuit during a period from the time point to the time when underflow is released. Determine the shape of the picture based on a picture header included in the; interrupt the decoding if the underflow of the bit buffer occurs during decoding of the I-picture or the P-picture; The video bit of the I-picture or the P-picture It should continue to decode the stream - Video decoding apparatus comprising a. 23. The apparatus of claim 22, wherein the operation control circuitry is to decode a second I-picture or P-picture that is already stored in the backward reference region when a decoded first I-picture or P-picture is transmitted to the forward reference region. Or if a decoded B-picture stored in the B-picture storage area is read as a playback picture, and a decoded third I-picture or P-picture is transmitted to the reverse reference area, decode already stored in the forward reference area. And a decoded B-picture stored in said fourth I-picture or P-picture or said B-picture storage area is read as said playback picture.