JP3338426B2 - MPEG video decoder - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an MPEG (Moving
Picture Expert Group) relates to a video decoder.

[0002]

2. Description of the Related Art The information handled by multimedia is enormous and diverse, and it is necessary to process such information at high speed in order to put multimedia into practical use. In order to process information at high speed, data compression / decompression technology is indispensable. As such data compression / decompression technology, the “MPEG” method is exemplified. This MPEG system is based on the ISO (International Organization).
for Standardization) / IEC (International Elec)
trotechnical Commission)
It is being standardized by O / IEC JTC1 / SC29 / WG11).

[0003] MPEG is composed of three parts. Part 1 “MPEG System Part” (ISO / IEC
IS 11172 Part1: Systems) defines a multiplex structure (multiplex structure) of video data and audio data and a synchronization method. Part 2 "MPE
In the "G video part" (ISO / IEC IS 11172 Part2: Video), a high-efficiency encoding method of video data and a format of the video data are specified. Part 3, "MPEG
Audio Part ”(ISO / IEC IS 11172 Part3: Audio)
Defines a high-efficiency encoding method of audio data and a format of audio data.

[0004] The video data handled by the MPEG video part relates to a moving image, and the moving image is composed of several tens (eg, 30) frames (still images, frames) per second. Video data includes a sequence (Sequence), a GOP (Group Of Pictures), a picture, a slice (Slice), and a macro block (Macrob).
lock) and blocks in the order of 6 layers.

[0005] At present, MPEG-1 and MPEG-1 are mainly used due to differences in encoding rates.
-2. In MPEG-1, a frame corresponds to a picture. In MPEG-2, a frame or a field can correspond to a picture. Two fields constitute one frame. A structure in which a frame corresponds to a picture is called a frame structure, and a structure in which a field corresponds to a picture is called a field structure.

[0006] MPEG uses a compression technique called inter-frame prediction. Inter-frame prediction compresses data between frames based on temporal correlation. In the inter-frame prediction, bidirectional prediction is performed. The bidirectional prediction is to use both forward prediction for predicting a current reproduced image from a past reproduced image (or picture) and backward prediction for predicting a current reproduced image from a future reproduced image. .

[0007] This bidirectional prediction is based on an I-picture (Intra-Pi
), a P picture (Predictive-Picture), and a B picture (Bidirectionally predictive-Picture). The I picture is generated independently of a past or future reproduced image. The P picture is generated by forward prediction (prediction from a past I picture or P picture). B pictures are generated by bidirectional prediction. In bidirectional prediction, a B picture is generated by any one of the following three predictions. Forward prediction; prediction from past I or P pictures; backward prediction; prediction from future I or P pictures, bidirectional prediction; prediction from past and future I or P pictures. Then, these I, P, and B pictures are respectively encoded. That is, an I picture is generated even if there is no past or future picture. In contrast, a P picture is not generated without a past picture, and a B picture is not generated without a past or future picture.

In the inter-frame prediction, first, an I picture is periodically generated. Next, a frame several frames ahead of the I picture is generated as a P picture. This P
The picture is generated by one-way (forward) prediction from the past to the present. Subsequently, a frame located before the I picture and after the P picture is generated as a B picture. When generating this B picture, an optimal prediction method is selected from three of forward prediction, backward prediction, and bidirectional prediction. In general, in a continuous moving image, a current image and images before and after the current image are very similar, and only a part thereof is different. Then, the previous frame (for example, I
Assuming that the picture and the next frame (for example, a P picture) are the same, if there is a change between both frames, only the difference (B picture data) is extracted and compressed.
Thus, data between frames can be compressed based on temporal correlation.

The data sequence (bit stream) of video data encoded in accordance with the MPEG video part is called an MPEG video stream (hereinafter, abbreviated as video stream). By the way, MPEG
-1 is mainly for Video CD (Compact Disc) and CD-ROM
(CD-Read Only Memory) and other storage media using MPEG-2.
It supports a wide range of applications, including.

[0010] In the storage medium, the following three special reproduction functions are required. A function to play videos at a higher speed than normal playback speed (hereinafter referred to as high-speed playback).
A function to play moving images at a lower speed than the normal playback speed (hereinafter referred to as low-speed playback). A function for playing back moving images one frame at a time (hereinafter referred to as frame-by-frame playback). The high-speed playback function
For example, it is used when the user performs fast-forward playback to view a moving image in a short time, or when performing fast-forward playback or fast-forward reverse playback to search for a desired moving image. The low-speed playback function and the frame-by-frame playback function are used, for example, when a user watches a moving image carefully.

FIG. 8 shows a conventional MP having a high-speed reproduction function.
3 shows a main block circuit of the EG video decoder. MPE
The G video decoder 101 includes a bit buffer 102, a picture header detection circuit 103, an MPEG video decode core circuit (hereinafter, abbreviated as a decode core circuit) 104, a video stream skip circuit 105, and a control core circuit 10.
6.

The control core circuit 106 includes circuits 102 to 10
5 is controlled. A video stream read from a recording medium such as a video CD is transferred to the bit buffer 102 via the video stream skip circuit 105.
The bit buffer 102 is a FIFO (First-In-First-Ou)
t) A ring buffer composed of a random access memory (RAM) having a configuration, and sequentially accumulates video streams transferred from the video stream skip circuit 105.

The picture header detection circuit 103 detects a picture header at the head of each picture of the video stream stored in the bit buffer 102. The control core circuit 106 reads a video stream for one picture every one frame period from the bit buffer 102 based on the detection result of the picture header detection circuit 103. In MPEG-1, a moving image is composed of 30 frames (frames) per second, and one frame period is 1/30 second.

The decode core circuit 104 decodes each picture read from the bit buffer 102 in accordance with the MPEG video part, and generates a video output for each picture. The video output is output to a display 107 provided outside the MPEG video decoder 101. The reason why the bit buffer 102 is provided is that the data amounts of the I, P, and B pictures are different. The data amount of the I picture is about 30 kbytes,
The data amount of the P picture is about 10 to 15 kbytes, and the data amount of the B picture is 0 to about 6 kbytes. On the other hand, the bit rate RB of the video stream read from the recording medium during normal reproduction is constant. The decode core circuit 104 performs decoding for each picture, and the decoding processing time differs depending on the data amount of each picture. Therefore, when the video stream read from the recording medium is directly transferred to the decode core circuit 104, some pictures cannot be decoded by the decode core circuit 104. To prevent this, by providing a bit buffer 102 as a buffer memory for a video stream read from a recording medium, I, P,
The difference in the data amount of each picture of B is absorbed.

The video stream skip circuit 105
At the time of normal reproduction, the video stream read from the recording medium is connected to the node 105a side and transferred to the bit buffer 102 as it is. At the time of high-speed reproduction, the connection to each of the nodes 105a and 105b is switched in accordance with the reproduction speed, and the video stream read from the recording medium is intermittently switched according to the reproduction speed.
Transfer to That is, when the video stream skip circuit 105 is connected to the node 105b, the video stream read from the recording medium is transmitted to the bit buffer 10b.
2 and skipped. As a result, the video stream transferred to the bit buffer 102 is thinned out by the amount skipped by the video stream skip circuit 105.

As described above, the bit rate RB of the video stream read from the recording medium during normal reproduction
Is constant. Therefore, it is necessary to control the occupancy of the bit buffer 102 so that the data amount of the video stream for one picture does not overflow or underflow due to too much or too little data. Therefore, in the MPEG video part, a virtual MPEG video decoder is assumed, and a definition for it is made.

FIG. 9 shows a change in the occupancy of the bit buffer 102 during normal reproduction. Bit buffer 10
The occupancy Bm of 2 rises with the bit rate RB as the slope of the graph. The bit rate RB is defined as shown in equation (1) according to the BR (Bit Rate) of the sequence header at the beginning of the sequence. The picture rate RP of the video stream read from the recording medium is defined by the PR (Picture Rate) of the sequence header. The capacity B of the bit buffer 102 is determined by the VBV (Vbv [Video Buffering Verifie
r] Buffer Size) as defined in equation (2). Then, for each frame period, a video stream for one picture that the decode core circuit 104 is to decode at that time is read from the bit buffer 102 at a stretch. Here, the data amount X of the video stream read from the recording medium and input to the bit buffer 102 during one frame period is defined as shown in Expression (3) according to the bit rate RB and the picture rate RP. Therefore, the occupation amount Bm (= B0 to B6) of the bit buffer 102 immediately after the video stream for one picture is read at a stretch from the bit buffer 102 is determined based on the data amount X and the capacity B of the bit buffer 102.
It is defined so as to satisfy the condition shown in Expression (4).

RB = 400 × BR (1) B = 16 × 1024 × VBV (2) X = RB / RP (3) 0 <Bm <BX = B− (RB) / RP) (4) The bit buffer 10 is set so as to satisfy the condition shown in the equation (4).
If the occupation amount Bm of 2 is specified, the bit buffer 1
02 does not overflow or underflow. Conversely, when the occupation amount Bm of the bit buffer 102 exceeds the threshold value (BX), the possibility that the bit buffer 102 overflows due to the video stream input to the bit buffer 102 in the next one frame period is extremely high. Become.

At the time of normal reproduction, the bit rate RB and the picture rate RP are set so that the equation (4) is satisfied.
, And the capacity B are defined. Therefore, equation (2)
If the capacity B of the bit buffer 102 is set as shown in (1), the bit buffer 102 does not overflow or underflow. However, in the actual bit buffer 102, in order to reliably prevent the overflow, the capacity is calculated by adding a margin α in consideration of the decoding processing time of the decode core circuit 104 to the capacity B shown in Expression (2). Is set. Normally, the margin α
Is set to a value similar to the data amount X shown in Expression (3). For example, in a video CD, the capacity B is 46 kbytes,
Since the data amount X is defined as 6 kbytes, the actual capacity of the bit buffer 102 is 52 k (= B + X = 46
(k + 6k) bytes.

During high-speed reproduction, the bit rate of the video stream read from the recording medium increases according to the reproduction speed. That is, when performing high-speed playback at n times the normal playback speed, the bit rate of the video stream read from the recording medium is n times (= n × RB) the bit rate RB during normal playback. Become. However, as described above, since the capacity B of the bit buffer 102 is set corresponding to normal reproduction, when the bit rate of the video stream becomes n × RB, the bit buffer 10
2 will overflow. Therefore, at the time of high-speed reproduction, the video stream transferred to the bit buffer 102 is thinned out by controlling the video stream skip circuit 105 as described above. as a result,
The bit rate of the video stream transferred to the bit buffer 102 is substantially equal to the bit rate RB during normal reproduction, and the overflow of the bit buffer 102 is avoided.

[0021]

The conventional MPEG video decoder 101 has the following problems. At the time of normal reproduction, as shown in equation (2), the bit buffer 102
Is set, the bit buffer 102 does not overflow in an ideal state. However, in an actual state, even if the capacity B of the bit buffer 102 is set as shown in Expression (2), the bit buffer 102 may overflow in the following cases.

(1) When the bit rate RB of the video stream read from the recording medium is not synchronized with the bit rate of the video output, and the bit rate RB is higher than the bit rate of the video output. (2) When the video stream read from the recording medium is not encoded as specified.

Since the bit buffer 102 is constituted by a ring buffer, when an overflow occurs, a newly input video stream is overwritten on a video stream already stored in the bit buffer 102. As a result, the bit buffer 10
2 is destroyed and lost.

For example, if the bit buffer 102 overflows during the decoding of an arbitrary picture in the decode core circuit 104, a portion of the picture being decoded that is left in the bit buffer 102 is newly input. The video stream is overwritten. As a result, the portion of the picture being decoded that remains in the bit buffer 102 is destroyed and lost. Then, the decoding core circuit 104 cannot complete the decoding of the picture, and cannot generate a video output of the picture.

As described above, a P picture cannot be generated without a past picture, and a B picture cannot be generated without a past or future picture. Only I pictures can be generated without past or future pictures. Therefore, if the picture being decoded at the time when the bit buffer 102 overflows is an I picture or a P picture, of the pictures in the video stream stored in the bit buffer 102, Cannot decode all P pictures and B pictures up to the I picture read out. That is, in the decode core circuit 104, the bit buffer 1
The decoding process cannot be restarted from 02 until the next I picture is read.

As described above, when the bit buffer 102 overflows, a large number of pictures cannot be decoded, so that the moving picture reproduced by the number of these pictures is dropped. As a result, the motion of the moving image is not smooth but jerky, and the image quality is deteriorated to make it hard to see. At the time of high-speed reproduction, control of the video stream skip circuit 105 is extremely complicated. Therefore, the control core circuit 1 that controls the video stream skip circuit 105
06 must be configured using a microcomputer. Therefore, an increase in cost and an increase in the size of the entire apparatus due to the provision of the microcomputer cannot be avoided.

Since the control of the video stream skip circuit 105 at the time of high-speed reproduction is performed according to the reproduction speed, the video stream skipped from the node 105b becomes irrelevant to the picture. Therefore, at the time of high-speed playback, the video stream transferred from the video stream skip circuit 105 to the bit buffer 102 includes a picture in which data is interrupted on the way, and the video stream stored in the bit buffer 102 is not. Be continuous.

When a video stream becomes discontinuous and an I picture or P picture is interrupted, all P pictures and B pictures can be generated until the next I picture is transferred to the bit buffer 102. Disappears. That is, at the time of high-speed reproduction, the decode core circuit 104 can decode only an I picture in which data is not interrupted in the middle.

The rate at which an I picture is included in the video stream read from the recording medium is at most 1-2
Seconds. For this reason, at the time of relatively slow high-speed reproduction of 2 to 4 times, frames are dropped in a moving image reproduced for pictures that cannot be decoded, and only 1 to 2 frames / second can be displayed. As a result, it is possible to obtain only a very inferior moving image similar to the frame-by-frame playback, even though the playback is at a high speed. In other words, the motion of the moving image is not smooth but jerky, and the image quality is deteriorated, making it hard to see.

For example, when a video CD is used as a recording medium, a track jump method is used. In this system, an optical pickup of a video CD player is repeatedly scanned between recording tracks of a video CD (one round of the CD), and an operation of reading a certain amount of video stream and then jumping to another recording track is repeated. Then, if an I picture happens to be included in the video stream read from the video CD, the I picture is decoded. In this case, it is impossible to decode all I pictures in the video stream read from the video CD, and some I pictures cannot be decoded. Only 1 to 0.5 frames / sec can be displayed. In addition, since the number of I-pictures included in a video stream read at one time from a video CD is not constant (one I-picture may not be able to be read),
The interval between one frame and one frame is not constant, and only very poor moving images can be obtained.

However, in the Video CDv2.0 standard, the I picture scan method is used. In this method, information of a recording track in which an I picture is stored in a video stream is defined. That information is called "scan information". By controlling the optical pickup of the video CD player using the scan information, it becomes possible to decode all the I pictures in the video stream read from the video CD. However, even in this case, as described above, at the time of relatively slow high-speed reproduction of 2 to 4 times, 1 to 2
Only frames / second can be displayed.

By the way, I, P,
In addition to the three types of B pictures, D pictures are defined. D picture is DCT (Discrete Cosine Tran
It consists of only DC (Direct Current) components of the (sform) coefficients and does not coexist in the same sequence as the I, P, and B pictures. The D picture is defined on the assumption that fast forward playback or fast forward reverse playback is performed when a user searches for a moving image to be viewed. However, since D-pictures are rarely included in the video stream,
Even when high-speed reproduction is performed based on D-pictures, at relatively low-speed reproduction of 2 to 4 times, the motion of the moving image is not smooth and the image quality is deteriorated.

The present invention has been made to solve the above problems, and has the following objects. 1] To provide an MPEG video decoder capable of avoiding overflow of a bit buffer. 2) To provide an MPEG video decoder capable of both improving the image quality by smoothing the motion of a moving image during special reproduction and avoiding overflow of a bit buffer.

[0034]

An MPEG video decoder according to claim 1, wherein: a bit buffer; a decode core circuit for decoding each picture read from the bit buffer in accordance with an MPEG video part; When the occupancy exceeds the threshold, the picture supplied from the bit buffer to the decode core circuit is not transferred to the decode core circuit until the occupancy falls below the threshold. And a judgment control circuit for skipping the moving image.
The point is that the threshold value is variably set based on the reproduction speed .

An MPEG video decoder according to a second aspect of the present invention includes a bit buffer for storing a video stream, a decode core circuit for decoding each picture read from the bit buffer in accordance with an MPEG video part,
A threshold value of the occupancy of the bit buffer is set based on the playback speed of the moving image. When the occupancy exceeds the threshold, the occupancy is supplied from the bit buffer to the decode core circuit until the occupancy falls below the threshold. The gist of the invention is to provide a determination control circuit for skipping a picture without transferring it to the decode core circuit.

An MPEG video decoder according to a third aspect of the present invention includes a bit buffer for storing a video stream, a decode core circuit for decoding each picture read from the bit buffer in accordance with an MPEG video part,
A threshold value for the occupancy of the bit buffer is set based on the playback speed of the moving image. When the occupancy exceeds the threshold, the picture supplied from the bit buffer to the decode core circuit until the occupancy falls below the threshold. And a decision control circuit that skips only B pictures and does not skip P pictures and I pictures.

According to a fourth aspect of the present invention, in the MPEG video decoder according to any one of the first to third aspects, the determination control circuit determines that the occupation amount of the bit buffer is equal to or smaller than a threshold value after reading the I picture or the P picture. , The next picture read from the bit buffer is B
The gist is to skip a picture .

According to a fifth aspect of the present invention, in the MPEG video decoder according to any one of the first to fourth aspects, the decoding core circuit includes one frame for reducing the occupation amount of data in the bit buffer. 2 in the period
One P picture is decoded, and the P picture decoded first is treated as intermediate data for performing forward prediction of the P picture decoded later, and is not played back. Only the P picture decoded later is used as a playback picture. The gist is to treat.

According to a sixth aspect of the present invention, in the MPEG video decoder according to any one of the first to fourth aspects, the MPEG video decoder further comprises a frame buffer for storing a decoding result of each picture generated by the decoding core circuit. The inside of the buffer is divided into three areas: a forward reference area, a backward reference area, and a B picture storage area, and the decode core circuit decodes two P pictures within one frame period, and Is to treat only decoded P-pictures as intermediate data for performing forward prediction and not to play back them. The intermediate data is stored in the B-picture storage area, and only P-pictures decoded later are treated as reproduced pictures. Is the gist.

According to a seventh aspect of the present invention, in the MPEG video decoder according to any one of the first to seventh aspects, the threshold value is a buffer size (Vb) defined by a sequence header attached to the head of a video stream sequence.
v. Buffer Size), Bit Rate, Picture Rate, and the ratio (n) of the actual playback speed to the normal playback speed.

[0041]

(First Embodiment) A first embodiment of the present invention will be described below with reference to FIGS. FIG. 1 shows an MP of this embodiment having a high-speed playback function.
3 shows a main block circuit of the EG video decoder.

The MPEG video decoder 1 comprises a bit buffer 2, a picture header detection circuit 3, an MPEG video decode core circuit (hereinafter abbreviated as a decode core circuit) 4,
It comprises a variable threshold overflow determination circuit (hereinafter abbreviated as a determination circuit) 5, a picture skip circuit 6, and a control core circuit 7. Each of the circuits 3 to 7 is a one-chip LSI.
It is installed in.

The control core circuit 7 controls each of the circuits 2 to 6. A video stream read from a recording medium such as a video CD is transferred to the bit buffer 2. The bit buffer 2 is constituted by a ring buffer composed of a RAM having a FIFO structure, and sequentially accumulates the transferred video stream as it is. The reason why the bit buffer 2 is provided is to absorb the difference in the data amount of each of I, P, and B pictures, similarly to the case where the bit buffer 102 is provided in the conventional MPEG video decoder 101. .

The picture header detection circuit 3 detects a picture header at the head of each picture of the video stream stored in the bit buffer 2, and determines the picture type (I, P, B) specified in each picture header. ) Is detected. The control core circuit 7 reads a video stream of an appropriate picture from the bit buffer 2 every frame period based on the detection result of the picture header detection circuit 3 and the determination result of the determination circuit 5 described later. The video stream read from the bit buffer 2 remains in the bit buffer 2 even after being read.

Each picture read from the bit buffer 2 is transferred to the decode core circuit 4 via the picture skip circuit 6. The decode core circuit 4 decodes each picture according to the MPEG video part and generates a video output for each picture. Its video output is
It is output to a display 8 provided outside the MPEG video decoder 1.

In the picture skip circuit 6, the connection to each of the nodes 6a and 6b is switched under the control of the control core circuit 7. When the picture skip circuit 6 is connected to the node 6a, the picture read from the bit buffer 2 is transferred to the decode core circuit 4 as it is. When connected to the node 6b, the picture read from the bit buffer 2 is skipped without being transferred to the bit buffer 2. As a result, the picture transferred to the decode core circuit 4 is a picture skip circuit 6
Is skipped in picture units by the amount skipped.

The determination circuit 5 determines a threshold value Bth of the occupation amount Bm of the bit buffer 2 based on an externally designated reproduction speed.
n, the occupancy Bm of the bit buffer 2 and the threshold Bth
Compare with n. The external reproduction speed is specified by a magnification n with respect to the normal reproduction speed. For example, at the time of 2 × speed reproduction, the magnification n = 2, and the threshold Bthn =
Bth2. During normal reproduction, the magnification n = 1, and the threshold value Bthn = Bth1.

The determination circuit 5 determines whether the bit buffer 2
If the occupation amount Bm does not exceed the threshold value Bthn, it is determined that there is no risk of the bit buffer 2 overflowing and that the bit buffer 2 is normal. In this case, the control core circuit 7 reads a video stream for one picture from the bit buffer 2. Then, the control core circuit 7 connects the picture skip circuit 6 to the node 6a side, and transfers the picture read from the bit buffer 2 to the decode core circuit 4.

When the occupancy Bm of the bit buffer 2 exceeds the threshold value Bthn, the determination circuit 5 determines that the bit buffer 2 may overflow. In this case, the control core circuit 7 reads a video stream of an appropriate picture from the bit buffer 2 until the occupation amount Bm of the bit buffer 2 falls below the threshold value Bthn. Then, the control core circuit 7 connects the picture skip circuit 6 to the node 6b side, and skips all video streams for appropriate pictures read from the bit buffer 2.

FIG. 2 shows a change in the occupancy Bm of the bit buffer 2 in this embodiment. As described above, the occupation amount Bm of the bit buffer 2 during normal reproduction increases with the bit rate RB as the slope of the graph. In the MPEG video decoder 1 of the present embodiment, the conventional MP
Similarly to the EG video decoder 101, at the time of normal reproduction, the bit rate R is set so that Expression (4) is satisfied.
B, picture rate RP, and capacity B are specified. That is, if the capacity B of the bit buffer 2 is set as shown in the equation (2), even if the connection of the picture skip circuit 6 is fixed to the node 6a side, in an ideal state, the bit buffer 2 Does not overflow or underflow.

Therefore, during normal reproduction, the occupation amount Bm (= B0 to B4) immediately after the data for one picture is read from the bit buffer 2 at a stretch is calculated by the equation (5) based on the threshold value Bth1. It is defined so as to satisfy the conditions shown. Note that the threshold value Bth1 is calculated based on the equation (4) and the equation (6).
Are set as shown in FIG. 0 <Bm <Bth1 <B (5) Bth1 = BX = B- (RB / RP) (6) By the way, in the actual state, the bit buffer 2 as shown in the equation (2) is obtained. Even if the capacity B is set, if the connection of the picture skip circuit 6 is fixed to the node 6a side,
In the cases (1) and (2), the bit buffer 2 may overflow.

However, in the present embodiment, if the occupation amount Bm of the bit buffer 2 exceeds the threshold value Bth1 during normal reproduction, it is determined that the bit buffer 2 may overflow. Then, until the occupation amount Bm of the bit buffer 2 falls below the threshold value Bth1, the bit buffer 2
, A video stream for an appropriate picture is read. Then, the picture skip circuit 6 is connected to the node 6b side, and all video streams for appropriate pictures read from the bit buffer 2 are skipped. Therefore, according to the present embodiment, the bit buffer 2 does not overflow during normal reproduction even in the cases (1) and (2).

The occupation amount Bm of the bit buffer 2 at the time of high-speed reproduction increases with the bit rate n × RB as a gradient of the graph. For example, the occupation amount Bm of the bit buffer 2 at the time of 2 × speed reproduction increases with the bit rate 2 × RB as the slope of the graph. Therefore, at the time of high-speed reproduction, the occupation amount Bm (= B0 to B4) immediately after the data for one picture is read at a stretch from the bit buffer 2 is equal to the threshold value Bth.
Based on n, it is defined so as to satisfy the condition shown in Expression (7). Note that the threshold value Bthn is set as shown in Expression (8).

0 <Bm <Bthn (7) Bthn = Bn × X = B− (n × RB / RP) (8) At the time of high-speed reproduction, the occupancy Bm of the bit buffer 2
Exceeds the threshold value Bthn, it is determined that the bit buffer 2 may overflow. For example, at the time of double-speed reproduction, the occupation amount Bm is equal to the threshold Bth2 (= B− (2 × RB
/ RP)), the occupation amount Bm at 3 × speed playback
Exceeds the threshold value Bth3 (= B- (3.times.RB / RP)), it is determined that the bit buffer 2 may overflow. Then, the occupation amount B of the bit buffer 2
Until m becomes smaller than the threshold value Bthn, a video stream for an appropriate picture is read from the bit buffer 2, and all the video streams are skipped. Therefore, according to the present embodiment, at the time of high-speed reproduction, the bit buffer 2 does not overflow even in the case (2).

If the bit buffer 2 overflows while the decoding core circuit 4 is decoding an arbitrary picture, a newly input video stream is added to the remaining portion of the bit buffer 2 of the picture being decoded. Is overwritten. As a result, the portion of the picture being decoded that remains in the bit buffer 2 is destroyed and lost. Then, the decoding core circuit 4 cannot complete the decoding of the picture, and cannot generate a video output of the picture. Therefore, it is absolutely necessary to prevent the bit buffer 2 from overflowing while the decoding core circuit 4 is decoding an arbitrary picture.

Therefore, it is necessary to determine whether or not the bit buffer 2 may overflow before the decoding core circuit 4 starts decoding an arbitrary picture. More precisely, when the picture header detection circuit 3 detects the picture header, it is determined whether or not the bit buffer 2 may overflow, and whether or not the picture is skipped via the picture skip circuit 6 is determined. There is a need to.

By the way, the data amount of one picture is 0
Although the data amount is up to 40 bytes, the data amount cannot be known until the decoding at the decoding core circuit 4 is completed. Although the decoding processing time of one picture varies depending on the data amount of the picture and the operation speed of the decoding core circuit 4, usually, the decoding processing time is one-third to three-thirds of one frame period.
It is about 4.

When the data amount of the picture read from the bit buffer 2 is 0 bytes, the occupation amount Bm of the bit buffer 2 does not change before and after the reading of the picture, so that even if the picture is skipped, overflow is avoided. It is not possible. Conversely, even if the data amount of the picture read from the bit buffer 2 is 0 bytes, there is no overflow if the bit buffer 2 has a sufficient free space.

Therefore, a free space for the data amount of the video stream read from the recording medium and input to the bit buffer 2 during one frame period is secured in the bit buffer 2. Then, even if the data amount of the picture read from the bit buffer 2 is 0 bytes, no overflow occurs. The data amount of the video stream read from the recording medium and input to the bit buffer 2 during one frame period is (n × X = n × RB / RP). If the free space of the bit buffer 2 is equal to or more than this data amount, no overflow occurs. Therefore, if the threshold value Bthn is set as shown in Expression (8), the overflow of the bit buffer 2 can be reliably avoided.

That is, the determination circuit 5 checks the free space of the bit buffer 2 when the picture header detection circuit 3 detects the picture header, and determines that the free space (n
It is determined whether or not × X = n × RB / RP) is secured. If a sufficient free space is not secured, the control core circuit 7 skips the picture read from the bit buffer 2 via the picture skip circuit 6 based on the picture header. Subsequently, when the picture header detection circuit 3 detects the next picture header, the determination circuit 5 checks the free space of the bit buffer 2 again. Since the time required for these processes is much shorter than the decoding process time of the decode core circuit 4, even if the decoding process of the decode core circuit 4 is started after a sufficient free space is secured in the bit buffer 2, In time.

Incidentally, the bit buffer 2 may underflow when the picture header detection circuit 3 detects a picture header or after the decoding core circuit 4 starts decoding. In this case, there is no particular problem since a video stream for one picture may be sequentially read from the bit buffer 2 as soon as the video stream read from the recording medium is input to the bit buffer 2.

As described in detail above, according to the present embodiment,
The following effects can be obtained. At the time of normal reproduction, it is possible to avoid overflow of the bit buffer 2 including the cases described in (1) and (2). At the time of high-speed reproduction, the overflow of the bit buffer 2 can be avoided, including the case shown in (2).

By providing the decision circuit 5 and the picture skip circuit 6, it is possible to avoid the overflow of the bit buffer 2 without providing the video stream skip circuit 105 as in the conventional MPEG video decoder 101. As described above, since the control of the determination circuit 5 and the picture skip circuit 6 is simple, the control core circuit 7 does not need to be configured using a microcomputer. Each of the circuits 3 to 7 is a one-chip LSI.
It is installed in. Therefore, according to the present embodiment, the cost does not increase and the entire device does not increase in size as in the conventional example.

The video stream skipped from the node 6b side of the picture skip circuit 6 is a picture unit. Therefore, data is not interrupted in the middle of a picture transferred to the decode core circuit 4. Therefore,
The decode core circuit 4 can decode not only an I picture but also a P picture and a B picture. As a result, dropped frames occurring in the moving image reproduced on the display 8 are reduced. Therefore, it is possible to display several frames per second at the time of relatively slow high-speed reproduction of 2 to 4 times.
Therefore, the motion of a moving image during high-speed playback can be smoothed, and the image quality can be greatly improved.

(Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. The configuration of the MPEG video decoder of the present embodiment is the same as that of the first embodiment. In the present embodiment, two thresholds B2thn and B3thn are set so as to satisfy the rule shown in Expression (9). The values of the thresholds B2thn and B3thn are the first values.
While being set according to the playback speed as in the embodiment,
The image quality of the moving image reproduced on the display 8 may be actually considered and appropriately set.

0 <B3thn <B2thn <B (9) The determination circuit 5 compares the occupancy Bm of the bit buffer 2 with the thresholds B3thn and B2thn, and the occupancy Bm is calculated by the equation (10).
It is determined in which area shown in (12). Bm <B3thn ... (10) B3thn <Bm <B2thn ... (11) B2thn <Bm ... (12) The determination circuit 5 calculates the occupation amount Bm of the bit buffer 2 as shown in Expression (10). Does not exceed the threshold value B3thn, it is determined that the bit buffer 2 is normal without any risk of overflow. In this case, the control core circuit 7 reads a video stream for one picture from the bit buffer 2. Then, the control core circuit 7 connects the picture skip circuit 6 to the node 6a side, and transfers the picture read from the bit buffer 2 to the decode core circuit 4.

The determination circuit 5 determines, as shown in equation (12),
When the occupation amount Bm of the bit buffer 2 exceeds the threshold value B2thn and does not exceed the threshold value Bthn, if the picture read from the bit buffer 2 is an I picture or a P picture, a first flag is set. If the occupation amount Bm of the bit buffer 2 exceeds the threshold value B3thn and does not exceed the threshold value B2thn as shown in Expression (11), the bit buffer 2
If the picture read from is a P picture, a second flag is set. When the first or second flag is set, the control core circuit 7 sets the
If the picture read from the bit buffer 2 is a B picture, the picture skip circuit 6 is connected to the node 6b to skip the picture.

FIG. 3 shows a change in the occupancy Bm of the bit buffer 2 in this embodiment. Occupancy Bm is equal to threshold B2t
If the value exceeds hn, the picture read from the bit buffer 2 is skipped without decoding if it is a B picture (illustrated * 1). Here, even if the occupation amount Bm still exceeds the threshold value B3thn after skipping the B picture, if the picture read next from the bit buffer 2 is an I picture or a P picture, decoding is performed (illustration * 2).

Even when the occupation amount Bm exceeds the threshold value B2thn, if the picture read from the bit buffer 2 is an I picture or a P picture, decoding is performed (see FIG.
3). Here, if the occupation amount Bm still exceeds the threshold value B3thn after the decoding of the I picture or the P picture, if the picture read out next from the bit buffer 2 is a B picture, the picture is skipped without decoding (* in the figure).
4). This skipping of the B picture is repeated until the occupation amount Bm falls below the threshold value B3thn (illustrated * 5).

When the occupation amount Bm exceeds the threshold value B2thn, if the picture read from the bit buffer 2 is an I picture or a P picture, the determination circuit 5 sets a first flag (illustrated * 6). When the first flag is set, if the next picture read from the bit buffer 2 is a B picture, the B picture is skipped even if the occupation amount Bm is less than the threshold value B3thn (illustrated *).
7).

When the occupation amount Bm exceeds the threshold B3thn and the threshold B
When the value does not exceed 2thn, if the picture read from the bit buffer 2 is a P picture, the determination circuit 5 sets a second flag (illustration * 8). When the second flag is set, if the next picture read from the bit buffer 2 is a B picture, the B picture is skipped even if the occupation amount Bm is less than the threshold value B3thn (illustrated *).
9).

When the occupation amount Bm exceeds the threshold value B3thn and the threshold value B
If it does not exceed 2thn, and the picture read from the bit buffer 2 is an I picture, the decision circuit 5
Is not set (illustration * 10). When the second flag is not set, if the occupation amount Bm is smaller than the threshold value B3thn, decoding is performed even if the next picture read from the bit buffer 2 is a B picture.

As described in detail above, according to the present embodiment,
The following effects can be obtained in addition to the effects of the first embodiment. When the occupation amount Bm of the bit buffer 2 exceeds the threshold value B3thn and does not exceed the threshold value Bthn, the I picture and the P picture are decoded as much as possible, and the B picture is skipped with priority.

Since a B picture is generated by bidirectional prediction, its importance is lower than that of an I picture or a P picture. Therefore, by skipping the B-picture of low importance with priority, it is possible to reduce the number of dropped frames that occur in the moving image reproduced on the display 8 as compared with the first embodiment. As a result, the motion of the moving image during high-speed playback can be further smoothed, and the image quality can be further improved.

By setting the first flag, the bit buffer 2 is decoded after decoding the I picture or the P picture.
Even if the occupation amount Bm of the image data is smaller than the threshold value B3thn, it is possible to skip the B picture to be read from the bit buffer 2 in advance with a margin. Also, by setting the second flag, even if the occupation amount Bm of the bit buffer 2 becomes lower than the threshold value B3thn after decoding the P picture, the B picture read out from the bit buffer 2 is skipped in advance with a margin. Can be.

In this way, skipping the B picture in advance is nothing but taking a preventive measure against the next overflow of the bit buffer 2. Therefore, overflow of the bit buffer 2 can be avoided more reliably. The data amount of the I picture is as large as two to three times that of the P picture. Therefore, the degree of reduction in the occupation amount Bm of the bit buffer 2 is greater when an I picture is read than when a P picture is read. Therefore,
The likelihood of the bit buffer 2 overflowing after the I picture has been read is smaller than after the P picture has been read. Therefore, by setting the first and second flags, the precautionary measures are differentiated between the I picture and the P picture. That is, by setting the threshold B2thn of the precautionary measure for the I picture to a value higher than the threshold B3thn of the precautionary measure for the P picture, the precautionary measure for the I picture can be less strict than that of the P picture. As a result, unnecessary skips of B pictures can be reduced.

When a video stream having the following GOP configuration (arrangement of picture types) shown in a) and b) is read from a recording medium, the effect of the present embodiment at the time of high-speed reproduction is simulated. The results shown were obtained. a) IBPBPBPBP... b) IBBPBBPBBPBBPBBIBP... [1] At the time of double-speed playback; . In the case of b), all of the I and P pictures and a part of the B picture can be decoded, and as a result, they can be displayed at 25 frames / second or more.

[2] During quadruple-speed playback; a) and b) can decode the I picture and the following three to four P pictures, and as a result, display at 15 frames / second or more. (Third Embodiment) Next, a third embodiment of the present invention will be described with reference to FIG. In this embodiment,
The same components as those in the first embodiment have the same reference numerals, and a detailed description thereof will be omitted.

FIG. 4 shows a block diagram of a main part of the MPEG video decoder of this embodiment having a special reproduction function (high-speed reproduction function, low-speed reproduction function, frame-by-frame reproduction function). The MPEG video decoder 11 of the present embodiment includes, in addition to the circuits 2 to 7 of the MPEG video decoder 1 of the first embodiment, a picture header detection / data amount analysis circuit (hereinafter abbreviated as an analysis circuit) 12, a register 13, 14. Each of the circuits 3 to 7 and 12 to 14 is one chip of L
It is mounted on SI.

The control core circuit 7 comprises the circuits 2 to 6, 12 to 1
4 is controlled. The video stream read from a recording medium such as a video CD is transferred to the bit buffer 2 via the analysis circuit 12. The analysis circuit 12 has the following two functions. A picture header at the head of each picture of the video stream read from the recording medium is detected, and the type (I, P, B) of the picture specified in each picture header is detected. The data amount of each detected picture is analyzed.

Each of the registers 13 and 14 has a FIFO structure of R
AM. The register 13 sequentially accumulates the type of each picture detected by the analysis circuit 12. That is, the GOP configuration of the video stream stored in the bit buffer 2 is recorded in the register 13. Register 14
Sequentially stores the data amount of each picture analyzed by the analysis circuit 12.

The decision circuit 5 has the following two functions. As in the second embodiment, the bit buffer 2
Is compared with each of the thresholds B2thn and B3thn to determine in which region the occupancy Bm is included in the equations (10) to (12). A picture to be skipped is selected based on the GOP structure recorded in the register 13, the data amount of each picture recorded in the register 14, and the above-described determination result.

In the first and second embodiments, the GOP structure of the video stream and the data amount of each picture cannot be known until the decoding in the decoding core circuit 4 is completed. However, in the present embodiment, by providing the analysis circuit 12, the GOP configuration and the data amount of each picture can be analyzed before the video stream is input to the bit buffer 2. That is,
The determination as to whether or not the bit buffer 2 may overflow can be made before the video stream is input to the bit buffer 2. Therefore, the picture to be skipped can be optimally selected according to the GOP structure of the video stream and the data amount of each picture. As a result, useless skipping of B pictures can be minimized.

As described in detail above, according to the present embodiment,
The following effects can be obtained in addition to the effects of the second embodiment. The number of B pictures that can be decoded after the overflow of the bit buffer 2 is avoided increases. Therefore, it is possible to further improve the image quality by smoothing the motion of the moving image during the high-speed reproduction.

Since the number of pictures stored in the bit buffer 2 and the data amount of each picture can be ascertained, the occupancy Bm of the bit buffer 2 can be accurately known. In addition, the degree of decrease in the occupation amount Bm of the bit buffer 2 after an arbitrary picture is read can be accurately known. In general, at the time of low-speed reproduction or frame-by-frame reproduction, the bit rate of a video stream read from a recording medium is the same as during normal reproduction. That is, at the time of low-speed reproduction or frame-by-frame reproduction, the number of pictures read from the bit buffer 2 per unit time is reduced, thereby reducing the number of frames of the moving image reproduced on the display 8. However, as mentioned above,
In the conventional MPEG video decoder 101, the occupation amount Bm of the bit buffer 2 after an arbitrary picture is read out
I did not know the degree of decrease. Therefore, every time a picture is read from the bit buffer 2, a video stream is read from the recording medium and transferred to the bit buffer 2 in order to avoid overflow or underflow. Therefore, the operation of reading the video stream from the recording medium has to be frequently repeated. For example, when a video CD is used as a recording medium, a video C
If the video stream is frequently read from D, the control of the driving device of the optical pickup of the video CD player becomes complicated, and the mechanical load on the driving device is increased, so that the device is easily broken.

In the present embodiment, the degree of reduction in the capacity of the bit buffer 2 after an arbitrary picture has been read can be accurately known, and therefore, only when the possibility of overflow or underflow increases. The video stream may be read from the recording medium. Therefore, according to the present embodiment, the operation of reading a video stream from a recording medium during low-speed reproduction or frame-by-frame reproduction can be reduced. Therefore, when a video CD is used as the recording medium, the control of the drive device of the optical pickup of the video CD player is simplified, and the mechanical load on the drive device is reduced to reduce the number of failures.

(Fourth Embodiment) Next, a fourth embodiment of the present invention will be described with reference to FIG. In the present embodiment, the same components as those in the third embodiment have the same reference numerals, and a detailed description thereof will be omitted. FIG. 5 shows a main block circuit of the MPEG video decoder according to the present embodiment having a special reproduction function. The MPEG video decoder 21 of this embodiment includes a frame buffer 22 in addition to the circuits 2 to 7 and 12 to 14 of the MPEG video decoder 11 of the third embodiment.

The control core circuit 7 includes the circuits 2 to 6, 12 to 1
4, 22 are controlled. The decoding result (video output) of each picture generated by the decoding core circuit 4 is transferred to each area 22a to 22c of the frame buffer 22. The decoding result of each picture read from each area 22 a to 22 c of the frame buffer 22 is transferred to the decoding core circuit 4.

The frame buffer 22 comprises a RAM,
The inside is divided into three areas (a forward reference area 22a, a backward reference area 22b, and a B picture storage area 22c). In the forward reference area 22a, a decoding result (video output) of a future I picture or P picture used when performing backward prediction in the decoding core circuit 4 is stored. The decoding result of the past I picture or P picture used when performing forward prediction in the decode core circuit 4 is stored in the backward reference area 22b.
The decoding result of the B picture is stored in the B picture storage area 22c. Then, the video output stored in any one of the areas 22a to 22c is output to the display 8.

Frame buffer 22 and bit buffer 2
Is an MPEG video decoder 1 with a reduced number of parts.
In order to reduce the cost of one, the area is provided separately in one RAM. By the way, the forward reference area 22a
Since the I picture or the P picture stored in the backward reference area 22b is used as the base data for performing the forward prediction or the backward prediction, the I picture or the P picture must be continuously stored in each area 22a, 22b until it becomes unnecessary. No. The B picture is not treated as the base data, and is unnecessary when output to the display 8.
Each of the regions 22a to 22c is called a plane.

When the MPEG video decoder and the MPEG audio decoder are mounted on one LSI, the bit buffer (audio bit buffer) for the MPEG audio decoder also includes the frame buffer 22 and the bit buffer for the MPEG video decoder. (Video bit buffer) 2 and an area are provided separately in one RAM. For example, when a video CD is used as a recording medium, a 4 MDRAM is used, the capacity of the video bit buffer 2 is 52 kbytes, and the capacity of each of the areas 22 a to 22 c of the frame buffer 22 is 14
The capacity of the audio bit buffer is set to 6.5 kbytes, and the capacity of the user area is set to 8 kbytes. By the way, the user area is a video CDv
It is used for 2.0 standard sector buffers.

At the time of high-speed reproduction at 4 × speed or higher, a moving image with sufficiently smooth motion can be obtained only by decoding I and P pictures, so that all B pictures can be skipped. In addition, at the time of high-speed reproduction of 8 × speed or higher, a moving image with sufficiently smooth motion can be obtained only by decoding an I-picture, so that all P-pictures and B-pictures can be skipped.

As described above, at the time of high-speed reproduction of 4 × speed or higher, the B picture storage area 22 of the frame buffer 22 is
c becomes unnecessary. Therefore, in the present embodiment, the B picture storage area 22c of the frame buffer 22, which is no longer needed, is used as the bit buffer 2 at the time of high-speed reproduction equal to or higher than quadruple speed reproduction. That is, the B picture storage area 22c of the frame buffer 22 is used as an additional memory of the bit buffer 2. As a result, in the case of the above-described 4MDRAM, the capacity of the bit buffer 2 is increased to about 200 kbytes (= original capacity of the bit buffer 2 52 k + capacity of the B picture storage area 22 c of 148.5 k), which is about four times the conventional capacity. it can.

As described in detail above, according to the present embodiment,
The following effects can be obtained in addition to the effects of the third embodiment. The overflow of the bit buffer 2 can be reliably avoided even at the time of high-speed reproduction of 4 × speed or more. When the effect of the present embodiment at the time of high-speed reproduction was simulated when the capacity of the bit buffer 2 was set to about 200 kbytes, it was confirmed that a moving image with a smooth motion could be obtained up to about 30 times speed reproduction.

(Fifth Embodiment) Next, a fifth embodiment of the present invention will be described with reference to FIGS. The configuration of the MPEG video decoder of the present embodiment is the same as that of the fourth embodiment. The decoding core circuit 4 converts two I-pictures or P-pictures into MPEG
It has the ability to decode in accordance with the video part and generate a video output for each picture. Then, when two I pictures or two P pictures are decoded within one frame period, the decode core circuit 4
The video output of the picture or the P picture is not output to the display 8, but only the video output of the I picture or the P picture decoded later is output to the display 8. That is, the I picture or P
Only pictures are treated as playback pictures. Then, the video output of the I picture or the P picture decoded earlier is treated as intermediate data used when performing forward prediction.

As described above, the B picture storage area 22c of the frame buffer 22 is not required at the time of high-speed reproduction of four times or more. Therefore, in the present embodiment, at the time of high-speed reproduction equal to or higher than quadruple-speed reproduction, the video output of the previously decoded I picture or P picture is stored in the unnecessary B picture storage area 22c of the frame buffer 22. Therefore, the previously decoded I picture or P picture
There is no need to provide a separate frame buffer for storing the video output of the picture.

Next, the operation of this embodiment will be described with reference to FIGS.
It will be described according to. When a video stream having a GOP structure as shown in FIG. 6A is read from a recording medium,
The pictures processed in each frame period (pictures decoded by the decode core circuit 4, pictures reproduced on the display 8, and pictures skipped via the picture skip circuit 6) are as shown in FIG. 6B.

FIG. 7 shows a change in the occupation amount Bm of the bit buffer 2 in the case shown in FIG. First, the P picture P1 is decoded. Here, if the occupation amount Bm still exceeds the threshold value B3thn even after the P picture P1 is read from the bit buffer 2, the two subsequently read B pictures B2 and B3 are skipped without decoding. I do. If the occupation amount Bm still exceeds the threshold value B3thn, the P picture P4 is decoded. At this time, the previously decoded P picture P1 is not reproduced because it is used as intermediate data when the decoding core circuit 4 performs forward prediction to generate the P picture P4. Then, only the P picture P4 is reproduced. These processes are performed within one frame period.

In the next one frame period, B picture B5
Is decoded and played. On the other hand, in the second embodiment (the dotted line in the figure), first, the P picture P1 is decoded and reproduced, and then the B pictures B2 and B3 are skipped without decoding. These processes are performed within one frame period. Therefore, at this point, the P picture P4 remains stored in the bit buffer 2. Therefore, the possibility that the bit buffer 2 overflows during the decoding of the P picture P4 during the next one frame period is extremely high.

As described in detail above, according to the present embodiment,
The following effects can be obtained in addition to the effects of the fourth embodiment. At the time of high-speed playback of 4 × speed or higher, a P which can be decoded while avoiding overflow of the bit buffer 2
More pictures. As a result, the number of B pictures that can be decoded increases. Therefore, it is possible to further improve the image quality by smoothing the motion of the moving image during the high-speed reproduction.

As in the second embodiment, in this embodiment, even if the threshold value B3thn is set to the same value as the threshold value Bthn,
The same effects as above can be obtained. The above embodiments may be modified as follows, and the same operation and effect can be obtained in such a case. [1] In each of the above embodiments, high-speed reproduction based on a D picture is performed together. In this case, the effects of the above embodiments can be further enhanced.

[2] The coefficient n in the above equation (8) is set to a value larger than the magnification n for the normal reproduction speed. For example, 2
In the double speed reproduction, the coefficient n in the equation (8) is set to a value larger than 2 (n> 2). In this case, the same effects as in the above embodiments can be obtained, but if the coefficient n is too large, the number of dropped frames that occur in the reproduced moving image increases. In other words, although it is best to make the coefficient n and the magnification n equal,
If it is a little, the value of the coefficient n may be adjusted.

[3] In the fourth embodiment, the frame buffer 22 is provided separately from the bit buffer 2. [4] In the fifth embodiment, a frame buffer for storing a video output of an I picture or a P picture decoded earlier is provided separately from the frame buffer 22.

[5] The first embodiment and the second embodiment are used together. [6] Not only video CD players but also VTRs (Video
The present invention is applied to a playback device of a storage medium using the MPEG system, such as a Tape Recorder) and a DVD (Digital Video Disk) player. [7] The first to fifth embodiments are replaced with software processing using a CPU. That is, each circuit (3 to 7, 1
The signal processing in 2) is replaced with software-based signal processing using a CPU.

Although the embodiments have been described above, technical ideas other than the claims that can be grasped from the embodiments will be described below together with their effects. (A) The MPEG video decoder according to any one of claims 1 to 4, wherein a decode core circuit and a judgment control circuit are formed on one chip.

[0106] If, as this, it is possible to miniaturize the entire MPEG video decoder.

Incidentally, in the present specification, the members according to the constitution of the present invention are defined as follows. (A) The determination control circuit includes a variable threshold overflow determination circuit 5, a picture skip circuit 6, and a control core circuit 7. (B) The video stream analysis circuit includes a picture header detection / data amount analysis circuit 12.

(C) The recording medium includes not only a video CD but also any digital recording medium such as a DVD, a CD-ROM, a hard disk, and a video tape.

[0109]

1) It is possible to provide an MPEG video decoder capable of avoiding overflow of a bit buffer. 2) It is possible to provide an MPEG video decoder capable of improving the image quality by smoothing the motion of a moving image during special reproduction and avoiding overflow of a bit buffer.

[Brief description of the drawings]

FIG. 1 is a main part block circuit diagram of a first and a second embodiment.

FIG. 2 is a graph for explaining the first embodiment.

FIG. 3 is a graph for explaining a second embodiment.

FIG. 4 is a main part block circuit diagram of a third embodiment.

FIG. 5 is a main part block circuit diagram of the fourth and fifth embodiments.

FIG. 6 is a schematic diagram for explaining a fifth embodiment.

FIG. 7 is a graph for explaining a fifth embodiment.

FIG. 8 is a main part block circuit diagram of a conventional example.

FIG. 9 is a graph for explaining a conventional example.

[Explanation of symbols]

 1,11,21 ... MPEG video decoder 2 ... Bit buffer 3 ... Picture header detection circuit 4 ... MPEG video decoding core circuit 5 ... Variable threshold overflow determination circuit 6 ... Picture skip circuit 6a, 6b ... Node 7 ... Control core circuit 8 ... Display 12: Picture header detection / data amount analysis circuit 22: Frame buffer 22a: Forward reference area 22b: Back reference area 22c: B picture storage area

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-7-135659 (JP, A) JP-A-6-292187 (JP, A) JP-A-6-261303 (JP, A) JP-A-6-261303 253277 (JP, A) JP-A-4-326281 (JP, A) JP-A-3-65875 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N ^7/ 24-7 / 68 H04N 5/91-5/956

Claims (7)

(57) [Claims] 1. A bit buffer, and each picture read from the bit buffer is stored in an MP.
A decoding core circuit for decoding in accordance with the EG video part, and a threshold value for the occupancy of the bit buffer,
When the occupancy exceeds the threshold, a determination control circuit that skips the picture supplied from the bit buffer to the decode core circuit without transferring the picture to the decode core circuit until the occupancy falls below the threshold, The MPEG video decoder , wherein the determination control circuit variably sets the threshold based on a reproduction speed of a moving image . 2. A bit buffer for storing a video stream, and each picture read from the bit buffer is stored in an MP.
A decoding core circuit for decoding in accordance with the EG video part; and a threshold value for the occupancy of the bit buffer is set based on the playback speed of the moving image. An MPEG video decoder comprising: a determination control circuit for skipping a picture supplied from the bit buffer to the decode core circuit without transferring the picture to the decode core circuit until the number falls below the threshold. 3. A bit buffer for accumulating a video stream, and each picture read from the bit buffer is stored in an MP.
A decoding core circuit for decoding in accordance with the EG video part; and a threshold value for the occupancy of the bit buffer is set based on the playback speed of the moving image. A determination control circuit for skipping a picture supplied from the bit buffer to the decode core circuit until the number of bits falls, without transferring the picture to the decode core circuit, skipping only a B picture, and not skipping a P picture and an I picture. An MPEG video decoder, comprising: 4. The M according to claim 1, wherein
In the PEG video decoder, the determination control circuit includes:
An MPEG video decoder characterized in that even if the occupancy of the bit buffer falls below a threshold value after reading an I picture or a P picture, if the next picture to be read from the bit buffer is a B picture, the MPEG video decoder skips. 5. The M according to claim 1, wherein
In the PEG video decoder, the decode core circuit decodes two P pictures within one frame period in order to reduce the amount of data occupied in the bit buffer. An MPEG video decoder characterized in that only a P picture decoded later is treated as a reproduced picture, and only a P picture decoded later is treated as a reproduced picture without treating it as intermediate data for performing forward prediction of the picture. 6. The M according to claim 1, wherein:
The PEG video decoder includes a frame buffer for storing a decoding result of each picture generated by the decoding core circuit, and the inside of the frame buffer is divided into three areas: a forward reference area, a backward reference area, and a B picture storage area. The decoding core circuit decodes two P-pictures within one frame period, and plays back only the previously decoded P-picture only by treating it as intermediate data for performing forward prediction of the subsequently decoded P-picture. An MPEG video decoder characterized in that the intermediate data is stored in a B picture storage area, and only P pictures decoded later are treated as reproduced pictures. 7. The M according to claim 1, wherein
In the PEG video decoder, the threshold value is a buffer size (Vbv Buffer Size) defined by a sequence header at the beginning of a video stream sequence.
And Bit Rate and Picture Rate (Pictur
e Rate) and a magnification (n) of the actual reproduction speed with respect to the normal reproduction speed.
EG video decoder.