KR100370143B1 - Method for forming contact plug of Semiconductor device - Google Patents
Method for forming contact plug of Semiconductor device Download PDFInfo
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- KR100370143B1 KR100370143B1 KR10-2000-0046342A KR20000046342A KR100370143B1 KR 100370143 B1 KR100370143 B1 KR 100370143B1 KR 20000046342 A KR20000046342 A KR 20000046342A KR 100370143 B1 KR100370143 B1 KR 100370143B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
Abstract
본 발명은 하부 금속배선과 상부 금속배선간을 연결하는 콘택(contact) 또는 비아(via)에서의 계면접촉저항을 낮추기 위한 반도체 소자의 콘택 플러그 형성 방법에 관한 것으로, 반도체 기판상에 콘택홀을 갖는 층간절연막을 형성하는 제 1 단계; 상기 콘택홀 내부 및 층간절연막상에 반응물을 흡착시키는 제 2 단계; 상기 흡착된 반응물을 플라즈마 처리를 통하여 환원시켜 금속막을 형성하는 제 3 단계: 그리고 상기 금속막이 형성된 콘택홀 내부에 플러그를 형성하는 제 4 단계를 포함하여 형성하는 것을 특징으로 한다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a contact plug of a semiconductor device for reducing interfacial contact resistance in a contact or via connecting a lower metal wiring to an upper metal wiring. A first step of forming an interlayer insulating film; A second step of adsorbing a reactant on the contact hole and on the interlayer insulating film; And a fourth step of forming the metal film by reducing the adsorbed reactant through plasma treatment, and forming a plug in the contact hole in which the metal film is formed.
Description
본 발명은 반도체 소자에 관한 것으로, 특히 하부 금속배선과 상부 금속배선간을 연결하는 콘택(contact) 또는 비아(via)에서의 계면접촉저항을 낮추기 위한 반도체 소자의 콘택 플러그 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a method of forming a contact plug of a semiconductor device for reducing interfacial contact resistance in a contact or via connecting a lower metal wiring to an upper metal wiring.
이하, 종래의 반도체 소자의 콘택 플러그 형성 공정에 관하여 설명하면 다음과 같다.Hereinafter, a process of forming a contact plug of a conventional semiconductor device will be described.
일반적으로 하부 금속배선(또는 반도체기판)상에 층간절연막을 형성하고, 상기 하부 금속배선이 드러나도록 콘택홀을 형성한 후 콘택홀 내부에 텅스텐을 형성하여 텅스텐 플러그를 형성한다.In general, an interlayer insulating layer is formed on a lower metal wiring (or semiconductor substrate), a contact hole is formed to expose the lower metal wiring, and tungsten is formed inside the contact hole to form a tungsten plug.
이 때, 하부 금속배선과의 접촉저항을 낮추기 위해서 텅스텐을 형성하기 전에 베리어금속막을 형성하는데 이를 글루 레이어(glue layer) 공정이라고 한다.At this time, in order to lower the contact resistance with the lower metal wiring, a barrier metal film is formed before tungsten is formed, which is called a glue layer process.
하부 금속배선과의 접촉저항을 낮추기 위해 형성하는 베리어 금속막은 보통 물리적 스퍼터(physical sputter) 방식의 RF 식각 및 물리적 기상 증착(Physical Vapor Deposition) 방식의 티타늄(Ti) 또는 IMP(Ionized Metal Plasma) 티타늄을 사용한다.The barrier metal film formed to lower the contact resistance with the lower metal wiring is usually made of physical sputter (RF) etching and physical vapor deposition (Ti) or IMP (Ionized Metal Plasma) titanium. use.
그리고, 콘택홀의 기저부의 불순물을 효과적으로 제거하고 하부 금속배선과의 오믹 콘택(ohmic contact)을 이루기 위해 상기의 물리적 스퍼터 방식으로 티타늄막을 두껍게 형성한다.The titanium film is thickly formed by the above physical sputtering method to effectively remove impurities in the bottom portion of the contact hole and make ohmic contact with the lower metal wiring.
이 때 콘택홀의 상부(hole top) 모서리 지역에서 티타늄막의 두께가 증가하게 되어 오버행잉(overhanging)에 의한 네거티브 슬로프(negative slop)가 형성되고, 이로 인해 텅스텐 증착 공정중에서 플러그 내에 보이드(void)가 발생될 수 있다.At this time, the thickness of the titanium film is increased in the hole top edge region of the contact hole, so that a negative slop due to overhanging is formed, which causes voids in the plug during the tungsten deposition process. Can be.
또한, 콘택홀 상부 지역의 티타늄 박막이 500Å의 두께로 두껍게 형성되면 텅스텐을 CMP공정으로 평탄화시켜 플러그를 형성할 때 단위 시간동안 식각비(removal rate)가 가장 낮은 티타늄막이 차지하는 비율이 높아져 이로 인해 전체적인 생산성을 떨어뜨리는 문제가 있다.In addition, when the titanium thin film in the upper region of the contact hole is formed to a thickness of 500 kW, the titanium film having the lowest etching rate for the unit time is increased during the unit time when the tungsten is flattened by the CMP process to form a plug. There is a problem that decreases productivity.
그리고, 스퍼터법에 의한 콘택홀 기저부의 두께 확보를 위해 개발된 IMP 티타늄의 경우는 추가적인 플라즈마 발생 장치등이 고가이고, 금속 이온(metal ion)에 의한 콘택홀 기저부의 손상등이 발생할 수 있다.In addition, in the case of IMP titanium developed to secure the thickness of the contact hole base portion by the sputtering method, an additional plasma generator is expensive, and damage to the contact hole base portion due to metal ions may occur.
그래서 현재는 화학적 기상 증착(Chemical Vapor Deposition : CVD)법으로 티타늄을 증착하는 방법이 활발히 연구되고 있다.Therefore, a method of depositing titanium by chemical vapor deposition (CVD) has been actively studied.
그러나 상기와 같은 종래의 반도체 소자의 금속 배선 형성 방법은 다음과 같은 문제점이 있다.However, the metal wiring formation method of the conventional semiconductor device as described above has the following problems.
첫째, CVD법에 의한 티타늄 증착은 반응물(반응기체와 환원기체)을 동시에 넣을 때 생기는 기체 상태 반응(gas phase reaction : heterogeneous reaction)등에 의해 우수한 콘포머러티(conformality)를 확보하기 힘들어 콘택홀 상부 부분의 증착두께가 두꺼워지는 문제가 발생한다.First, titanium deposition by CVD method is difficult to secure excellent conformality due to gas phase reaction (heterogeneous reaction) that occurs when reactants (reaction gas and reducing gas) are added at the same time. A problem arises in that the deposition thickness of the film becomes thick.
둘째, 콘택홀 내부에 기체 상태 반응에 의해서 충분히 반응되지 않고 존재하는 불순물을 제거하기 위해서는 500℃이상의 기판 온도가 요구되기 때문에 배선공정에서 알루미늄 합금을 사용하는 텅스텐 플러그 형성공정에서 이 방법을 사용하는데 한계가 있다.Second, it is limited to use this method in the tungsten plug forming process using aluminum alloy in the wiring process because substrate temperature of 500 ℃ or higher is required to remove impurities that are not sufficiently reacted by gas phase reaction inside the contact hole. There is.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 하부 금속배선과 상부 금속배선간을 연결하는 콘택(contact) 또는 비아(via)에서의 계면접촉저항을 낮추기 위해 반응기체의 흡착 및 플라즈마 처리를 통해 환원시켜 베리어금속막을 형성하고, 그 두께를 감소시킬 수 있는 반도체 소자의 콘택 플러그 형성 방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems and the adsorption and plasma treatment of the reactor to reduce the interfacial contact resistance in the contact (via) or the via (connecting) connecting the lower metal wiring and the upper metal wiring It is an object of the present invention to provide a method for forming a contact plug of a semiconductor device capable of reducing the thickness of the barrier metal film and reducing its thickness.
도 1a 내지 1c는 본 발명에 의한 반도체 소자의 콘택 플러그 형성 방법을 나타낸 공정 단면도1A to 1C are cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호 설명Explanation of symbols for the main parts of drawings
1 : 하부 금속배선 2 : 반사방지막1: lower metal wiring 2: antireflection film
3 : 층간절연막 4 : 콘택홀3: interlayer insulating film 4: contact hole
5 : TiCl45a : 티타늄막5: TiCl 4 5a: titanium film
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 콘택 플러그 형성 방법은 반도체 기판상에 콘택홀을 갖는 층간절연막을 형성하는 제 1 단계; 상기 콘택홀 내부 및 층간절연막상에 반응물을 흡착시키는 제 2 단계; 상기 흡착된 반응물을 플라즈마 처리를 통하여 환원시켜 금속막을 형성하는 제 3 단계: 그리고 상기 금속막이 형성된 콘택홀 내부에 플러그를 형성하는 제 4 단계를 포함하여 형성하는 것을 특징으로 한다.A method of forming a contact plug of a semiconductor device according to the present invention for achieving the above object includes a first step of forming an interlayer insulating film having a contact hole on a semiconductor substrate; A second step of adsorbing a reactant on the contact hole and on the interlayer insulating film; And a fourth step of forming the metal film by reducing the adsorbed reactant through plasma treatment, and forming a plug in the contact hole in which the metal film is formed.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 콘택 플러그 형성 방법을 상세히 설명하면 다음과 같다.Hereinafter, a method of forming a contact plug of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 1a 내지 1c는 본 발명에 의한 반도체 소자의 콘택 플러그 형성 방법을 나타낸 공정단면도이다.1A to 1C are process cross-sectional views illustrating a method for forming a contact plug of a semiconductor device according to the present invention.
본 발명의 콘택 플러그 형성 방법은 먼저 도 1a에 도시한 바와 같이, 반도체 기판 또는 하부금속배선(알루미늄)(1)상에 반사방지막(2)을 형성한 후, 상기 반사방지막(2)상에 층간절연막(Inter-Layer Dielectric, or Inter-Metal Dielectric)(3)을 형성한다.In the method for forming a contact plug of the present invention, as shown in FIG. 1A, an antireflection film 2 is formed on a semiconductor substrate or a lower metal wiring (aluminum) 1, and then an interlayer is formed on the antireflection film 2. An insulating film (Inter-Layer Dielectric, or Inter-Metal Dielectric) 3 is formed.
여기서, 층간절연막(3)은 소자를 구동하기 위한 트랜지스터의 캐패시터나 금속 배선간을 절연시키거나, 다층 금속배선에서 상, 하부 금속배선의 절연을 위해 형성한다.Here, the interlayer insulating film 3 is formed to insulate between the capacitor and the metal wiring of the transistor for driving the device, or to insulate the upper and lower metal wiring in the multilayer metal wiring.
이어, 층간절연막(3)상에 감광막을 도포한 후 일정 영역이 드러나도록 노광및 현상공정을 통해 감광막을 선택적으로 패터닝한 후 패터닝된 감광막을 마스크로 층간절연막(3) 및 반사방지막(2)을 이방성식각하여 일정 영역의 하부금속배선(또는 반도체기판)(1)상에 콘택홀(4)을 형성한다.Subsequently, after the photoresist is applied onto the interlayer insulating film 3, the photoresist is selectively patterned through an exposure and development process so that a predetermined area is exposed, and then the interlayer insulating film 3 and the antireflection film 2 are formed using the patterned photoresist as a mask. Anisotropic etching is performed to form the contact hole 4 on the lower metal wiring (or semiconductor substrate) 1 in a predetermined region.
이 때, 콘택홀(4)은 트랜지스터의 소오스/드레인 영역이나, 다층금속배선에서 하부금속배선상에 형성할 수 있다.In this case, the contact hole 4 may be formed on the source / drain regions of the transistor or on the lower metal wiring in the multilayer metal wiring.
그리고, 콘택홀(4)의 기저부의 불순물들을 제거하기 위하여 세정(pre-cleaning)공정인 RF 식각(etch) 공정을 진행한다.In order to remove impurities at the bottom of the contact hole 4, an RF etch process, which is a pre-cleaning process, is performed.
하지만 상기 불순물들은 이후에 진행할 환원성 플라즈마 처리에서 충분히 제거될 수 있어 상기 세정공정을 생략할 수 있다.However, the impurities may be sufficiently removed in a subsequent reducing plasma treatment, and thus the cleaning process may be omitted.
도 1b에 도시한 바와 같이, Ti를 함유하고 있는 반응기체, 예를 들어 TiCl4(5)를 콘택홀(4) 내부 및 층간절연막(3)상에 흡착시킨다.As shown in Fig. 1B, a reactive gas containing Ti, for example TiCl 4 (5), is adsorbed on the inside of the contact hole 4 and on the interlayer insulating film 3.
이 때, 0.1mtorr∼100torr의 압력에서 TiCl4(5)를 10Å∼300Å의 두께로 흡착시킨다.At this time, TiCl 4 (5) is adsorbed to a thickness of 10 kPa to 300 kPa at a pressure of 0.1 mtorr to 100 tor.
이어, 도 1c에 도시한 바와 같이, H2플라즈마와 같은 환원성 분위기의 플라즈마를 이용하여 상기 TiCl4(5)를 환원시켜 콘택홀(4) 내부 및 층간절연막(3)상에 티타늄막(5a)을 형성한다.Next, as shown in FIG. 1C, the TiCl 4 (5) is reduced by using a plasma having a reducing atmosphere such as H 2 plasma to form the titanium film 5a on the inside of the contact hole 4 and the interlayer insulating film 3. To form.
상기 플라즈마 처리시에 공정 압력은 0.1mtorr∼10torr이고, 이 때의 기판온도는 100℃∼600℃이다.During the plasma treatment, the process pressure is 0.1 mtorr to 10 torr, and the substrate temperature at this time is 100 ° C to 600 ° C.
이 때, H2플라즈마에 의해 TiCl4(5) 물질이 환원되면서 부산물로 HCl이 발생하고, 상기 HCl로 인해 콘택홀(4) 기저부에 있는 금속 계통의 불순물등이 제거된다.At this time, HCl is generated as a by-product while the TiCl 4 (5) material is reduced by the H 2 plasma, and the HCl removes impurities such as metals at the base of the contact hole 4.
그리고 콘택홀(4)의 기저부에 요구되는 금속막의 두께 및 플라즈마 처리에서 환원되어 형성되는 흡착층(티타늄막)의 두께에 따라 도 1b 및 1c에 도시된 과정 즉, TiCl4(5) 기체를 흡착한 후 H2플라즈마에 의해 환원시켜 티타늄막(5a)을 형성하는 과정을 반복할 수 있다.The process shown in FIGS. 1B and 1C, that is, the TiCl 4 (5) gas is adsorbed according to the thickness of the metal film required at the base of the contact hole 4 and the thickness of the adsorption layer (titanium film) formed by reduction in plasma treatment. After that, the process of reducing the titanium film 5a by reducing the H 2 plasma may be repeated.
여기서, Ti를 함유하고 있는 반응기체 대신에, Ta를 함유하고 있는 반응기체인 TaCl5를 이용해도 된다.Here, TaCl 5 which is a reactant containing Ta may be used instead of the reactant containing Ti.
이후에 도면에는 도시되지 않았지만, 티타늄막(5a)상에 CVD법으로 티타늄 나이트라이드(TiN)막을 형성하고, 전면에 텅스텐을 형성한 후 평탄화시켜 콘택홀(4) 내부에 텅스텐 플러그를 형성한다.Although not shown in the drawings, a titanium nitride (TiN) film is formed on the titanium film 5a by CVD, tungsten is formed on the entire surface, and flattened to form a tungsten plug in the contact hole 4.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 콘택 플러그 형성 방법에 있어서 다음과 같은 효과가 있다.As described above, the method of forming a contact plug of a semiconductor device according to the present invention has the following effects.
첫째, 접촉 저항 감소를 위한 티타늄막의 두께를 감소시킬 수 있어 증착공정에서의 생산성을 증대시킬 수 있을 뿐만 아니라, 텅스텐 플러그 형성 공정에서 야기되는 텅스텐 플러그 내의 보이드(void) 형성을 억제할 수 있다.First, it is possible to reduce the thickness of the titanium film for reducing contact resistance, thereby increasing productivity in the deposition process, and suppressing void formation in the tungsten plug caused by the tungsten plug forming process.
둘째, 단위 시간당 식각비(removal rate)가 가장 낮은 티타늄막의 두께를 감소시킴으로서 CMP 공정의 생산성을 향상시킬 수 있다.Second, the productivity of the CMP process can be improved by reducing the thickness of the titanium film having the lowest etching rate per unit time.
셋째, 티타늄막을 형성할 때 고가장비인 CVD 장비 및 IMP 스퍼터 장비를 사용하지 않고, CVD 티타늄 나이트라이드를 형성하는 장비의 가스라인(gas line)만을 개조하여 사용할 수 있어, 티타늄막과 티타늄나이트라이드막을 형성하는 공정을 같은 곳(insitu)에서 진행할 수 있어 불순물이 개제되는 것을 방지할 수 있다.Third, it is possible to use only the gas line of the equipment for forming CVD titanium nitride without using expensive CVD equipment and IMP sputter equipment when forming the titanium film, so that the titanium film and titanium nitride film can be used. The forming process can be carried out in the same place (insitu) to prevent the impurities from being deposited.
따라서 콘택 접촉저항 감소를 기대할 수 있다.Therefore, the contact contact resistance can be expected to decrease.
넷째, 흡착물(TiCl4,TaCl5) 환원시 형성되는 부산물인 HCl을 이용하여 콘택홀 기저부에 존재하는 불순물들을 제거할 수 있어 RF 식각에 의한 세정공정을 생략할 수 있어 공정 단순화의 효과가 있다.Fourth, impurities present in the bottom of the contact hole can be removed by using HCl, a by-product formed during the reduction of the adsorbate (TiCl 4 , TaCl 5 ), which can simplify the cleaning process by RF etching. .
Claims (10)
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| CN101630656B (en) * | 2008-07-15 | 2012-01-25 | 中芯国际集成电路制造(上海)有限公司 | Methods for forming contact hole and dual damascene structure |
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| JPH0290519A (en) * | 1988-09-28 | 1990-03-30 | Hitachi Ltd | Method of filling fine hole with metal |
| JPH06204191A (en) * | 1992-11-10 | 1994-07-22 | Sony Corp | Surface processing method after formation of metallic plug |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0290519A (en) * | 1988-09-28 | 1990-03-30 | Hitachi Ltd | Method of filling fine hole with metal |
| JPH06204191A (en) * | 1992-11-10 | 1994-07-22 | Sony Corp | Surface processing method after formation of metallic plug |
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