KR100370125B1 - Method for forming interconnection line in semiconductor device - Google Patents
Method for forming interconnection line in semiconductor device Download PDFInfo
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- KR100370125B1 KR100370125B1 KR10-1999-0059454A KR19990059454A KR100370125B1 KR 100370125 B1 KR100370125 B1 KR 100370125B1 KR 19990059454 A KR19990059454 A KR 19990059454A KR 100370125 B1 KR100370125 B1 KR 100370125B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/02134—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material comprising hydrogen silsesquioxane, e.g. HSQ
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
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- Condensed Matter Physics & Semiconductors (AREA)
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- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
본 발명은 저유전율의 절연막의 표면밀도를 강화하고, 배선간의 저유전율이 차지하는 비율을 극대화하여 배선간의 커패시턴스를 감소시키며, 절연특성을 개선시킬 수 있는 반도체 소자의 배선형성방법에 관한 것으로, 본 발명 반도체 소자의 배선형성방법은 절연기판 또는 하부절연층상에 저유전율의 제 1 절연층을 형성하는 공정과, 상기 제 1 절연층을 선택적으로 제거하여 하부 배선이 형성될 영역을 정의하는 공정과, 상기 제 1 절연층을의 표면을 질화층으로 변화시키는 공정과, 상기 제 1 절연층이 제거된 부분에 하부배선을 형성하는 공정과, 상기 표면이 질화층으로 변화된 제 1 절연층 및 상기 하부배선상에 제 2 절연층을 형성하는 공정과, 상기 하부배선이 노출되도록 상기 제 2 절연층에 비아 홀을 형성하는 공정과, 상기 비아 홀을 통해 상기 하부배선과 연결되는 상부배선을 형성하는 공정을 포함하여 이루어진다.The present invention relates to a method for forming a wiring of a semiconductor device capable of enhancing the surface density of an insulating film having a low dielectric constant, maximizing the ratio of the low dielectric constant between wirings, reducing capacitance between wirings, and improving insulation characteristics. A method of forming a wiring of a semiconductor device may include forming a first dielectric layer having a low dielectric constant on an insulating substrate or a bottom dielectric layer, selectively removing the first dielectric layer, and defining a region where a bottom wiring is to be formed; Changing the surface of the first insulating layer into a nitride layer, forming a lower wiring in a portion where the first insulating layer is removed, and forming a first insulating layer and the lower wiring on which the surface is changed into a nitride layer Forming a second insulating layer in the second insulating layer; forming a via hole in the second insulating layer to expose the lower wiring; and through the via hole It comprises the step of forming an upper wiring connected to the interconnection portion.
Description
본 발명은 반도체 소자에 관한 것으로 특히, 층간절연막의 신뢰성을 향상시킬 수 있는 반도체 소자의 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor devices, and more particularly, to a method for forming a wiring of a semiconductor device capable of improving the reliability of an interlayer insulating film.
일반적으로 배선형성에 따른 층간절연막으로써, HSQ(HydrogenSilsesquioxane)을 이용한다.Generally, HSQ (Hydrogen Silsesquioxane) is used as an interlayer insulating film due to wiring formation.
HSQ를 포함한 SOG(Spin On Glass) 방식의 배선의 층간절연막 형성은 스핀-코팅(spin-coating)재료와 배선간의 격리를 위한 라이너(liner) 개념의 PECVD절연막을 형성하고, 그 위에 저유전율을 갖는 스핀-코팅 재료를 형성하고, 흡습방지를 위해서 스핀-코팅 재료위에 PECVD절연막을 형성하여 배선의 층간절연막을 형성한다.The interlayer insulating film formation of the SOG (Spin On Glass) wiring including HSQ forms a PECVD insulating film of a liner concept for isolation between the spin-coating material and the wiring, and has a low dielectric constant thereon. A spin-coating material is formed, and a PECVD insulating film is formed on the spin-coating material to prevent moisture absorption to form an interlayer insulating film of wiring.
이하, 첨부된 도면을 참조하여 종래 기술에 따른 반도체 소자의 배선 형성방법을 설명하기로 한다.Hereinafter, a wiring forming method of a semiconductor device according to the prior art will be described with reference to the accompanying drawings.
도 1a 내지 1f는 종래 기술에 따른 반도체 소자의 배선 형성방법을 설명하기 위한 공정단면도이다.1A to 1F are cross-sectional views illustrating a method of forming a wiring of a semiconductor device according to the prior art.
도 1a에 도시한 바와 같이, 하부절연층(11)상에 메탈층을 형성한 후, 패터닝하여 하부 배선(12)을 형성한다.As shown in FIG. 1A, a metal layer is formed on the lower insulating layer 11 and then patterned to form the lower wiring 12.
이후, 도 1b에 도시한 바와 같이, 상기 하부 배선(12)을 포함한 하부절연층(11)상에 제 1 절연층(13)을 형성한다.Subsequently, as illustrated in FIG. 1B, a first insulating layer 13 is formed on the lower insulating layer 11 including the lower wiring 12.
여기서, 상기 제 1 절연층(13)은 통상 PECVD절연막을 사용하는데, 상기 제 1 절연층(13)은 배선과 이후에 형성될 SOG막과의 접촉을 통해 발생할 수 있는 흡습 등에 의한 메탈의 부식을 방지하는 역할을 한다.In this case, the first insulating layer 13 typically uses a PECVD insulating film. The first insulating layer 13 resists corrosion of the metal due to moisture absorption, which may occur through contact between the wiring and the SOG film to be formed later. It serves to prevent.
도 1c에 도시한 바와 같이, 상기 제 1 절연층(13)상에 스핀-코팅 방식으로 유전율이 낮은 제 2 절연층(14)을 형성한다.As shown in FIG. 1C, a second dielectric layer 14 having a low dielectric constant is formed on the first dielectric layer 13 by a spin-coating method.
통상적으로 상기 제 2 절연층(14)의 물질로서는 무기계열, 유기계열을 포함하여 산화막보다 유전율이 낮은 절연물질을 사용한다.Typically, as the material of the second insulating layer 14, an insulating material having a lower dielectric constant than the oxide film, including an inorganic series and an organic series, is used.
이와 같은 유전율이 낮은 절연물질을 사용하는 이유는 배선간의 커패시턴스 감소 효과를 가져와 소자의 동작속도를 개선시킬 수 있기 때문이다.The reason for using such a low dielectric constant insulating material is that it can reduce the capacitance between wirings and improve the operation speed of the device.
이어, 도 1d에 도시한 바와 같이, 상기 제 2 절연층(14)상에 제 3 절연층(15)을 형성한다.Subsequently, as shown in FIG. 1D, a third insulating layer 15 is formed on the second insulating layer 14.
통상적으로 상기 제 2 절연층(14)은 밀도가 산화막(SiO2)보다 낮기 때문에 흡습에 취약하므로 이를 보호하기 위해 캡핑 절연막인 제 3 절연층(15)을 형성한다.Typically, since the second insulating layer 14 has a lower density than the oxide film SiO 2 , the second insulating layer 14 is vulnerable to moisture absorption, so that the third insulating layer 15, which is a capping insulating film, is formed to protect the second insulating layer 14.
이후, 도 1e에 도시한 바와 같이, 상기 제 3 절연층(15)상에 포토레지스트(도시하지 않음)를 도포한 후, 패터닝하여 비아 콘택(Via contact)을 정의한 후, 상기 제 3 절연층(15), 제 2 절연층(14) 및 제 1 절연층(13)을 플라즈마 에칭처리하여 하부 배선(12)의 표면을 노출되는 비아홀(16)을 형성한다.Subsequently, as shown in FIG. 1E, a photoresist (not shown) is coated on the third insulating layer 15, and then patterned to define a via contact, and then the third insulating layer ( 15), the second insulating layer 14 and the first insulating layer 13 are plasma etched to form the via holes 16 exposing the surface of the lower wiring 12.
이어서, 도 1f에 도시한 바와 같이, 상기 비아홀(16)을 통해 상기 하부 배선(12)과 연결되는 상부 배선(17)을 형성하면 종래 기술에 따른 배선 형성공정이 완료된다.Subsequently, as shown in FIG. 1F, when the upper wiring 17 connected to the lower wiring 12 is formed through the via hole 16, the wiring forming process according to the related art is completed.
그러나 상기와 같은 종래 반도체 소자의 배선형성방법은 다음과 같은 문제점이 있었다.However, the wiring forming method of the conventional semiconductor device as described above has the following problems.
첫째, 소자가 집적화됨에 따라 배선과 배선간의 간격이 좁아질 경우, 하부 배선을 포함한 전면에 PECVD절연막이 형성되기 때문에 그 후에 저유전율의절연막을 형성할 수 있는 배선과 배선간에 저유전율이 채워질 공간이 작아져서 배선과 배선간의 커패시턴스 감소 효과가 현저하게 떨어진다.First, when the gap between the wiring becomes smaller as the device is integrated, a PECVD insulating film is formed on the entire surface including the lower wiring, so that there is a space between the wiring and the wiring which can form a low dielectric constant insulating film thereafter. As a result, the effect of reducing the capacitance between the wiring and the wiring is remarkably inferior.
둘째, 비아홀 형성시 홀의 측벽부에 저유전율의 절연막이 노출되기 때문에 플라즈마 에칭시 플라즈마 데미지(plasma damage)에 의한 흡습 등에 의해 비아 저항이 불규칙해진다.Second, since the insulating film of low dielectric constant is exposed to the sidewall portion of the hole when the via hole is formed, the via resistance becomes irregular due to moisture absorption due to plasma damage during plasma etching.
셋째, 저유전율의 절연막은 높은 수소 밀도에 의해 PECVD절연막과의 흡착력이 약하기 때문에 와이어 본딩(wire bonding)시 하부 배선과 상부 배선 사이의 PECVD절연막과 저유전율의 절연막과의 계면에서 결합력이 저하되고, 이로 인해 절연층이 들뜨는 불량이 발생하여 절연층의 신뢰성을 저하시킨다.Third, since the low dielectric constant insulating film has a weak adsorption force with the PECVD insulating film due to the high hydrogen density, the bonding strength is decreased at the interface between the PECVD insulating film and the low dielectric constant insulating film between the lower wiring and the upper wiring during wire bonding. This causes a defect in which the insulating layer is lifted up, thereby lowering the reliability of the insulating layer.
본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 안출한 것으로, 저유전율의 절연막의 표면밀도를 강화하고, 배선간의 저유전율이 차지하는 비율을 극대화하여 배선간의 커패시턴스를 감소시키며, 절연특성을 개선시킬 수 있는 반도체 소자의 배선형성방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems of the prior art, to enhance the surface density of the insulating film of the low dielectric constant, to maximize the ratio of the low dielectric constant between the wiring to reduce the capacitance between the wiring, improve the insulation characteristics It is an object of the present invention to provide a wiring forming method of a semiconductor device.
도 1a 내지 1f는 종래 기술에 따른 반도체 소자의 배선 형성방법을 설명하기 위한 공정단면도1A to 1F are cross-sectional views illustrating a method of forming wirings in a semiconductor device according to the related art.
도 2a 내지 2g는 본 발명에 따른 반도체 소자의 배선 형성방법을 설명하기 위한 공정단면도2A through 2G are cross-sectional views illustrating a method of forming wirings in a semiconductor device according to the present invention.
도면의 주요부분에 대한 부호의 설명Explanation of symbols for main parts of the drawings
11,21 : 절연기판 또는 하부절연층 13,22 : 제 1 절연층(HSQ)11,21: insulating substrate or lower insulating layer 13,22: first insulating layer (HSQ)
22a : 질화층 12,23 : 하부배선22a: nitride layer 12, 23: lower wiring
14,24 : 제 2 절연층 16,25 : 비아 홀14,24: second insulating layer 16,25: via hole
17,26 : 상부배선17,26: upper wiring
상기의 목적을 달성하기 위한 본 발명 반도체 소자의 배선 형성방법은 절연기판 또는 하부절연층상에 저유전율의 제 1 절연층을 형성하는 공정과, 상기 제 1 절연층을 선택적으로 제거하여 하부 배선이 형성될 영역을 정의하는 공정과, 상기 제 1 절연층을의 표면을 질화층으로 변화시키는 공정과, 상기 제 1 절연층이 제거된 부분에 하부배선을 형성하는 공정과, 상기 표면이 질화층으로 변화된 제 1 절연층 및 상기 하부배선상에 제 2 절연층을 형성하는 공정과, 상기 하부배선이 노출되도록 상기 제 2 절연층에 비아 홀을 형성하는 공정과, 상기 비아 홀을 통해 상기 하부배선과 연결되는 상부배선을 형성하는 공정을 포함하여 이루어짐을 특징으로 한다.In order to achieve the above object, a method of forming a wiring of a semiconductor device according to the present invention includes forming a low dielectric constant first insulating layer on an insulating substrate or a lower insulating layer, and selectively removing the first insulating layer to form lower wiring. Defining a region to be formed, changing the surface of the first insulating layer to a nitride layer, forming a lower wiring in a portion where the first insulating layer is removed, and changing the surface to a nitride layer Forming a second insulating layer on the first insulating layer and the lower wiring; forming a via hole in the second insulating layer to expose the lower wiring; and connecting the lower wiring through the via hole. Characterized in that it comprises a step of forming the upper wiring to be.
이하, 본 발명 반도체 소자의 배선 형성방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a wiring forming method of the semiconductor device of the present invention will be described with reference to the accompanying drawings.
먼저, 본 발명은 저유전율을 갖는 HSQ(Hydrogen-Silsesquioxane) 계열의 SOG막의 표면밀도를 강화시키고, damascene구조를 이용하여 배선간에 저유전율이 차지하는 비율을 극대화시켜 배선간의 커패시턴스를 감소시키는데 특징이 있다.First, the present invention is characterized by reducing the surface-to-wire capacitance by enhancing the surface density of a HSQ (Hydrogen-Silsesquioxane) -based SOG film having a low dielectric constant, and maximizing the ratio of the low dielectric constant between wirings using a damascene structure.
그리고, damascene구조에 의해서 하부 배선과 상부 배선과의 사이에 PECVD절연막만 존재하도록하여 비아 홀의 신뢰성 및 패키징을 위한 와이어 본딩시 HSQ의 낮은 흡착특성에 기인한 와이어 본딩의 불량을 방지하는데 특징이 있다.In addition, the damascene structure allows only the PECVD insulating film to exist between the lower interconnection and the upper interconnection to prevent defects in wire bonding due to low adsorption characteristics of HSQ during wire bonding for via hole reliability and packaging.
통상의 HSQ는 무기계열의 SOG로서 넌-에치백(non-etchback)이 가능하므로 공정이 간단하고, 저밀도에 의한 저유전 특성을 가지므로 배선의 층간절연막으로 각광을 받고 있다.Conventional HSQ is an inorganic SOG that can be non-etched back, and thus has a simple process and low dielectric properties due to low density.
그러나 HSQ는 O2플라즈마에 매우 취약하기 때문에 비아 홀 형성시 수반되는 상기 O2플라즈마에 의해 막질이 변질되어 저유전 특성이 상실되기도 한다.However, since the HSQ it is highly susceptible to O 2 plasma is the film quality is deteriorated by the O 2 plasma involved in forming the via-holes and also a low dielectric loss characteristics.
이러한 문제점은 NH3플라즈마 처리나, N2분위기의 RTP(Rapid Thermal Process)를 통해 표면의 수소가 탈착되면서 순간적으로 고밀도의 절연층으로 변화하는 특성을 이용하면 O2와 결합하는 수소가 이미 제거된 상태이므로 플라즈마 데미지로부터 HSQ를 보호할 수 있다.This problem is NH 3 as the hydrogen on the surface removable through the plasma treatment or, RTP (Rapid Thermal Process) in N 2 atmosphere, the instantaneously by using a characteristic changing in the insulating layer of the high density of hydrogen in combination with O 2 already removed This condition protects the HSQ from plasma damage.
만일, 이러한 질소-베이스(N2-base)의 표면처리들이 통상적인 배선의 층간절연막 형성방법으로 이루어질 경우, 비아 홀의 데미지를 막을 수는 있으나 하부 배선과 상부 배선 사이에 잔류하는 HSQ의 대부분은 질화가 어렵기 때문에 와이어 본딩시 흡착 불량을 막기는 어렵다.If such surface treatment of nitrogen-based (N 2 -base) is made by the conventional method of forming an interlayer insulating film of wiring, it is possible to prevent the damage of the via hole, but most of the HSQ remaining between the lower wiring and the upper wiring is nitrided. Since it is difficult to prevent poor adsorption at the time of wire bonding.
따라서, 본 발명은 비아 홀의 데미지를 막을 수 있으며, 와이어 본딩시 흡착불량을 개선시킬 수 있는 방법을 제안한다.Therefore, the present invention proposes a method that can prevent the damage of the via holes and improve the adsorption defects during wire bonding.
도 2a 내지 2g는 본 발명 반도체 소자의 배선형성방법을 설명하기 위한 공정단면도이다.2A to 2G are cross-sectional views showing a process for forming a wiring of the semiconductor device of the present invention.
도 2a에 도시한 바와 같이, 절연기판 또는 하부절연층(21)상에 제 1 절연층으로서, HSQ층(22)을 형성한다.As shown in FIG. 2A, the HSQ layer 22 is formed as the first insulating layer on the insulating substrate or the lower insulating layer 21.
이후, 하부 배선을 형성하기 위해 도 2b에 도시한 바와 같이, 상기 HSQ층(22)상에 포토레지스트(도시하지 않음)를 도포한 후, 패터닝하고, 상기 패터닝된 포토레지스트를 마스크로 상기 HSQ층(22)을 선택적으로 제거하여 하부 배선이 형성될 영역(A)을 확보한다.Then, as shown in FIG. 2B to form a lower wiring, a photoresist (not shown) is applied on the HSQ layer 22, and then patterned, and the HSQ layer is patterned using the patterned photoresist as a mask. Optionally remove 22 to secure the area A in which the lower wiring is to be formed.
이후, 상기 포토레지스트를 제거하게 되는데, 상기 포토레지스트 제거를 위한 O2플라즈마에 의해 HSQ층(22)의 표면은 일부 데미지를 입게된다.Thereafter, the photoresist is removed, and the surface of the HSQ layer 22 is partially damaged by the O 2 plasma for removing the photoresist.
상기 HSQ층(22)이 데미지를 입은 상태에서 질소를 포함하는 분위기에서 열처리 혹은 플라즈마 처리를 행한다.Heat treatment or plasma treatment is performed in an atmosphere containing nitrogen while the HSQ layer 22 is damaged.
질소 분위기에서 열처리하면, 도 2c에 도시한 바와 같이, 데미지 입은HSQ층(22)이 질화층(22a)으로 변화한다.When the heat treatment is performed in a nitrogen atmosphere, as shown in FIG. 2C, the damaged HSQ layer 22 is changed into the nitride layer 22a.
질화층(22a)은 소수성의 특성으로 변화하므로 흡습에 매우 강하고, 이후에 비아 홀을 매립할 때, 수분 발생을 억제한다.Since the nitride layer 22a changes due to the hydrophobic property, the nitride layer 22a is very resistant to moisture absorption, and subsequently suppresses the generation of moisture when the via hole is filled.
또한, 종래에서처럼 저유전율을 갖는 절연막을 별도로 형성하지 않기 때문에 이후에 배선을 형성할 경우, 배선과 배선 사이는 오직 표면이 질화층(22a)으로 이루어진 HSQ층(22)만이 존재하게 되어 충분히 저유전율 특성을 활용할 수 있다.In addition, since an insulating film having a low dielectric constant is not formed separately as in the prior art, when wiring is formed later, only the HSQ layer 22 having the surface of the nitride layer 22a exists between the wiring and the wiring, so that the dielectric constant is sufficiently low. Can take advantage of characteristics
이어, 도 2d에 도시한 바와 같이, 표면이 질화층(22a)으로 이루어진 HSQ층(22)을 포함한 전면에 배선 물질층을 형성한 후, CMP공정을 수행하여 상기 HSQ층(22)의 사이사이에 하부 배선(23)들을 형성한다.Subsequently, as shown in FIG. 2D, a wiring material layer is formed on the entire surface including the HSQ layer 22 formed of the nitride layer 22a, and then a CMP process is performed between the HSQ layers 22. Lower wirings 23 are formed on the substrate.
이어서, 도 2e에 도시한 바와 같이, 상기 하부 배선(23)들을 포함한 전면에 상기 하부 배선(23)과 이후에 형성될 상부 배선과의 절연을 위한 제 2 절연층(24)으로써, PECVD절연막을 형성한다.Next, as shown in FIG. 2E, a PECVD insulating film is formed on the front surface including the lower wirings 23 as a second insulating layer 24 for insulating the lower wirings 23 and the upper wirings to be formed later. Form.
상기 제 2 절연층(24)은 통상적인 실리콘 산화막의 유전율을 가지므로 저유전 특성은 없으나, 배선과의 흡착이 우수하므로 향후 와이어 본딩시 고압에 대한 저항능력으로 층간절연층의 파괴를 방지하여 패키지의 불량을 방지한다.Since the second insulating layer 24 has a dielectric constant of a conventional silicon oxide film, there is no low dielectric property. However, since the second insulating layer 24 has excellent adsorption with wiring, the second insulating layer 24 has a resistance against high voltage during wire bonding to prevent breakdown of the interlayer insulating layer To prevent bad.
이어, 도 2f에 도시한 바와 같이, 상기 제 2 절연층(24)상에 포토레지스트(도시하지 않음)를 도포한 후, 패터닝하여 비아 콘택을 정의한다.Subsequently, as shown in FIG. 2F, a photoresist (not shown) is applied on the second insulating layer 24, and then patterned to define a via contact.
이후, O2플라즈마 에칭을 통해 상기 제 2 절연층(24)을 소정부분 제거하여 하부배선(23)이 노출되는 비아 홀(25)을 형성한다.Thereafter, the second insulating layer 24 is removed by O 2 plasma etching to form a via hole 25 through which the lower wiring 23 is exposed.
이때, 상기 PECVD절연막인 상기 제 2 절연층(24)은 O2플라즈마에 대한 저항성이 우수하므로 넌-에치백 방식의 배선의 층간절연막 형성시 HSQ층(22)의 데미지를 방지하여 안정적으로 비아 홀을 형성할 수 있다.At this time, since the second insulating layer 24, which is the PECVD insulating film, has excellent resistance to O 2 plasma, it prevents damage of the HSQ layer 22 when forming the interlayer insulating film of the non-etch back type wiring, thereby stably via hole. Can be formed.
이어서, 도 2g에 도시한 바와 같이, 상기 비아 홀(25)을 통해 상기 하부 배선(23)과 연결되는 상부 배선(26)을 형성하면, 본 발명의 반도체 소자의 배선 형성공정이 완료된다.Subsequently, as shown in FIG. 2G, when the upper wiring 26 connected to the lower wiring 23 is formed through the via hole 25, the wiring forming process of the semiconductor device of the present invention is completed.
이상 상술한 바와 같이, 본 발명은 다음과 같은 효과가 있다.As described above, the present invention has the following effects.
첫째, HSQ층의 표면에 질화층을 형성하여 HSQ층에 의한 흡습을 방지할 수 있으므로 비아홀 매립시에 수분 발생을 억제시킬 수 있어 배선이 부식되는 현상을 방지할 수 있다.First, since a nitride layer is formed on the surface of the HSQ layer to prevent moisture absorption by the HSQ layer, moisture generation can be suppressed during via hole filling, thereby preventing corrosion of the wiring.
둘째, HSQ층을 형성한 후 하부 배선을 형성하여 하부 배선 사이의 HSQ층의 공간을 충분히 확보할 수 있으므로 배선간 캐패시턴스를 감소시킬 수 있다.Second, since the formation of the lower wiring after forming the HSQ layer can ensure a sufficient space of the HSQ layer between the lower wiring, it is possible to reduce the capacitance between the wiring.
셋째, 제 2 절연층으로 O2플라즈마에 대한 저항성이 우수한 PECVD 절연막을 이용하므로 제 2 절연층에 비아홀을 형성하는 공정에서 O2플라즈마에 의한 데미지를 방지할 수 있다.넷째, 제 2 절연층으로 배선과의 흡착력이 우수한 PECVD 절연막을 이용하여 와이어 본딩시 고압이 인가되더라도 절연층이 들뜨는 현상을 방지할 수 있으므로 절연층의 신뢰성을 향상시킬 수 있다.Third, since a PECVD insulating film having excellent resistance to O 2 plasma is used as the second insulating layer, damage by O 2 plasma can be prevented in the process of forming a via hole in the second insulating layer. By using a PECVD insulating film having excellent adhesion to the wiring, even if a high pressure is applied during wire bonding, the insulating layer can be prevented from being lifted, thereby improving the reliability of the insulating layer.
Claims (5)
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| JPH05308073A (en) * | 1992-04-30 | 1993-11-19 | Clarion Co Ltd | Manufacture of semiconductor device |
| JPH1187502A (en) * | 1997-09-09 | 1999-03-30 | Toshiba Corp | Manufacture of semiconductor device |
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| JPH05308073A (en) * | 1992-04-30 | 1993-11-19 | Clarion Co Ltd | Manufacture of semiconductor device |
| JPH1187502A (en) * | 1997-09-09 | 1999-03-30 | Toshiba Corp | Manufacture of semiconductor device |
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