KR100368981B1 - Metal wiring formation method of semiconductor device - Google Patents
Metal wiring formation method of semiconductor device Download PDFInfo
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- KR100368981B1 KR100368981B1 KR10-1998-0025775A KR19980025775A KR100368981B1 KR 100368981 B1 KR100368981 B1 KR 100368981B1 KR 19980025775 A KR19980025775 A KR 19980025775A KR 100368981 B1 KR100368981 B1 KR 100368981B1
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- titanium silicide
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- 239000002184 metal Substances 0.000 title claims abstract description 25
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000011229 interlayer Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000004140 cleaning Methods 0.000 claims abstract description 8
- 229910021341 titanium silicide Inorganic materials 0.000 claims description 11
- 239000012535 impurity Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims 2
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 230000004888 barrier function Effects 0.000 abstract description 13
- 239000004020 conductor Substances 0.000 abstract description 2
- 229910021332 silicide Inorganic materials 0.000 abstract 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 abstract 1
- 239000007789 gas Substances 0.000 description 9
- 229910008484 TiSi Inorganic materials 0.000 description 8
- 239000010410 layer Substances 0.000 description 6
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 3
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000005429 filling process Methods 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- 239000013078 crystal Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011534 incubation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 베리어 금속막의 사용없이, 미세한 콘택홀 내에 용이하게 전도체를 매립할 수 있는 반도체 소자의 금속 배선 형성방법을 개시한다.The present invention discloses a method for forming a metal wiring of a semiconductor device which can easily embed a conductor in a fine contact hole without the use of a barrier metal film.
개시된 본 발명은, 반도체 기판상에 콘택홀을 구비한 층간 절연막을 형성하는 단계와, 상기 반도체 기판 결과물을 챔버내에 장입하고, 소정 온도에서 클리닝하는 단계와, 상기 콘택홀 내부가 충분히 충진되도록, 티타늄 실리사이드 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.According to the present invention, there is provided a method of forming an interlayer insulating film having contact holes on a semiconductor substrate, charging the semiconductor substrate resultant into a chamber, cleaning at a predetermined temperature, and filling the inside of the contact hole sufficiently, Forming a silicide plug.
Description
본 발명은 반도체 소자의 금속 배선 형성방법에 관한 것으로, 보다 구체적으로는 베리어 금속막의 사용없이, 미세한 콘택홀 내에 용이하게 전도체를 매립할 수 있는 반도체 소자의 금속 배선 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices in which a conductor can be easily embedded in minute contact holes without using a barrier metal film.
반도체 소자의 집적도가 증가함에 따라, 금속 배선간을 연결하는 콘택홀의 사이즈는 감소되고, 그 깊이또한 깊어진다. 이에따라, 콘택홀내에 금속 배선을 충진시키기가 매우 어렵다.As the degree of integration of semiconductor devices increases, the size of the contact holes connecting the metal lines decreases, and the depth thereof also deepens. Accordingly, it is very difficult to fill the metal wiring in the contact hole.
종래에는 도 1에 도시된 바와 같이, 접합 영역(1a)이 구비된 반도체 기판(1)상에 접합 영역(1a)이 노출되도록 콘택홀(H1)이 구비된 층간 절연막(2)을 형성한다. 그후, 콘택홀(H1) 내벽에 화학 기상 증착 방식(chemical vapor deposition: 이하 CVD)에 의하여 Ti/TiN으로 된 베리어 금속막(3)을 피복한다. 그리고나서, 콘택홀(H1)내에 공간 매립 특성이 우수한 텅스텐 금속막을 이용하여 플러그(4)를 형성한다.In the related art, as shown in FIG. 1, the interlayer insulating layer 2 having the contact hole H1 is formed on the semiconductor substrate 1 having the junction region 1a so as to expose the junction region 1a. Thereafter, the barrier metal film 3 made of Ti / TiN is coated on the inner wall of the contact hole H1 by chemical vapor deposition (CVD). Then, the plug 4 is formed using a tungsten metal film having excellent space filling characteristics in the contact hole H1.
그러나, 상기한 종래의 콘택홀 매립 공정은 다음과 같은 문제점을 갖는다.However, the conventional contact hole filling process described above has the following problems.
첫째로, 상기한 콘택홀 매립 공정은 베리어 금속막(3)을 형성한다음, 플러그(4)를 형성하여야 하므로 공정이 복잡하다.First, the above-mentioned contact hole filling process is complicated by forming the barrier metal film 3 and then forming the plug 4.
둘째로, 베리어 금속막(3) 역시 일정한 두께를 지니므로, 결과적으로 베리어 금속막(3)이 콘택홀의 사이즈를 줄이게 된다. 이로 인하여, 플러그(4)의 매립특성이 저하되어, 콘택 저항이 증대된다.Secondly, the barrier metal film 3 also has a constant thickness, so that the barrier metal film 3 reduces the size of the contact hole. For this reason, the embedding characteristic of the plug 4 falls, and contact resistance increases.
셋째로, 콘택홀내에는 기판 실리콘과 Ti의 계면, Ti와 TiN간의 계면, TiN과 텅스텐 금속의 계면이 존재하므로, 누설전류가 발생되기 쉽다.Third, since the interface between the substrate silicon and Ti, the interface between Ti and TiN, and the interface between TiN and tungsten metal exist in the contact hole, leakage current is likely to occur.
따라서, 본 발명은 상기한 종래의 문제점을 해결하기 위한 것으로, 베리어 금속막을 사용하지 않고도 미세한 콘택홀을 용이하게 매립시킬 수 있는 반도체 소자의 금속 배선 형성방법을 제공하는 것을 목적으로 한다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device capable of easily filling a fine contact hole without using a barrier metal film.
도 1은 종래의 콘택홀 매립방법을 설명하기 위한 도면1 is a view for explaining a conventional contact hole filling method
도 2a 내지 도 2c는 본 발명에 따른 콘택홀 형성방법을 설명하기 위한 도면.2a to 2c are views for explaining a method for forming a contact hole according to the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 기판 11a: 접합 영역11 substrate 11a junction region
12 : 층간 절연막 13 : 티타늄 실리사이드막12: interlayer insulating film 13: titanium silicide film
13a : 티타늄 실리사이드 플러그13a: titanium silicide plug
상기한 본 발명의 목적을 달성하기 위하여, 본 발명의 일 실시예에 따르면, 반도체 기판상에 콘택홀을 구비한 층간 절연막을 형성하는 단계와, 상기 반도체 기판 결과물을 챔버내에 장입하고, 소정 온도에서 클리닝하는 단계와, 상기 콘택홀 내부가 충분히 충진되도록, 티타늄 실리사이드 플러그를 형성하는 단계를 포함하는 것을 특징으로 한다.In order to achieve the above object of the present invention, according to an embodiment of the present invention, forming an interlayer insulating film having a contact hole on a semiconductor substrate, and the resulting semiconductor substrate in the chamber and at a predetermined temperature Cleaning and forming a titanium silicide plug such that the inside of the contact hole is sufficiently filled.
본 발명에 의하면, 플러그를 C54 구조를 갖는 TiSi2으로 형성하므로써, 별도의 베리어 금속막이 요구되지 않는다.According to the present invention, by forming the plug from TiSi 2 having a C54 structure, a separate barrier metal film is not required.
이에따라, 공정이 단축되고, 베리어 금속막 증착으로 인한 콘택홀 사이즈 축소라는 문제점이 해결된다.Accordingly, the process is shortened and the problem of reducing the contact hole size due to barrier metal film deposition is solved.
(실시예)(Example)
이하 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 자세히 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
첨부한 도면 도 2a 내지 도 2d는 본 발명에 따른 반도체 소자의 금속 배선 형성방법을 설명하기 위한 도면이다.2A to 2D are diagrams for describing a method for forming metal wirings of a semiconductor device according to the present invention.
도 2a를 참조하여, 접합 영역(11a)이 구비된 반도체 기판(11) 상에 층간 절연막(12)을 형성한다. 이어서, 접합 영역(11a)이 노출되도록, 층간 절연막(12)을 식각하여, 콘택홀(H2)을 형성한다.Referring to FIG. 2A, an interlayer insulating film 12 is formed on the semiconductor substrate 11 provided with the junction region 11a. Next, the interlayer insulating film 12 is etched to expose the junction region 11a to form the contact hole H2.
그후, 콘택홀(H2)이 형성된 결과물을 종래의 베리어 금속막(Ti)을 증착하였던 CVD 챔버, 또는 폴리실리콘을 증착하는 챔버에 장입한다음, 챔버내 온도가 650 내지 750℃가 되도록 히팅(heating)한다. 그리고나서, 챔버내에 SiH4가스를 주입하여 클리닝(cleaning) 공정을 실시한다. 이때, 클리닝시 챔버내 압력이 1.2mTorr 정도가 되도록 SiH4가스의 양을 8 내지 10 sccm의 플로우 레이트(flow rate)로 주입한다. 여기서, SiH4가스에 의한 클리닝 공정은 콘택홀(H2) 저면에 자연 산화막을 제거하여 인큐베이션 타임(incubation time)을 증대시키면서, 콘택홀(H2) 매립용 물질의 핵 생성을 증대시키는 역할을 한다.Thereafter, the resultant in which the contact hole H2 is formed is charged into a CVD chamber in which a conventional barrier metal film Ti is deposited or a chamber in which polysilicon is deposited. )do. Then, SiH 4 gas is injected into the chamber to perform a cleaning process. At this time, the amount of SiH 4 gas is injected at a flow rate of 8 to 10 sccm so that the pressure in the chamber is about 1.2 mTorr during cleaning. Here, the cleaning process by SiH 4 gas increases the incubation time by removing the native oxide film on the bottom of the contact hole H2 and increases the nucleation of the material for filling the contact hole H2.
그리고나서, 챔버내에 TiCl4가스와 SiH4가스를 주입한다. 그러면, 도 2b에 도시된 바와 같이, 이들 가스 사이의 반응물인 C54 구조를 갖는 티타늄 실리사이드층(13:TiSi2)이 콘택홀(H2)내에 매립된다. 여기서, SiH4가스는 8 내지 10 sccm의 플로우 레이트로 주입하고, TiCl4가스는 0.1 내지 0.5 sccm 정도로 주입함이 바람직하다. 이때, 증착 공정시, 콘택 저항을 더욱 감소시키기 위하여, 증착 초기에 PCl3가스를 주입할 수 있다. 이는 TiSi2층(13)내에 P 불순물의 농도를 증대시키어, TiSi2층(13)의 전도성을 개선하기 위함이다.Then, TiCl 4 gas and SiH 4 gas are injected into the chamber. Then, as shown in FIG. 2B, a titanium silicide layer 13 (TiSi 2 ) having a C54 structure that is a reactant between these gases is embedded in the contact hole H2. Here, SiH 4 gas is injected at a flow rate of 8 to 10 sccm, and TiCl 4 gas is preferably injected at about 0.1 to 0.5 sccm. In this case, in order to further reduce the contact resistance during the deposition process, the PCl 3 gas may be injected at the beginning of the deposition. This is to improve the conductivity, TiSi 2 layer 13 sikieo increasing the concentration of P impurities in the TiSi 2 layer 13.
그후에, 도 2c에 도시된 바와 같이, TiSi2층(13)을 상기 층간 절연막(12) 표면이 노출되도록 에치백(etch back) 또는 CMP(chemical vapor deposition) 공정을 실시하여, 티타늄 실리사이드로 된 플러그(13a)를 형성한다.Then, as shown in FIG. 2C, the TiSi 2 layer 13 is subjected to an etch back or chemical vapor deposition (CMP) process to expose the surface of the interlayer insulating film 12, thereby forming a plug of titanium silicide. (13a) is formed.
본 실시예에서는 콘택홀내에 형성되는 플러그를 가장 안정한 크리스탈 구조인 C54 구조를 갖는 TiSi2로 형성한다. 이때, TiSi2층(13)은 종래의 플러그 금속막에 비하여, 기판(11) 및 층간 절연막(12)과의 접촉 특성이 우수하므로, 콘택홀 내벽에 별도의 베리어 금속막을 형성하지 않아도 된다. 또한, 콘택홀내에 여러개의 계면이 존재하지 않으므로, 누설 전류도 발생되지 않는다.In this embodiment, the plug formed in the contact hole is formed of TiSi 2 having a C54 structure which is the most stable crystal structure. At this time, since the TiSi 2 layer 13 has better contact characteristics with the substrate 11 and the interlayer insulating film 12 than the conventional plug metal film, it is not necessary to form a separate barrier metal film on the inner wall of the contact hole. In addition, since several interfaces do not exist in the contact hole, no leakage current is generated.
이상에서 자세히 설명된 바와 같이, 본 발명에 의하면, 플러그를 C54 구조를 갖는 TiSi2으로 형성하므로써, 별도의 베리어 금속막이 요구되지 않는다.As described in detail above, according to the present invention, by forming the plug from TiSi 2 having a C54 structure, a separate barrier metal film is not required.
이에따라, 공정이 단축되고, 베리어 금속막 증착으로 인한 콘택홀 사이즈 축소라는 문제점이 해결된다.Accordingly, the process is shortened and the problem of reducing the contact hole size due to barrier metal film deposition is solved.
또한, 콘택홀내에 여러개의 계면이 존재하지 않으므로, 누설 전류도 발생되지 않는다.In addition, since several interfaces do not exist in the contact hole, no leakage current is generated.
기타, 본 발명은 그 요지를 일탈하지 않는 범위에서 다양하게 변경하여 실시할 수 있다.In addition, this invention can be implemented in various changes within the range which does not deviate from the summary.
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| KR10-1998-0025775A KR100368981B1 (en) | 1998-06-30 | 1998-06-30 | Metal wiring formation method of semiconductor device |
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| JPS6151918A (en) * | 1984-08-22 | 1986-03-14 | Fujitsu Ltd | Manufacture of semiconductor device |
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| JPS6151918A (en) * | 1984-08-22 | 1986-03-14 | Fujitsu Ltd | Manufacture of semiconductor device |
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