KR100368861B1 - Method of repairing over erased cell in non-volatile memory - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, comprising: a plurality of word lines connecting control gate electrodes of a memory cell unit; A plurality of sector row blocks comprising a row unit consisting of a plurality of bit lines and a plurality of bit lines connecting the drain region of the cell (I / O) block The present invention relates to a NOR type nonvolatile semiconductor memory device having: More specifically, the present invention relates to a method of erasing the nonvolatile semiconductor memory, and includes a repair for preventing a false operation caused by an over erased cell in an erase operation of the nonvolatile NOR semiconductor memory cell. In the conventional method of erasing cell data, the over-erased cell distribution forms a tail of a normal distribution and performs over-erasure verification for each cell even though it occupies a small portion of the entire cell. In order to overcome the disadvantages to be performed, the erase operation time of a cell can be reduced by simultaneously performing erase verification on a cell connected to one bit line in a sector.

Description

Method of repairing over erased cell in non-volatile memory}

The present invention provides a nonvolatile semiconductor memory device which shortens over erase verification time by simultaneously performing over erase verification on a cell connected to one bit line in a sector during over erase verification of a semiconductor memory device having a NOR-type memory cell structure. It is about.

With reference to the accompanying drawings will be introduced a conventional technology with a basic description of the NOR-type semiconductor memory device. 1 illustrates a unit cell structure of a NOR flash semiconductor memory device.

Referring to FIG. 1, a unit cell of a NOR-type semiconductor memory device may include a p-type semiconductor substrate 10 and a drain region 12 formed at a predetermined distance from a predetermined source region and a source region formed thereon. A thin tunnel oxide layer 13 is formed on the drain region located at a distance from the source and a channel forming region between the source and the drain to serve as a potential well, and is formed thereon. It consists of a floating gate 15 for storage and an electrode of a control gate 16 insulated by another insulating film 14 formed on the floating gate.

A typical NOR write operation of a semiconductor memory device applies another high voltage between a source and a drain while a high voltage is applied to a control gate, thereby injecting a hot carrier generated near a drain into the floating gate. For example, Vg = 10V, Vd = 6 ~ 9V, Vs = 0V, Vb = 0V. This injection of electrons is a series of actions that raises the threshold voltage of the memory cell.

The conditions at this time are shown in Figs. 2 (a) and 2 (b). The memory cells must perform a data erase operation prior to a data write operation due to their characteristics, which is usually FN tunneling. Nordheim tunneling phenomenon is used. Since F-N tunneling is an operation requiring a relatively long time due to its small amount of current, F-N tunneling is generally performed in a unit of a predetermined cell bundle.

In the erase operation, a predetermined negative high voltage (eg, −10 V) is applied to the control gate electrode 16, and a predetermined positive high voltage (eg, +5 V) is applied to the source region 11. A high electric field of 7 MV / cm or more is induced in the insulating layer 13 between the control gate and the source region so that electrons in the floating gate are ejected into the source region by FN tunneling through the insulating layer by the high electric field. This operation lowers the threshold voltage. In this case, the drain 12 region is made floating in order to improve the efficiency of the erase operation.

The conditions at this time are shown in FIG. 3 (a) and FIG. 3 (b).

In the semiconductor memory cell, the tunnel oxide film quality may not be uniform due to its characteristics. In particular, in the case of a cell having a relatively thin tunnel oxide film thickness, a higher electric field is applied under the same bias condition so that the semiconductor memory cell may be in a negative direction during an erase operation. The problem is that the degree of movement increases. Such a cell is generally called a fast cell, and this state is called over erase. In particular, a NOR flash semiconductor memory is a big problem.

In a typical flash semiconductor memory, a word line that is not selected during a read operation is applied with a voltage of 0 V. At this time, if the over erase cell has a negative threshold voltage, the load current of the bit line through the unselected memory cell ( This is because the load current is released, which affects the normal read operation. The distribution of the over erased cells is shown in FIG.

An erase verify voltage level 40 for determining that the erase is completed when the voltage is less than the predetermined voltage during the erase operation, and a program verify voltage level 41 for determining that the write is completed when the voltage exceeds the predetermined voltage during the write operation. And margin levels 41 that may be present in a read operation.

As shown in the figure, there is an erase cell distribution that does not have a normal Gaussian distribution by the fast cells in the absence of an over erase verification action. In order to prevent the problem caused by the over erase cells, the over erase verification operation is performed after the erase operation. At this time, the distribution of the cells is gathered above a predetermined over erase verify level 42 through a soft program.

In the conventional technology, the over erase read operation during the over erase verify operation is performed on individual cells and is completed after a predetermined routine is performed. An example of such a routine according to the prior art is shown in FIG. 5, and the source is Korean Patent Application Publication No. 1999-0042720, Application No. 10-1997-0063619.

As shown in FIG. 5, the conventional over erase remedy method performs a sequential over erase verification in a bit by bit manner on a row address in an erase sector, and when over erased cells are found, If a soft program is executed and the end of the row address in the sector is reached, the column address is increased by one, and the above routine is repeated at the first sector row address.

Therefore, in the present invention, the over erase erase read process, which is performed separately for individual bits in the conventional NOR-type flash semiconductor memory device, is performed at the same time by the number of cells of word lines in a predetermined erase sector unit. The goal is to reduce the time taken to verify reads.

In general, it has been reported that the ratio of fast cells which are rapidly erased by thinning of the partial tunnel insulating film in a cell of a NOR flash semiconductor memory device is less than 0.01%. Thus, assuming that there are 16 word lines in a sector within the same sector, the probability that one of the 16 adjacent cells is over erased is less than 1%. The over erase verification read process searches for a cell that maintains the bit line at a low level because the current capacity is greater than that of the cell used as the reference of the over erase verify level. Without this, the bit line is charged to a high level so that it can be easily distinguished.

1 is a schematic vertical view showing a unit cell of a conventional NOR fresh semiconductor memory device.

2 is a schematic diagram showing a write operation of a conventional NOR fresh semiconductor memory device.

3 is a schematic diagram showing an erase operation of a conventional NOR fresh semiconductor memory device.

4 is a representative diagram showing a threshold voltage distribution of a cell in a conventional NOR fresh semiconductor memory device.

5 is a flowchart illustrating the performance of an over erase repair operation in a NOR type fresh semiconductor memory device in the prior art.

6 is a schematic block diagram for explaining a configuration and operation of a memory cell array in a NOR fresh semiconductor memory device.

7 is a flowchart for explaining an over erase repair operation performed in a NOR fresh semiconductor memory device according to the present invention.

6 is a configuration diagram of a memory array for explaining the over erase verification diary operation according to the present invention. Each configuration reads data of a predetermined sub bit line (B / L0 to B / Li) divided by a sector 61, which is a predetermined word line bundle, and a column free decoder 62. A sense block 67 and the like.

When the erase verify read operation is started, all word lines connected to the row free decoder 60-2 of FIG. 6 are simultaneously enabled with a predetermined voltage. The most distinctive feature of the conventional sequential word line enable method is this simultaneous word line enable part. For example, in the case of sector 0, all word lines (W / L 0 to W / L i) connected to B / L0 of sector 0 (61) are enabled at the same time, for all cells connected to B / L 0 in the sector. At the same time, an erase erase read operation is performed. Over-Erase Verification Even with any over- erased cell, cell current flows to keep the bit line low. However, when there are no over erased cells, the cells are turned off and the bit line is charged to a predetermined level and read out to a high level. The probability that there are over erased cells is less than 1%, so it is mostly read as verification success. If the verification is successful, the over erase verify read operation is performed on the next bit line.

If a bit line low level is detected due to the presence of an over erase cell for a specific bit line during the over erase verify read operation, a bit by bit verification method is performed on individual word lines. The bit-by-bit verification method achieves the same result whether the word line address is sequentially increased for a specific bit line or the column address is sequentially increased for a specific word line.

7 is a flowchart illustrating the over erase verification read method according to the present invention.

After entering the erase repair operation, all column addresses are set to " 0 " (70). After enabling all word lines of the selected sector (71: for example, W in FIG. 6). / L 0 to W / L i) and the erase verify read operation 72 is performed, and the presence or absence of the over erased cell is determined based on the read data (73). Repeat the operation, enable only the first column address in the sector if there are over erase cells (74), and reset the counter specifying the number of soft programs to "0" (75). Read the over erase of the row (76) and if over erased, then run the soft program (78). If there are no and erase cells, the above operation is repeated for the same next row. After the operation (78), if the over erase operation is read again and the state is over erased, the soft program process is repeated as many times as the predetermined soft program number (78, 79, 7-1, 7-6, 7-5).

If the above operations are completed for all cells of the selected bit line, the column address is increased by one step and the above operation is repeated. This operation is repeated until the last bit line is completed.

The present invention for reducing the over erase verification time of a NOR type nonvolatile semiconductor memory device starts from the statistical consideration that the over erased cells exist in less than 0.01% of the total normal distribution. This technology can reduce reading time to about 1/15 level.

When the present invention is applied to a NOR type nonvolatile semiconductor memory device, the over erase verification read time may be reduced to improve the erase performance of the device.

Claims (7)

In a typical NOR-type semiconductor memory device having a plurality of word lines and a plurality of bit lines and a plurality of memory cells arranged in a bit intersecting region with the word lines, a plurality of word lines and a plurality of cell lines connected to the same bit line may be provided. A word memory is enabled (enabled), the semiconductor memory device, characterized in that the state values of the cells connected to the plurality of word lines through a single bit line is applied to the bit line in a superimposed state. The semiconductor memory device of claim 1, wherein the plurality of word line structures have a sub word line driver structure having a tree shape. The semiconductor memory device according to claim 1, wherein the bit line structure has a sub bit line driver structure in a tree form. The method of claim 1, wherein the plurality of word line structures have a sub word line driver structure in a tree form, or the bit line structure has a sub bit line driver structure in a tree form. Or a complex type of two types. Electrically write, read, and erase data, and have a plurality of word lines, a plurality of bit lines, and a plurality of memory cells arranged in an area intersecting the word lines. Word line selection means for performing; In a semiconductor memory device having bit line selection means for selecting the bit line, after the data is erased, the state of the erased cell is converted into a threshold voltage of an appropriate erase level (generally termed a program). Performing over-erasing verify read operation for determining whether over-erasing is performed, and in case of over-erasing determination, changing a threshold voltage of a cell through a weak program, and repeating this process a predetermined number of times. And a predetermined program counter and a row and column address counter to perform the above process for each cell, and perform the over erase verify read operation on a plurality of cells connected to the same bit line at the same time. And an erase verification read operation time. The semiconductor memory device according to claim 1, wherein the plurality of word line bundles is equal to the number of sector word lines. 6. The semiconductor memory device according to claim 5, wherein the plurality of word line bundles is equal to the number of sector word lines.