KR100364603B1 - Cmos image sensor which shares common output buffer - Google Patents

Abstract

A CMOS image sensor sharing an output buffer section is disclosed. The CMOS image sensor according to the present invention includes a pixel array including a plurality of pixels arranged in rows and columns, the pixel array including a plurality of data transmission lines respectively transmitting data pairs generated from the pixels arranged in each column; A plurality of sample / hold pairs for receiving and holding the data pairs output from each of the data transmission lines, and transmitting the held data pairs in response to predetermined control signals input from the outside; And a buffer amplifying unit for comparing the signals of the data pairs transmitted from the sample / hold pairs, amplifying and outputting the compared result. The buffer amplifier is shared by a plurality of sample / hold pairs.

Therefore, compared with the prior art in which a buffer amplifier is arranged for each column, the present invention reduces the layout area by a plurality of columns sharing a buffer amplifier. And accordingly, the area of the light receiving portion in each pixel can be increased.

Description

CMOS image sensor sharing output buffer section {CMOS IMAGE SENSOR WHICH SHARES COMMON OUTPUT BUFFER}

The present invention relates to an image sensor implemented with a CMOS (Complementary Metal Oxide Semiconductor).

In general, an image sensor refers to a device that captures an image by using a property of a semiconductor that reacts to light. Part of each subject in the natural world has different electrical values at each pixel of the sensing device due to different brightness and wavelength of light. This electrical value is converted into a level capable of signal processing by the image sensor.

The CMOS image sensor uses a different method from a charge coupled device (hereinafter referred to as CCD) when outputting a signal. In other words, the CCD transfers the charge accumulated in the light receiving unit that performs the photoelectric conversion to the transmission unit, converts the voltage into a voltage at the final output terminal, and outputs it. On the other hand, the CMOS image sensor is characterized in that the charge accumulated in each pixel is output as a voltage.

1 is a view for explaining a conventional CMOS image sensor. The conventional CMOS image sensor includes a row decoder 103, a column select shift register 105, a pixel array 101, sample / hold pairs 107, and a buffer amplifier 109. Here, the pixel array 101 is composed of a plurality of pixel sensors, and the sample / hold pair 107 is composed of a reference sample / hold and a signal sample / hold.

Each pixel sensor is composed of photo diodes and MOS tran-sistors. The row decoder 103 selects a row of the pixel array 101 in response to a predetermined clock signal. The readout of the pixels of the selected row is completed when the readout is completed. In addition, the column selection shift register 105 may select a column of each pixel sensor sequentially in response to a clock signal output from a controller (not shown) when a row of the pixel array 101 is selected. The sample / hold pair 107 holds the voltage output from the pixel sensor of the column selected by the column select shift register 105, and outputs the held result to the buffer amplifier 109. That is, the voltage output from each pixel sensor is output to the buffer amplifier 109 through the column select register 105.

However, in the conventional CMOS image sensor, a buffer amplifier 109 is provided for each column. Therefore, a problem arises in that the layout area increases due to the buffer amplifier 109 arranged for each column.

An object of the present invention is to provide a CMOS image sensor for arranging a buffer output unit to minimize the layout area.

1 is a view for explaining a conventional CMOS image sensor.

2 is a block diagram schematically illustrating a CMOS image sensor according to an exemplary embodiment of the present invention.

3 is a circuit diagram illustrating a unit pixel sensor of the CMOS image sensor illustrated in FIG. 2.

FIG. 4 is a diagram for explaining timing of main signals and terminals related to driving of the CMOS image sensor of the present invention and holding of data accordingly. FIG.

<Description of the symbols for the main parts of the drawings>

101, 201: pixel array 103, 203: row decoder

105, 205: column select shift registers 107, 207: sample / hold pairs 109, 209: buffer amplifier

One aspect of the present invention for achieving the above object relates to a CMOS image sensor. The CMOS image sensor of the present invention includes a pixel array including a plurality of pixels arranged in rows and columns, the pixel array including a plurality of data transmission lines respectively transmitting data pairs generated from the pixels arranged in each column; A plurality of sample / hold pairs for receiving and holding the data pairs output from each of the data transmission lines, and for transmitting the held data pairs in response to predetermined control signals input from the outside; And a buffer amplifier configured to compare signals of data pairs transmitted from the sample / hold pairs, amplify and output the compared result. The buffer amplifier is shared by the plurality of sample / hold pairs. The data pair includes reference data output in a reset mode and signal data output in a signal mode, and each sample / hold pair includes: a reference sample / hold for selecting and holding the reference data; And a signal sample / hold for selecting and holding the signal data.

Hereinafter, a preferred embodiment of the CMOS image sensor according to the present invention will be described in detail with reference to FIGS. 2 to 4.

As shown in FIG. 2, the CMOS image sensor according to an embodiment of the present invention includes a row decoder 203, a column select shift register 205, a pixel array 201, a sample / hold 207, and a buffer amplification. It consists of a part 209. Here, the pixel array 201 is composed of a plurality of pixel sensors, and the sample / hold pair 207 is composed of a reference sample / hold 207a and a signal sample / hold 208b.

The row decoder 203 shown in Fig. 2 selects a row of the pixel array 201 in response to a predetermined address (not shown) signal. The pixels in the selected row are reset to output reference data. When the output of the reference data is completed, the signal data is output. The data pairs of the output reference data and the signal data are stored in the sample / hold 207 pair. That is, the reference data is stored in the reference sample / hold 207a and the signal data is stored in the signal sample / hold 207b.

As such, the data pairs of the reference data and the signal data stored in each sample / hold pair are transmitted to the buffer amplifier 209.

The buffer amplifier 209 is implemented with a comparison circuit 209a and a buffer circuit 209b.

The comparison circuit 209a compares the data transmitted from the reference sample / hold 207a with the data transmitted from the signal sample / hold 207b, and compares the comparison signal VCOM according to the difference in the voltage level of the compared data. Will occur). The comparison signal VCOM according to the result of comparison is transmitted to the buffer circuit 209b. The buffer circuit 209b buffers the comparison signal VCOM and transmits it to the internal circuit which is continued or outputs through an output terminal.

FIG. 3 is a diagram illustrating unit pixels of the pixel array illustrated in FIG. 2. Each unit pixel consists of four MOS transistors and one photodiode. The four transistors include a transfer transistor M1 for transporting the photocharge generated in the photodiode to the sensing node, a reset transistor M2 for discharging the charge stored in the sensing node for the next signal detection, and a source. The drive transistor M3 serves as a follower, and the select transistor M4 enables addressing through switching.

The reset transistor M2 is turned on by the reset signal of the "high" level (ie, Vdd level) applied from the row decoder. The voltage at the source terminal N1 of the reset transistor M2 becomes (Vdd-Vt). The source terminal N2 of the drive transistor M3 is (Vdd-2Vt).

FIG. 4 is a diagram for explaining timing of main signals and terminals related to driving of the CMOS image sensor of the present invention and holding of data accordingly. FIG.

In FIG. 4, (a) shows control signals generated in the column select shift register 205, and (b) shows the timing of the reset signal reset applied to the reset transistor M2 and the holding of the reference data accordingly. It is a figure for demonstrating. (C) is a diagram for explaining the timing of the transmission signal TX applied to the transfer transistor M1 and the holding of the signal data, and (d) is a timing diagram of the data transmission line DIO of FIG. to be.

2 to 4, the operation of the CMOS image sensor of the present invention is described as follows.

Assume that column 1 is selected in the first column selection section.

The reset signal reset becomes "high" in the reset section, i.e., the section in which the control signal col1 becomes "high." The reference data RD is then held with the reference sample / hold 207a. Subsequently, the transmission signal TX becomes "high" in the signal holding section, that is, the section in which the control signal col2 becomes "high". Then, the signal data (SD) is held. The held reference data RD and signal data SD are transmitted to the output buffer unit 209.

Then, the reference data RD1 and the signal data SD1 of the column 1 transmitted to the output buffer unit 209 are compared with each other, and the difference between the voltage levels of the reference data RD1 and the signal data SD1 is a buffer circuit. 209b is buffered and output.

Subsequently, when column 2 is selected in the second column selection section, the control signal col3 and the control signal col4 sequentially become a "high" level. The reference data RD2 and the signal data SD2 of the column 2 are compared and output in the same manner as in the column 1.

Although the present invention has been described with reference to one embodiment shown in the drawings, this is merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. . Therefore, the true technical protection scope of the present invention will be defined by the appended claims technical spirit.

As described above, with the CMOS image sensor of the present invention, the layout area is significantly reduced by the plurality of columns sharing a buffer amplifier. And accordingly, the area of the light receiving portion in each pixel can be increased.

Claims (3)

delete CMOS image sensor, A pixel array including a plurality of pixels arranged in rows and columns, the plurality of data transmission lines respectively transmitting data pairs generated from the pixels arranged in each column; A plurality of sample / hold pairs for receiving and holding the data pairs output from each of the data transmission lines, and for transmitting the held data pairs in response to predetermined control signals input from the outside; And A buffer amplifier configured to compare signals of data pairs transmitted from the sample / hold pairs, amplify and output the compared result, The buffer amplifier is shared by the plurality of sample / hold pairs, The data pair includes reference data output in a reset mode and signal data output in a signal mode. Each of the sample / hold pairs A reference sample / hold for selecting and holding the reference data; And And a signal sample / hold for holding and selecting the signal data. The method of claim 2, The buffer amplification unit And a comparison circuit for comparing data transmitted from said reference sample / hold with data transmitted from said signal sample / hold.