KR100358147B1 - Method for forming ferroelectric capacitor - Google Patents

Abstract

The present invention relates to a ferroelectric capacitor capable of improving electrical characteristics and electrode capacity of a BLT ferroelectric capacitor by forming a non-oriented ferroelectric body as a seed layer and forming a BLT ferroelectric thin film thereon, A method of manufacturing a ferroelectric capacitor according to the present invention includes: a first step of forming a lower electrode on a substrate on which a predetermined process is completed; A second step of forming a ferroelectric seed layer having no orientation on the lower electrode; A third step of forming a ferroelectric thin film of Bi _x La _y Ti ₃ O ₁₂ (x is 3.2 to 3.5, y is 0.4 to 0.9) on the ferroelectric seed layer; And a fourth step of forming an upper electrode on the Bi _x La _y Ti ₃ O ₁₂ ferroelectric thin film.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a method for forming a ferroelectric capacitor,

The present invention relates to a ferroelectric capacitor manufacturing method, and more particularly, to a BLT ferroelectric capacitor manufacturing method.

As the degree of integration increases in a semiconductor device, a capacitor having a high electrode capacity in a narrow space and having little influence of a leakage current has been required.

SBT (Sr _x Bi _y Ti ₃ O ₁₂ where x is 0.7 to 0.9 and y is 2.2 to 2.6) or SBTN (Sr _x Bi _y (Ta _i Nb _j ) ₂ O ₉ where x is 0.7 to 0.9, y (2.2 to 2.6, i is 0.6 to 0.9, and j is 0.1 to 0.4)), which is a ferroelectric thin film of Bi-layered perovskite. Further, Pt or the like having excellent electrical characteristics has been used as an electrode material.

On the other hand, the SBT (N) ferroelectric has good thin film fatigue characteristics and polarization saturation characteristics, but since the crystal structure is complicated, it is difficult to obtain a film having a flat surface and a problem of high crystallization temperature occurs.

In order to solve this problem, BLT (Bi _x La _y Ti ₃ O ₁₂ (x is 3.2 to 3.5, y is 0.4 to 0.9) which is higher in relative polarization value than SBT (N) and lower in crystallization temperature is relatively reliable. Ferroelectric thin films are being actively studied.

Generally, the ferroelectric of the bismuth layered structure has a larger polarization value in the a-axis or b-axis direction than the c-axis.

However, in the case of BLT, the polarization value in the a-axis or b-axis direction is very large at 50 μC / cm 2 while the polarization value in the c-axis direction is very small at 4 μC / ㎠ (LANDOLT-BRNSTEIN Numerical Data and Functional Relationships in Science and Technology, New Series Group VII, Ferroelectrics and Related Substances, Subvolume a: Oxides edited by T. Mitsui S. Nomura (Springer-Verlag Berlin Heidelberg New York 1981), pp. 237).

Therefore, in order to obtain a BLT ferroelectric thin film having an increased polarization, the c-axis orientation should be suppressed and the orientation of the a-axis or b-axis should be improved.

However, the BLT ferroelectric thin film is generally formed in a c-axis orientation with low surface energy after the crystallization thermal process, irrespective of the deposition method, for example, sputtering, resulting in a problem that the polarization value is lowered.

In addition, the BLT ferroelectric thin film has a crystal structure that is monoclinic or pseudo-orthorhombic, that is, a = 5.411A, b = 5.448A, c = 32.38A, while SBT (N) ferroelectric The thin film has a crystal structure of Orthorhombic, that is, a = 5.512 ANGSTROM, b = 5.512 ANGSTROM and c = 25.00 ANGSTROM ("Electrical Properties of (Bi, La) ₄ Ti ₃ O ₁₂ Based Films Prepared by RF Sputtering" , N. Ichinose and M. Nomura, Jpn.J.Eff.Phys. 35 (1996) 4960).

Disclosure of Invention Technical Problem [8] Accordingly, the present invention has been made keeping in mind the above problems occurring in the prior art, and an object of the present invention is to provide a BLT ferroelectric thin film having a non- And a method of manufacturing a ferroelectric capacitor capable of improving the electrical characteristics and the electrode capacity of the ferroelectric capacitor.

FIGS. 1A to 1E are cross-sectional views illustrating a ferroelectric capacitor manufacturing process according to an embodiment of the present invention;

FIGS. 2A to 2F are cross-sectional views illustrating a ferroelectric capacitor manufacturing process according to another embodiment of the present invention;

Fig. 3 is an X-ray diffraction pattern showing the difference in orientation between the crystallized BLT ferroelectric thin film and the SBT ferroelectric thin film.

Description of the Related Art [0002]

10, 30: substrate

11, 31: Source / drain junction

12, 32: field oxide film

13, 33: gate insulating film

14, 34: gate electrode

15, 35: a first interlayer insulating film

16, 36: bit line

17, 37: a second interlayer insulating film

18: Polysilicon plug

19: silicide layer

20: diffusion barrier

21, 40: lower electrode

22, 41: ferroelectric seed layer

23, 42: BLT ferroelectric thin film

24, 43: upper electrode

25: Hydrogen diffusion barrier

26: Planarization insulating film

27, 47: metal wiring layer

38: Pasivation layer

39: Adhesive layer

44: a third interlayer insulating film

45: First diffusion preventing film

46: second diffusion barrier film

According to an aspect of the present invention, there is provided a method of fabricating a ferroelectric capacitor, including: forming a lower electrode on a substrate on which a predetermined process is completed; A second step of forming a ferroelectric seed layer having no orientation on the lower electrode; A third step of forming a ferroelectric thin film of Bi _x La _y Ti ₃ O ₁₂ (x is 3.2 to 3.5, y is 0.4 to 0.9) on the ferroelectric seed layer; And a fourth step of forming an upper electrode on the Bi _x La _y Ti ₃ O ₁₂ ferroelectric thin film.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention.

1A to 1E are cross-sectional views illustrating a ferroelectric capacitor manufacturing process according to an embodiment of the present invention.

2A to 2F are cross-sectional views illustrating a capacitor manufacturing process according to another embodiment of the present invention.

3 is an X-ray diffraction pattern showing the difference in orientation between the crystallized BLT ferroelectric thin film and the SBT ferroelectric thin film.

Before describing the embodiments, Fig. 3, which provides the technical idea of the present invention, will be described.

Referring to FIG. 3, the orientation of each thin film was confirmed as the intensity (A, B) by X-ray diffraction of the BLT and SBT ferroelectric thin films on the Pt lower layer after the crystallization heat treatment. Here, the vertical axis represents an arbitrary unit in terms of the relative number of times in X-ray diffraction as an intensity, and the horizontal axis represents an angle (2 Theta) measured along an arbitrary crystal plane.

Specifically, in the case of the BLT (A) is, A _1, A _2, A _3, A _4, A _6, and a c-axis orientation, such as A ₈ dominant, non-oriented (Random orientation), as shown in A ₄ and A ₆ .

On the other hand, in the case of the SBT system (B), it can be seen that the a-axis or no-orientation is dominant like B ₁ to B ₅ . That is, unlike BLT (A), the SBT system (B) is generally not affected by the deposition method and crystallizes with no orientation.

Therefore, when a ferroelectric capacitor is manufactured, a SBT ferroelectric thin film is deposited and crystallized to a thickness of 200 Å or less as a seed layer, and then a BLT ferroelectric thin film is deposited and crystallized to form a SBT ferroelectric having a crystal structure similar to that of BLT, The BLT ferroelectric thin film is crystallized while having no orientation and thus has a higher polarization value than a single BLT ferroelectric thin film having c-axis orientation.

Hereinafter, embodiments of the present invention will be described with reference to Figs. 1A to 1E.

First, FIG. 1A shows a cross-sectional view in which a predetermined insulating structure and a lower layer of a conductive structure are formed on a semiconductor substrate 10.

Hereinafter, the lower layer forming process will be described in detail.

A source / drain junction 11, a field oxide film 12, a gate oxide film 13, and a gate electrode 14 are formed on a substrate 10. Then, a first interlayer insulating film 15 and a second interlayer insulating film 17 for separating the gate electrode 14 and the bit line 16 are formed.

Subsequently, after the first and second interlayer insulating films 15 and 17 are selectively etched to form a first contact hole (not shown), a recessed polysilicon plug 18 and a silicide layer 19 are formed, And the diffusion barrier layer 20 are formed in a predetermined region in the first contact hole (not shown). The second interlayer insulating film 17 may be an oxide film formed of HTO or Boro Phospho Silicate Glass (BPSG), and the silicide layer 19 may be formed of conventional silicon (Si) and titanium (Ti) A silicide is used by thermal reaction of cobalt (Co). The diffusion barrier layer 20 may be formed of TiN, TiAlN or TiSiN.

Subsequently, as shown in FIG. 1B, a SBT-based ferroelectric seed layer 22 of SBT or SBTN having a lower electrode 21 and a non-oriented property is formed to a thickness of 50 Å to 200 Å on the entire surface of the resultant, The seed layer 22 is crystallized without orientation.

Specifically, the lower electrode 21 is formed by stacking a noble metal and a conductive oxide of Pt / IrO ₂ / Ir or IrO ₂ / Ir. The ferroelectric seed layer 22 is deposited by a sol- (Metal Organic Chemical Vapor Deposition (MOCVD) or Atomic Layer Deposition (ALD)), which is a method of forming a metal oxide layer, In the case of using the sol-gel method, MOD or LSMCD, an organic matter may remain in the ferroelectric seed layer 22 because a liquid source is applied and heat-treated. Therefore, after the deposition, the organic material is removed by baking at a temperature of 350 ° C to 500 ° C for 2 to 6 minutes.

The ferroelectric seed layer 22 is maintained at a temperature of 700 ° C. to 800 ° C. and is subjected to a rapid thermal annealing process for 1 second to 60 seconds in an atmosphere of oxygen (O ₂ ), nitrogen (N ₂ ), or argon (Ar) Annealing (RTA).

Next, as shown in FIG. 1C, a BLT ferroelectric thin film 23 and a Pt-based upper electrode 24 having a thickness of 300 ANGSTROM to 700 ANGSTROM are formed on the entire surface of the ferroelectric seed layer 22.

At this time, a SBT-type second ferroelectric seed layer (not shown) may be further formed on the upper electrode 24 to increase the polarization value of the non-oriented multi-layer dielectric thin film.

Specifically, the BLT ferroelectric thin film 23 is deposited by the same method as the ferroelectric seed layer 22 described above. After the BLT ferroelectric thin film 23 is deposited, crystallization heat treatment is performed, or the upper electrode 24 ) Or after the formation of the second ferroelectric seed layer (not shown), the crystallization heat treatment may be performed by first performing the heat treatment on the ferroelectric seed layer 22 described above, And furnace annealing in an atmosphere of nitrogen or argon for 20 minutes to 4 hours.

Next, as shown in FIG. 1 (d), the upper electrode 24 and the BLT ferroelectric thin film 23 are etched to form a pattern, and a recovery heat treatment is performed to determine the residual polarization value of the ferroelectric material deteriorated by the plasma impact during etching. Restoration.

Specifically, the recovery heat treatment is performed by furnace annealing at a temperature of 600 to 700 ° C for 10 to 30 minutes in an atmosphere of nitrogen or argon.

However, in the etching process, the lower electrode 21 may be performed first, or the upper electrode 24 may be performed first.

Next, as shown in FIG. 1E, a hydrogen diffusion barrier film 25 such as Al ₂ O ₃ and a planarization insulating film 26 such as a silicon oxide film or SOG (Spin On Glass) are sequentially formed on the entire surface of the resultant structure. Thereafter, a pattern is formed by etching the hydrogen diffusion preventing film 25 and the planarization insulating film 26 to form a second contact hole (not shown) for forming a metal pattern with the upper electrode 24, A heat treatment is performed to restore the characteristics of the ferroelectric material, and a metal wiring layer 27 is formed by forming a pattern after depositing and etching a TiN antireflection film (arc-TiN) / Al / TiN or the like.

Here, the recovery heat treatment is performed by furnace annealing at a temperature of 600 ° C to 700 ° C for 10 minutes to 30 minutes in an atmosphere of nitrogen or argon.

2A to 2F are cross-sectional views illustrating a process for fabricating a capacitor according to another embodiment of the present invention, which shows a NPP (Non Poly Plug) structure without a plug at a lower portion of a lower electrode. Here, the same processes as those in Figs. 1A to 1E will be described with reference to the first embodiment described above.

2A shows a cross-sectional view in which a predetermined insulating structure and a lower layer of a conductive structure are formed on a semiconductor substrate 30.

The lower layer is formed with a source / drain junction 31, a field oxide film 32, a gate oxide film 33 and a gate electrode 34 formed on a substrate 30. The gate electrode 34 and the bit line 36 And a second interlayer insulating film 37 is formed on the first interlayer insulating film 35. The second interlayer insulating film 37 is formed on the first interlayer insulating film 35. [ The passivation layer 38 formed by HTO is formed on the second interlayer insulating film 37. Next,

Next, the said passivation layer (38) over the adhesive layer 39 and the lower electrode 40 and the non-SBT or SBTN SBT ferroelectric seed layer 41 having the orientation, such as SiO ₂ in as shown in Figure 2b To 50 Å to 200 Å, and then heat treatment is performed to crystallize the ferroelectric seed layer 41 in a non-oriented manner.

Specifically, the lower electrode 40 is made of Pt or Pt, and the ferroelectric seed layer 41 is deposited in the same manner as in the first embodiment.

The ferroelectric seed layer 41 is crystallized by rapid thermal annealing (RTA) in an oxygen atmosphere for 1 second to 60 seconds while maintaining the temperature at 700 to 800 ° C.

Next, as shown in FIG. 2C, a BLT ferroelectric thin film 42 and a Pt-based upper electrode 43 having a thickness of 300 Å to 700 Å are formed on the entire surface of the ferroelectric seed layer 41.

At this time, a SBT-based second ferroelectric seed layer (not shown) may be further formed on the upper electrode 43 to increase the polarization value of the non-oriented multi-layer dielectric thin film.

Specifically, the BLT ferroelectric thin film 42 is deposited by the same method as the ferroelectric seed layer 41 described above. After the BLT ferroelectric thin film 42 is deposited, crystallization heat treatment is performed, or the upper electrode 43 ) Or after the formation of the second ferroelectric seed layer (not shown), the crystallization heat treatment may be performed by first subjecting the ferrocyse seed layer 41 to heat treatment, Lt; 0 > C to 850 < 0 > C and furnace annealing in an oxygen atmosphere for 20 minutes to 4 hours.

Next, as shown in FIG. 2D, a pattern is formed after etching the upper electrode 43 and the BLT ferroelectric thin film 42, and then a recovery heat treatment is performed to determine the residual polarization value of the ferroelectric material deteriorated by the plasma impact at the time of etching Restoration.

Specifically, the recovery heat treatment is performed by furnace annealing in an oxygen atmosphere for 10 to 30 minutes while maintaining a temperature of 600 to 800 ° C.

However, in the etching process, the lower electrode 40 may be performed first, or the upper electrode 43 may be performed first.

Next, as shown in FIG. 2E, a third interlayer insulating film 44 is formed on the entire surface of the resultant structure, and then selectively patterned to form a hole (not shown) for the capacitor contact. Next, a first diffusion preventing film 45 is formed on the capacitor using TiN or the like in order to prevent deterioration of the capacitor characteristics occurring at the capacitor contact portion in forming the metal wiring and the diffusion preventing film after the recovery heat treatment is performed under the same conditions as described above. It is formed to remain only in the contact area. Here, the third interlayer insulating film 44 is made of SiO ₂ , BPSG (Boro PhosphoSilicate Glass), BPSG / SiO ₂ or the like.

Next, the source / drain junction 31 on the semiconductor substrate 30 is selectively patterned to form a second diffusion barrier film 46 such as TiN / Ti, as shown in FIG. 2F. Next, the second diffusion prevention film 46 and the first diffusion prevention film 45 are plugged using a metal wiring layer 47 such as Al, and then the second diffusion prevention film 46 and the metal wiring layer 47 are patterned do.

As described above, the method of manufacturing a ferroelectric capacitor of the present invention is characterized in that a non-oriented SBT ferroelectric seed layer is formed in a lower portion of a BLT ferroelectric thin film at a predetermined thickness to induce a non-oriented property of the BLT ferroelectric thin film, The electrode capacity can be greatly improved.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, it will be understood by those of ordinary skill in the art that various embodiments are possible within the scope of the technical idea of the present invention.

In the ferroelectric capacitor manufacturing method, deterioration of characteristics of a ferroelectric can be minimized, and electrical characteristics and electrode capacity can be improved.

Claims (14)

A method of manufacturing a ferroelectric capacitor, A first step of forming a lower electrode on a substrate on which a predetermined process is completed; A second step of forming a ferroelectric seed layer having no orientation on the lower electrode; A third step of forming a ferroelectric thin film of Bi _x La _y Ti ₃ O ₁₂ (x is 3.2 to 3.5, y is 0.4 to 0.9) on the ferroelectric seed layer; And A fourth step of forming an upper electrode on the Bi _x La _y Ti ₃ O ₁₂ ferroelectric thin film, And forming a ferroelectric capacitor on the ferroelectric capacitor. The method according to claim 1, After the third step, And forming a ferroelectric seed layer having no orientation on the Bi _x La _y Ti ₃ O ₁₂ ferroelectric thin film. 3. The method according to claim 1 or 2, The ferroelectric seed layer Sr _x Bi _y Ti ₃ O ₁₂ (x is 0.7 to 0.9, y is 2.2 to 2.6) or Sr _x Bi _y (Ta _i Nb _j ) ₂ O ₉ (x is 0.7 to 0.9, y is 2.2 to 2.6, 0.6 to 0.9, and j is 0.1 to 0.4) is used as the ferroelectric capacitor. The method of claim 3, The ferroelectric seed layer Lt; RTI ID = 0.0 > 200A. ≪ / RTI > 3. The method according to claim 1 or 2, The Bi _x La _y Ti ₃ O ₁₂ ferroelectric thin film and the ferroelectric seed layer, A sol-gel method, an MOD, an LSMCD, a sputtering method, a metal organic chemical vapor deposition method, or an atomic layer deposition method. 6. The method of claim 5, When the sol-gel method, MOD or LSMCD is used, Wherein the ferroelectric capacitor is baked at 350 to 500 ° C. The method according to claim 1, In the Bi _x La _y Ti ₃ O ₁₂ ferroelectric thin film, Wherein the ferroelectric capacitor has a thickness of 300 to 700 angstroms. The method according to claim 1, The upper electrode includes: Pt system is used as the ferroelectric capacitor. The method according to claim 1, In the second step, After the formation of the ferroelectric seed layer, rapid thermal annealing is performed at a temperature of 700 ° C to 800 ° C and an atmosphere of oxygen, nitrogen or argon for 1 second to 60 seconds. The method according to claim 1, After the third step, Further comprising performing a heat treatment to crystallize the Bi _x La _y Ti ₃ O ₁₂ ferroelectric thin film. The method according to claim 1, After the fourth step, And crystallizing the Bi _x La _y Ti ₃ O ₁₂ ferroelectric thin film. The method according to claim 10 or 11, In the crystallization heat treatment, Rapid thermal annealing at a temperature of 700 ° C to 800 ° C and an atmosphere of either oxygen, nitrogen, or argon for 1 second to 60 seconds; And Roasting at a temperature of 600 ° C to 700 ° C and an atmosphere of nitrogen or argon for 20 minutes to 4 hours And forming a ferroelectric capacitor on the ferroelectric capacitor. The method according to claim 1, After the fourth step, Selectively etching the upper electrode and the Bi _x La _y Ti ₃ O ₁₂ ferroelectric thin film to form a pattern; And Recovery heat treatment at a temperature of 600 ° C to 700 ° C and an atmosphere of nitrogen or argon for 10 minutes to 30 minutes And forming a ferroelectric capacitor on the ferroelectric capacitor. The method according to claim 1, The lower electrode may include: Pt system / IrO ₂ / Ir or IrO ₂ / Ir is used as the ferroelectric capacitor.