KR100357630B1 - Communication device between host board and target boards - Google Patents

Abstract

An apparatus for communication between the host board and the target boards in a communication system consisting of a host board and a target board is disclosed. The present invention proposes a communication device requiring a high speed data transmission and a small number of edge pins by connecting a host board having a control unit and a target board having a control unit with each other through a differential line cable or a backplane. . Signals transmitted and received between the host board and the target boards include mode signals, address signals, and data signals for operation mode classification. When the host board reads data of a corresponding board among the target boards, a transmission frame transmitted from the target board to the host board includes a mode cycle, an address cycle, a turnaround cycle, a preparation cycle, a data cycle, and a turnaround cycle. Has the format of. When the host board wants to write data to a corresponding board among the target boards, a transmission frame transmitted from the host board to the target board is a mode cycle, an address cycle, a data cycle, a turn around cycle, a preparation cycle, and a turn around. It has the format of a cycle.

Description

Communication device between host board and target board {COMMUNICATION DEVICE BETWEEN HOST BOARD AND TARGET BOARDS}

The present invention relates to an apparatus for communication between the host board and the target board in a communication system consisting of a host board and a target board.

In general, a communication system such as an International Mobile Telecommunication (IMT-2000) system is composed of a plurality of boards. The plurality of boards may be divided into one host board and target boards. Typically, the host board is provided with a control unit such as a central processing unit (CPU), while the target boards are not provided with a control unit.

In such a configuration, that is, communication between the host board including the control unit and the target boards without the control unit, high-speed data transmission is naturally required. It may also be useful if fewer edge pins are used to connect the host board and the target board.

Accordingly, an object of the present invention is to provide a communication device that enables high-speed data transmission between a host board and a target board in a communication system.

Another object of the present invention is to provide an apparatus for allowing a host board including a control unit and a target board without a control unit to be connected through a small number of edge pins in a communication system.

It is still another object of the present invention to provide an apparatus in which a host board having a control unit and a target board having no control unit are connected through a small number of edge pins in a communication system, thereby enabling high-speed data transmission.

In order to achieve the above object, the present invention provides a high speed data transmission and a small number of edge pins by connecting a host board having a control unit and a target board having no control unit with a differential line cable or a backplane. Propose a communication device. Signals transmitted and received between the host board and the target boards include mode signals, address signals, and data signals for operation mode classification. When the host board reads data of a corresponding board among the target boards, a transmission frame transmitted from the target board to the host board includes a mode cycle, an address cycle, a turnaround cycle, a preparation cycle, a data cycle, and a turnaround cycle. Has the format of. When the host board attempts to write data to a corresponding board among the target boards, a transmission frame transmitted from the host board to the target board includes a mode cycle, an address cycle, a data cycle, a turn around cycle, a preparation cycle, and a turn around. It has the format of a cycle.

1 is a view showing the configuration of a communication device between a host board and a target board according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a component for terminating line signals in a host board and a target board according to an embodiment of the present invention. FIG.

3 is a diagram illustrating target line interface chip signals used in a transceiver in a target board shown in FIG.

4 illustrates target FPGA interface chip signals used in the FPGA in the target board shown in FIG.

5 is a view showing a connection between a host board and a target board according to an embodiment of the present invention.

6 is a diagram illustrating inter-board operation timing according to an embodiment of the present invention.

7 shows a lead frame according to an embodiment of the invention.

8 is a view showing a light frame according to an embodiment of the present invention.

9 illustrates an address cycle according to an embodiment of the present invention.

10A illustrates the operation timing of 16-bit data access in accordance with one embodiment of the present invention.

10B illustrates operation timing of 8-bit data access according to another embodiment of the present invention.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same reference numerals are used as much as possible even if displayed on different drawings. Also, in the following description, many specific details such as components of specific circuits are shown, which are provided to help a more general understanding of the present invention, and the present invention may be practiced without these specific details. It will be self-evident to those of ordinary knowledge in Esau. In the following description of the present invention, if it is determined that detailed descriptions of related known functions or configurations may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. Terms to be described later are defined in consideration of functions in the present invention, which may vary according to the intention or custom of the user or chip designer, and the definitions should be made based on the contents throughout the present specification.

1 is a block diagram illustrating a communication device between a host board and a target board according to an exemplary embodiment of the present invention.

Referring to FIG. 1, the host board 100 includes a microprocessor 110 as a controller, a field programmable gate array (FPGA) 120, a driver 130, and a transceiver 140. The target board 200 includes a receiver 210, a transceiver 220, an FPGA 230, and function modules 240.

The microprocessor 110 and the FPGA 120 of the host board 100 are connected through a low voltage transistor transistor logic (LVTTL) central processing unit bus (CPU bus). The CPU bus may vary depending on the type of the microprocessor 110. The FPGA 120 and the transceiver 140 and the FPGA 12 and the driver 130 are connected through an LVTTL communication device (CD) bus. The driver 130 of the host board 100 and the receiver 210 of the target board 200 are connected through a differential line cable or a backplane (hereinafter, referred to as a “differential line cable”). In addition, the transceiver 140 of the host board 100 and the transceiver 220 of the target board 200 are connected through a differential line cable. An edge pin for connecting the differential line cable is provided on the host board 100 and the target board 200. The difference line follows the line interface specification. Receiver 210 and FPGA 230 and transceiver 220 and FPGA 230 of the target board 200 are connected through an LVTTL CD bus. The FPGA 230 and the function modules 240 of the target board 200 are connected through an LVTTL decoded bus. The decryption bus is a bus for accessing the function modules 240 in the target board 200. Here, although one host board 100 and one target board 200 are illustrated as being connected, it should be noted that a plurality of target boards 200 may be connected to one host board 100. In addition, the host board 100 preferably has a redundant structure so that the host board 100 can operate normally even under a power failure or failure.

In this way, the host board 100 and the target board 200 are connected via differential line cables, and these boards transmit and receive so-called LVTTL CD bus signals. The LVTTL CD bus signal includes a bus clock signal CLK, a frame sync signal FS, and an address / data signal AD. Since the LVTTL CD bus signal is transmitted and received through a differential line cable, it may be defined as a bus low voltage differential signal (LVDS). This LVDS is a signal with a level of 3.3 / 5.0 volts. That is, the transceivers in the host board 100 and the target board 200 transmit and receive signals of 3/3 / 5.0 volts. The bus clock signal and the frame synchronization signal are signals supplied from the driver 130 of the host board 100 to the receiver 210 of the target board 200. The bus clock signal is always supplied, and the frame synchronization signal appears every time access is started and maintains one clock. For example, the address / data signal is transmitted and received through four lines, and is a signal that is actually transmitted / received including information such as an access mode, an address, data, and ready. All signal buses LVDS on the bus are inputted and outputted at the rising edge of the bus clock signal CLK. Transmission and reception control of all signal buses LVDS on the bus is performed only on the host board 100 side. This is because the microprocessor 110 is provided as a controller in the host board 100, but the controller is not provided in the target board 200.

The bus clock signal CLK, the frame synchronizing signal FS, and the address / data signal AD [3: 0] are TTL (Transistor Transistor Logic) signals, and the signals are defined in Table 1 below.

Signal Direction Full Name CLK Host to target Bus clock FS Host to target Frame Synchronization AD [3: 0] Both way Address and Data

FIG. 2 is a diagram illustrating a component for terminating line signals in a host board and a target board according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the host board 100 includes transceivers 141 and 142 having a redundant structure. The transceivers 141 and 142 of the redundant structure are connected to the transceivers 221 to 223 of the target board 200 through a differential line cable or a backplane. In this case, the resistor Rt is positioned at the end of the differential line cable or the backplane. The resistor Rt is a resistor for terminating the LVDS differential line of the minus signal and the plus signal. The resistance value of the resistor Rt is determined to match the impedance of the LVDS line.

FIG. 3 is a diagram illustrating target line interface chip signals used in the receiver 210 and the transceiver 220 in the target board 200 illustrated in FIG. 1.

In FIG. 3, reference numerals 211 and 212 denote the configuration of the receiver 210 of FIG. 1, and reference numerals 221 to 224 denote the configuration of the transceiver 220 of FIG. This receiver 210 and transceiver 220 can be implemented using the DS92LV010ATM line transceiver.

The receiver 211 receives the bus clock LVDS signals CD_CLK_P and CD_CLK_N provided through the differential line cable from the driver 130 of the host board 100 and outputs the receiver bus clock signal CD_CLK. The receiver 212 receives the frame sync LVDS signals CD_FS_P and CD_FS_N provided from the driver 130 of the host board 100 through the difference line cable, and outputs the receiver frame sync signal CD_FS. The receiver bus clock signal CD_CLK and the receiver frame synchronization signal CD_FS are applied to the FPGA 230 of the target board 200.

The transceiver 221 transmits / receives the address / data line 0 LVDS signals CD_ADO_P and CD_ADO_N from the transceiver 140 of the host board 100. The transceiver 221 inputs a CD_ADDO driver signal from the FPGA 230 of the target board 200 and outputs a CD_ADR0 receiver signal to the FPGA 230. The transceiver 222 transmits and receives an address / data line 1 LVDS signal CD_AD1_P and CD_AD1_N from the transceiver 140 of the host board 100. The transceiver 221 inputs a CD_ADD1 driver signal from the FPGA 230 of the target board 200 and outputs a CD_ADR1 receiver signal to the FPGA 230. The transceiver 223 transmits / receives the address / data line 2 LVDS signals CD_AD2_P and CD_AD2_N from the transceiver 140 of the host board 100. The transceiver 223 inputs a CD_ADD2 driver signal from the FPGA 230 of the target board 200 and outputs a CD_ADR2 receiver signal to the FPGA 230. The transceiver 224 transmits / receives the address / data line 3 LVDS signals CD_AD3_P and CD_AD3_N from the transceiver 140 of the host board 100. The transceiver 224 inputs a CD_ADD3 driver signal from the FPGA 230 of the target board 200 and outputs a CD_ADR3 receiver signal to the FPGA230. The transceivers 221 to 224 are enabled by the CD_AD driver enable signal CD_ADE applied to each DE terminal to transmit the CD_ADDO to CD_ADD3 driver signals. On the other hand, said transceivers 221-224, so that each terminal RE is connected to the ground terminal, and outputs the received signal when the receiver CD_AD address / data lines LVDS signals. Table 2 below summarizes the target line interface chip signals as shown in FIG. 3.

CD_CLK_P: Bus Clock LVDS positive signalCD_CLK_N: Bus Clock LVDS negative signalCD_FS_P: Frame Synchronization LVDS positive signalCD_FS_N: Frame Synchronization LVDS negative signalCD_CLK: Receiver Single ended Bus Clock SignalCD_FS: Receiver Single ended Frame Sync. SignalCD_AD0_P: Address Data line 0 LVDS positive signalCD_AD0_N: Address Data line 0 LVDS negative signalCD_AD1_P: Address Data line 1 LVDS positive signalCD_AD1_N: Address Data line 1 LVDS negative signalCD_AD2_P: Address Data line 2 LVDS positive signalCD_AD2_N: Address Data line 2 LVDS negative signalCD_AD3_: Address Data line 3 LVDS positive signalCD_AD3_N: Address Data line 3 LVDS negative signalCD_ADD0: CD_AD0 Driver SignalCD_ADD1: CD_AD1 Driver SignalCD_ADD2: CD_AD2 Driver SignalCD_ADD3: CD_AD3 Driver SignalCD_ADR0: CD_AD0 Receiver SignalCD_ADR1: CD_AD1 Receiver SignalCD_ADR2: CD_AD2 Receiver CDCD Receiver Enable Signal

FIG. 4 is a diagram illustrating target FPGA interface chip signals used in the FPGA 230 in the target board shown in FIG. 1.

Referring to FIG. 4, the FPGA 230 inputs a CD_CLK signal and a CD_FS signal from the receiver 210, and also inputs a CD_ADR (3: 0) signal from the transceiver 220. The FPGA 230 outputs a CD_ADD (3: 0) signal and a CD_ADE signal to the transceiver 220. In this case, the CD_AD driver enable signal CD_ADE enables the transceiver 220 when the FPGA 230 in the target board prepares or outputs an address / data line.

The FPGA 230 provides an address signal Addr (0:19) to the function modules 240 (internal devices) 240 inside the target board 200, and transmits and receives data signals Data (0: 7,15) with the function modules 240. . In addition, the FPGA 230 provides a chip select signal / CS (0: n), a data read / write signal / RW, and an output enable signal / OE to the function modules 240.

FIG. 5 is a diagram illustrating a connection between the host board 100 and the target boards 200 according to an exemplary embodiment of the present invention.

Referring to FIG. 5, a connection between a redundant host board Host (A) (B) and a plurality of target boards Target (0) to (n) is shown. For example, up to eight target boards may be connected to one port of the host board. The signals between the host boards are connected on differential line cables or on the backplane. All target boards are also connected on differential line cables or backplanes.

6 is a diagram illustrating inter-board operation timing according to an exemplary embodiment of the present invention.

Referring to FIG. 6, all signals transmitted and received between the host board 100 and the target board 200 are LVDS signal levels according to the present invention. The CD bus clock CLK has a predetermined period (for example, 80 ns to 500 ns), and may be variably determined within the above range. The frame synchronization signal FS LVDS input and the analog / data signal AD (3: 0) LVDS input may have an input delay of 2ns-5ns with respect to the clock CLK. The analog / data signal AD (3: 0) LVDS output may have an output delay of up to 40 ns with respect to the clock CLK.

As described above, a format of a transmission frame for signal transmission and reception between the host board 100 and the target board 200 according to the present invention is divided into a read frame and a write frame. Here, the lead frame is a frame in which the host board 100 reads data of the target board 200, while the write frame is a frame in which the host board 100 writes data to the target board 200. The transmission frame according to the present invention consists of a mode cycle, an address cycle, a data cycle, a turnaround cycle and a ready cycle. The formats of the lead frame and the light frame according to the embodiment of the present invention are shown in FIGS. 8 and 9, respectively.

Read / Write Frame

7 is a view showing a lead frame according to an embodiment of the present invention.

Referring to FIG. 7, the lead frame is a frame when the host board 100 reads data of the target board 200. The lead frame has a mode cycle of 1 clock, an address cycle of 6 clocks, an add cycle of 1 clock, a ready cycle of 1-n clocks, and a clock of 2 clocks / 4 clocks. It consists of a data cycle of Data and a turnaround cycle of one clock. The data cycle consists of two data clocks for 8-bit data access and four data clocks for 16-bit data access. The preparation cycle is determined to have one or more clocks depending on the access speed of the device (function module) in the target board 200.

8 is a view showing a light frame according to an embodiment of the present invention.

Referring to FIG. 8, the write frame is a frame in which the host board 100 writes data to the target board 200. The write frame includes a mode clock of 1 clock, an address cycle of 6 clocks (Addr), a turnaround cycle (TA) of 1 clock, a ready cycle of (1-n) clock, and a clock of 2 clock / 4 clock. It consists of a data cycle (Data) and one clock turnaround cycle (TA). The data cycle consists of two data clocks for 8-bit data access and four data clocks for 16-bit data access. The preparation cycle is determined to have one or more clocks depending on the access speed of the device (function module) in the target board 200.

Mode Cycle

Table 3 below defines the mode cycle according to the present invention.

AD bit Value Access direction 0 0 Host write the data to target device One Host read the data from target device One 0 8 bits data length One 16 bits data length 3: 2 xx Don't care

Referring to <Table 3>, when the AD bit value is "00", it indicates an 8-bit data write mode. When the AD bit value is "01", it indicates that the 8-bit data read mode. When the AD bit value is "10", it indicates that the 16-bit data write mode is used. If the AD bit value is not the above values, it indicates that the reserved mode is reserved. As such, the mode cycle includes write, read, and data length information. This mode cycle is a cycle maintained for one clock at the falling edge of the frame sync signal FS.

Address Cycle

9 is a diagram illustrating an address cycle according to an embodiment of the present invention.

Referring to FIG. 9, the address cycle consists of six clocks following the mode cycle, and has an address range of 16 MBytes. A (0) represents the Least Significant Bit (LSB), and A (23) represents the Most Significant Bit (MSB). The AD (3) signal represents A (23), A (19), A (15), A (11), A (7) and A (3). The AD (2) signal represents A (22), A (18), A (14), A (10), A (6) and A (2). The AD (1) signal represents A (21), A (17), A (13), A (9), A (5) and A (1). The AD (0) signal represents A (20), A (16), A (12), A (8), A (4) and A (0).

Data Cycle

10A illustrates an operation timing of 16 bit data access according to an embodiment of the present invention.

Referring to FIG. 10A, D 15 represents an MSB, and D (0) represents an LSB. The AD (3) signal is composed of D (15), D (11), D (7), and D (3). The AD (2) signal is composed of D (14), D (10), D (6), and D (2). The AD (1) signal is composed of D (13), D (9), D (5), and D (1). The AD (0) signal is composed of D (12), D (8), D (4), and D (0). This 16-bit data access operation is performed when AD (1) = 1X in the mode cycle.

10B is a diagram illustrating operation timing of 8-bit data access according to another embodiment of the present invention.

Referring to FIG. 10B, D (7) represents MSB and D (0) represents LSB. The AD (3) signal is composed of D (7) and D (3). The AD (2) signal is composed of D (6) and D (2). The AD (1) signal is composed of D (5) and D (1). The AD (0) signal consists of D (4) and D (0). This 8-bit data access operation occurs when AD (1) = 0X in the mode cycle.

Turn Around Cycle

Turnaround cycles are cycles that are inserted for one clock each time the driver of the AD (3: 0) signal changes. The turnaround cycle is to prevent damage to the driver chip due to signal collision. The AD line maintains three states during the turn-around cycle. The data during the turnaround cycle is not valid.

Ready Cycle

The preparation cycle may be represented as shown in Table 4 below.

AD (3: 0) Description 0000 Ready state. Operation can be perform next step. 0001 Not ready state. Host must wait more. 1xxx Abort frame. Frame is aborted by target. other RESERVED

The signal for the preparation cycle as shown in Table 4 above is generated at the access target board. The host board 100 waits until AD (3: 0) becomes "0000". If the AD (3: 0) signal is "1xxx", the current access frame is suspended.

As described above, the present invention can be commonly used for all boards that perform high-speed data transfer with a small number of pins between a host board having a control unit (for example, a CPU or a microprocessor) and a target board without the control unit. There is an advantage in that multiple target boards can be connected and used in the backplane.

Meanwhile, in the detailed description of the present invention, specific embodiments have been described, but various modifications are possible without departing from the scope of the present invention. Therefore, the scope of the present invention should not be limited to the described embodiments, but should be determined not only by the scope of the following claims, but also by those equivalent to the scope of the claims.

Claims (7)

A host board having a control unit, It consists of a target board which is not equipped with a control part, And the host board and the target board are connected to each other through a differential line cable, and a transceiver for transmitting and receiving a low voltage differential signal through the cable in the host board and the target board. The communication device of claim 1, wherein the host board has a redundant structure. In the apparatus for communication between a host board having a control unit and target boards having no control unit: The host board; A first edge pin for connecting the target boards through a differential line cable; A driver for transmitting a clock signal and a synchronization signal to the target boards; A first transmitter and receiver for transmitting an address and a data signal to and from said target boards, Each of the target boards; A second edge pin for connecting to the host board through the difference line cable; A receiver for receiving the clock signal and the synchronization signal; And a second transmitter / receiver for transmitting address and data signals to and from the host board. The communication device of claim 3, wherein the signals transmitted and received during the first transmission / reception period of the host board and the second transmission / reception period of the target boards include a mode signal for distinguishing an operation mode, an address signal, and a data signal. The method of claim 3, wherein when the host board reads data of a corresponding board among the target boards, the transmission frame transmitted from the second transceiver to the first transceiver includes a mode cycle, an address cycle, a turnaround cycle, A communication device having a format of a preparation cycle, a data cycle, and a turnaround cycle. The transmission frame of claim 3, wherein the transmission frame transmitted from the first transceiver to the second transceiver when the host board attempts to write data to a corresponding board among the target boards includes a mode cycle, an address cycle, and a data cycle. And a format of a turnaround cycle, a preparation cycle, and a turnaround cycle. The communication device of claim 3, wherein the host board has a redundant structure.