KR100356620B1 - a planarization method for a semiconductor wafer - Google Patents
a planarization method for a semiconductor wafer Download PDFInfo
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- KR100356620B1 KR100356620B1 KR1019990067733A KR19990067733A KR100356620B1 KR 100356620 B1 KR100356620 B1 KR 100356620B1 KR 1019990067733 A KR1019990067733 A KR 1019990067733A KR 19990067733 A KR19990067733 A KR 19990067733A KR 100356620 B1 KR100356620 B1 KR 100356620B1
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- semiconductor substrate
- oxide film
- trench
- cmp
- polishing
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- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000004140 cleaning Methods 0.000 claims abstract description 19
- 239000007788 liquid Substances 0.000 claims abstract description 14
- 238000005498 polishing Methods 0.000 claims abstract description 14
- 229910021642 ultra pure water Inorganic materials 0.000 claims abstract description 4
- 239000012498 ultrapure water Substances 0.000 claims abstract description 4
- 239000000919 ceramic Substances 0.000 claims description 2
- 239000000126 substance Substances 0.000 abstract description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 229910052710 silicon Inorganic materials 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 238000005530 etching Methods 0.000 description 3
- 150000004767 nitrides Chemical class 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000004380 ashing Methods 0.000 description 2
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005406 washing Methods 0.000 description 2
- 239000003082 abrasive agent Substances 0.000 description 1
- 230000002378 acidificating effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000010924 continuous production Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 239000012634 fragment Substances 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000006748 scratching Methods 0.000 description 1
- 230000002393 scratching effect Effects 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02065—Cleaning during device manufacture during, before or after processing of insulating layers the processing being a planarization of insulating layers
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
반도체 기판에 트렌치를 형성하고 산화막을 형성하여 트렌치를 채운 다음, 역 해자 패턴 형성 공정을 통하여 트렌치 상부를 제외한 부분에서 산화막을 제거한다. 다음, 반도체 기판을 HF 등의 세정액 중에 위치시키고 CMP(chemical mechanical polishing)를 진행한다. CMP 후 초순수로 반도체 기판을 세정한다. 이렇게 하면, 연마 부스러기에 의하여 반도체 기판이 긁히는 것을 방지할 수 있고, 연마와 세정을 동시에 진행함으로써 공정을 단순화할 수 있다.A trench is formed in the semiconductor substrate, an oxide film is formed to fill the trench, and an oxide film is removed from portions except the upper portion of the trench through a reverse moat pattern forming process. Next, the semiconductor substrate is placed in a cleaning liquid such as HF and chemical mechanical polishing (CMP) is performed. After CMP, the semiconductor substrate is cleaned with ultrapure water. In this way, the semiconductor substrate can be prevented from being scratched by polishing debris, and the process can be simplified by carrying out polishing and cleaning at the same time.
Description
본 발명은 반도체 기판의 평탄화(chemical mechanical polishing : CMP) 공정에 관한 것으로서, 더 자세하게는 STI(shallow trench isolation) 공정을 사용하여 소자 분리 영역을 형성한 후에 진행하는 평탄화 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a chemical mechanical polishing (CMP) process, and more particularly, to a planarization process that proceeds after forming a device isolation region using a shallow trench isolation (STI) process.
반도체 소자를 제조하는 공정 중에서 소자 분리 영역을 형성하는 방법 중의 하나로 STI 공정이 사용된다. STI 공정은 반도체 기판에 트렌치(trench)를 형성하고 트렌치를 절연 물질로 채우는 방법이다. 이를 좀더 상세하게 설명하면, 규소 기판에 트렌치를 형성하고, 열산화막을 형성한 다음, 상압 화학 기상 증착(APCVD :atmospheric pressure chemical vapor deposition)에 의해 산화막(필드 산화막)을 형성하여 트렌치를 채운다. 이어서, 사진 식각 공정을 통하여 역 해자 패턴(reverse moat pattern)을 형성하고, CMP(chemical mechanical polishing) 공정을 통하여 평탄화함으로써 소자 분리 영역을 형성한다.The STI process is used as one of methods for forming device isolation regions in the process of manufacturing a semiconductor device. The STI process is a method of forming a trench in a semiconductor substrate and filling the trench with an insulating material. In more detail, a trench is formed on a silicon substrate, a thermal oxide film is formed, and an oxide film (field oxide film) is formed by filling an trench by atmospheric pressure chemical vapor deposition (APCVD). Subsequently, a reverse moat pattern is formed through a photolithography process, and a device isolation region is formed by planarization through a chemical mechanical polishing (CMP) process.
이러한 STI 공정 중에서 평탄화를 위한 CMP 공정을 진행하는 도중에 산화막 파편에 의하여 규소 기판의 활성 영역이나 소자 분리 벽으로 작용하는 트렌치 내의 산화막이 깊게 긁힘으로써 소자 불량을 유발하는 경우가 있다.During the SMP process, during the CMP process for planarization, device defects may be caused by deep scratching of an oxide film in a trench acting as an active region or a device isolation wall of a silicon substrate by oxide fragments.
그러면 종래의 기술에 따른 평탄화 공정에 대하여 살펴본다.This will be described with respect to the planarization process according to the prior art.
먼저, 역 해자 패턴을 형성한 후, 이에 사용된 감광막을 애싱(ashing)하여 제거하고, 세정한다First, an inverse moat pattern is formed, and then the photoresist used therein is removed by ashing and washing.
다음, 공기 중에서 CMP 공정을 진행한다. CMP 공정은 연마제(slurry)를 흘려주면서 패드를 마찰시킴으로써 기판 표면을 연마하는 공정이다. 이 과정에서 기계적 마찰에 의하여 떨어져 나온 모난 산화막 덩어리가 규소 기판이나 트렌치 내부의 산화막을 긁어 상처를 입히는 경우가 있다.Next, the CMP process is performed in air. The CMP process is a process of polishing a substrate surface by rubbing a pad while flowing a slurry. In this process, the lump of oxide film separated by mechanical friction may scratch the silicon substrate or the oxide film inside the trench to injure it.
이어서, 화학 약품을 사용하여 CMP 공정에서 발생한 분진과 잔류 연마제 등을 세정하고, 초순수(deionized)로 세척한다.Subsequently, the chemicals are used to clean the dust, residual abrasives, and the like generated in the CMP process, followed by ultra deionized water.
본 발명이 이루고자 하는 기술적 과제는 평탄화 공정에서 규소 기판이 표면이 손상되는 것을 방지하는 것이다.The technical problem to be achieved by the present invention is to prevent the silicon substrate surface from being damaged in the planarization process.
도 1은 종래의 기술에 따라 STI 형성 후 진행하는 평탄화 공정의 흐름도이고,1 is a flowchart of a planarization process proceeding after STI formation according to the prior art,
도 2 내지 도 5는 본 발명의 실시예에 따라 반도체 기판을 평탄화하는 방법을 공정 단계에 따라 순서대로 나타낸 단면도이고,2 to 5 are cross-sectional views sequentially showing a method of planarizing a semiconductor substrate according to an embodiment of the present invention according to the process steps,
도 6은 본 발명의 실시예에 따른 CMP 장비의 개념도이다.6 is a conceptual diagram of CMP equipment according to an embodiment of the present invention.
이러한 과제를 해결하기 위하여 본 발명에서는 반도체 기판을 세정액 중에서 연마한다.In order to solve this problem, in the present invention, the semiconductor substrate is polished in a cleaning liquid.
구체적으로는, 반도체 기판에 역 해자 패턴을 형성하고, 반도체 기판을 세정액 중에 담근 상태에서 연마하고, 반도체 기판을 초순수로 세정한다.Specifically, an inverse moat pattern is formed on the semiconductor substrate, the semiconductor substrate is polished in a state of immersion in the cleaning liquid, and the semiconductor substrate is washed with ultrapure water.
이 때, 연마는 CMP에 의하는 것이 바람직하고, 세정액은 HF 용액일 수 있다.At this time, the polishing is preferably by CMP, the cleaning liquid may be HF solution.
그러면 도면을 참고로 하여 본 발명의 실시예에 따라 반도체 기판을 평탄화하는 방법을 설명한다.Next, a method of planarizing a semiconductor substrate according to an exemplary embodiment of the present invention will be described with reference to the accompanying drawings.
도 1 내지 도 5는 본 발명의 실시예에 따라 반도체 기판에 소자 분리 영역을 형성하는 방법을 공정 단계에 따라 순서대로 나타낸 단면도이다.1 to 5 are cross-sectional views sequentially illustrating a method of forming an isolation region in a semiconductor substrate according to an exemplary embodiment of the present invention, according to the process steps.
먼저, 도 1에 도시한 바와 같이, 규소 기판(1) 위에 화학 기상 증착법을 사용하여 2,000Å 정도의 질화막(2)을 증착하고, 사진 식각 방법을 사용하여 트렌치(T)를 형성한다. 이 때, 식각 방법으로 건식 식각을 사용하며, 트렌치의 깊이는 약 5,000Å 정도가 되도록 형성한다.First, as shown in FIG. 1, a nitride film 2 of about 2,000 mV is deposited on the silicon substrate 1 using chemical vapor deposition, and the trench T is formed using a photolithography method. At this time, dry etching is used as an etching method, and the trench is formed to have a depth of about 5,000 mm 3.
다음, 도 2에 도시한 바와 같이, 산화막(3)을 9,400Å 정도로 증착하고 사진 식각 방법을 사용하여 트렌치(T) 상부를 제외한 산화막(3)을 제거한다. 이어서 산화막(3) 상부에 남아있는 감광막(도시하지 않음)을 애싱하여 제거하고 규소 기판(1)을 세정한다. 이 과정이 역 해자 패턴 형성 공정이다. 이 때, 산화막(3)은 트렌치(T)의 단차로 인하여 트렌치(T) 중앙부에서 오목하고 주변부는 뾰족하게 형성된다.Next, as shown in FIG. 2, the oxide film 3 is deposited to about 9,400 kPa and the oxide film 3 except for the upper portion of the trench T is removed using a photolithography method. Subsequently, the photoresist film (not shown) remaining on the oxide film 3 is removed by ashing and the silicon substrate 1 is cleaned. This process is a reverse moat pattern formation process. At this time, the oxide film 3 is concave in the center portion of the trench T due to the step difference in the trench T, and the periphery is sharply formed.
이어, 도 3에 도시한 바와 같이, 산화막(3)을 평탄화하기 위해 CMP 공정을진행한다. 이 때, CMP는 반도체 기판(1)을 세정액 속에 담근 상태에서 진행한다.Next, as shown in FIG. 3, a CMP process is performed to planarize the oxide film 3. At this time, CMP advances in the state which immersed the semiconductor substrate 1 in the washing | cleaning liquid.
도 6은 본 발명의 실시예에 따른 CMP 장비의 개념도이다.6 is a conceptual diagram of CMP equipment according to an embodiment of the present invention.
본 발명의 실시예에서 사용되는 CMP 장비에는 세정액(40)을 담는 용기(10)가 설치되어 있고, 상하의 연마축(21, 22)은 반도체 기판(1)이 세정액(40) 속에 잠기는 높이에 반도체 기판(1)을 위치시키고 회전하면서 패드(23, 24)를 기판(1)과 마찰시켜 연마한다. 이 때, 세정액(40)으로는 HF 또는 BOE(buffer oxide etchant) 등 산화막(3)에 대하여 적당한 식각률을 가지는 화학 물질을 사용한다. 연마제는 이러한 강산성의 세정액(40) 내에서도 사용가능한 재질 예를 들어 세라믹(ceramic) 등 세정액(40)에 용해되지 않는 물질을 사용하여야 한다.CMP equipment used in the embodiment of the present invention is provided with a container 10 containing the cleaning liquid 40, the upper and lower polishing shafts (21, 22) is a semiconductor at a height that the semiconductor substrate 1 is immersed in the cleaning liquid (40) The pads 23 and 24 are rubbed and polished with the substrate 1 while the substrate 1 is positioned and rotated. At this time, as the cleaning liquid 40, a chemical substance having an appropriate etching rate with respect to the oxide film 3 such as HF or buffer oxide etchant (BOE) is used. The abrasive should be made of a material which can be used even in the strongly acidic cleaning liquid 40, for example, a material that does not dissolve in the cleaning liquid 40, such as ceramic.
이렇게 하면, 세정액(40)이 패드(23, 24)와 반도체 기판(1) 사이의 마찰력을 완화시켜 줌으로써 기계적인 손상을 감소시킴과 동시에 산화막(3)을 식각하여 연마율을 종전과 같은 정도로 유지시키거나 또는 더 향상시킬 수 있다. 또한 CMP 공정 중에 산화막(3)이 깨져 모난 산화막(3) 덩어리가 나오더라도 세정액(40)이 이를 식각하여 원만한 모양으로 만듦으로써 하부 기판(1)이나 산화막(3)에 손상을 가하는 것을 방지할 수 있다.In this way, the cleaning liquid 40 reduces the mechanical damage by alleviating the friction force between the pads 23 and 24 and the semiconductor substrate 1, while simultaneously etching the oxide film 3 to maintain the polishing rate to the same level as before. May be improved or further improved. In addition, even when the oxide film 3 is broken during the CMP process and the lump of the oxide film 3 comes out, the cleaning liquid 40 may be etched into a smooth shape to prevent damage to the lower substrate 1 or the oxide film 3. have.
도 4에 도시한 바와 같이, CMP 공정은 산화막(3)의 위 부분이 제거되어 평탄한 상태가 될 때까지 진행한다.As shown in FIG. 4, the CMP process proceeds until the upper portion of the oxide film 3 is removed to become a flat state.
다음, 연속 공정으로 기판(1)을 회전시키면서 초순수를 분사하는 세정 공정을 통하여 질화막(2) 상부의 불순물 입자를 제거한다.Next, the impurity particles on the upper part of the nitride film 2 are removed through the cleaning process of spraying ultrapure water while rotating the substrate 1 in a continuous process.
다음, 도 5에 도시한 바와 같이, 질화막(2)을 제거하면 산화막(3)으로 채워진 얕은 트렌치(T)가 형성된다.Next, as shown in FIG. 5, when the nitride film 2 is removed, a shallow trench T filled with the oxide film 3 is formed.
이상과 같이, 세정액 속에서 반도체 기판을 연마함으로써 연마 부스러기에 의하여 반도체 기판이 긁히는 것을 방지할 수 있고, 연마와 세정을 동시에 진행함으로써 공정을 단순화할 수 있다.As described above, by polishing the semiconductor substrate in the cleaning liquid, it is possible to prevent the semiconductor substrate from being scratched by the polishing debris, and the process can be simplified by simultaneously performing the polishing and the cleaning.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| KR1019990067733A KR100356620B1 (en) | 1999-12-31 | 1999-12-31 | a planarization method for a semiconductor wafer |
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| KR1019990067733A KR100356620B1 (en) | 1999-12-31 | 1999-12-31 | a planarization method for a semiconductor wafer |
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| KR20010066148A KR20010066148A (en) | 2001-07-11 |
| KR100356620B1 true KR100356620B1 (en) | 2002-10-18 |
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