KR100351000B1 - Semiconductor integrated circuit device - Google Patents

Abstract

Write to a memory cell in which a gate is connected to a word line, one side of a source / drain is connected to a data line, and is connected in series to the address selection MOSFET to form a capacitor having a thin insulating film as a dielectric. In operation, a voltage higher than a normal operating voltage supplied between the data line and the common electrode of the capacitor is applied to the selected capacitor by turning on the address selection MOSFET, and a precharge supplied to the data line during a read operation. A voltage different from the voltage is supplied to the common electrode of the capacitor to sense the potential change of the data line by the sense amplifier. Thus, the structure is used as the programmable ROM.

Description

Semiconductor integrated circuit device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device. For example, a defect remedy technique of a dynamic RAM (random access memory) and an EPROM (erasable & programmable lead / orange memory) aimed at increasing atmospheric storage capacity is provided. The present invention relates to a technology effective for use.

As a defect repair technique in a semiconductor memory device, a defective address is stored using a fuse, and a row or column (word line or data line) containing a defect bit is collectively prepared as a spare row or column (reservation) for redundancy. A word line or a preliminary data line). As described above, for example, Japanese Patent Laid-Open Publication No. 60-89899, Japanese Patent Laid-Open Publication No. 63-79298, and the like, have been made as to a defect repair technique using a fuse.

In the technique of storing a defective address by using a fuse as described above, even if the miniaturization by the latest semiconductor technology is taken into consideration, a pitch having a pitch of about 10 μm and a length of about 20 μm is required. There is a problem. In the present inventors, the device breakdown voltage tends to decrease as a whole as the device becomes smaller, especially in a dynamic memory cell, and as a result, the dielectric film of the capacitor is formed thin so as to obtain a large capacitance value in a small area. The problem of becoming small was considered to be used as a ROM according to the opposite idea. As a result, when the dynamic memory cell is used as a nonvolatile ROM, the area required for 1-bit storage can be greatly reduced to about 1/60 of the case of using the fuse, and the process of the dynamic RAM is left as it is. Since it can be used, it has been found that memory access can be made faster by devising a layout.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device having a ROM which is electrically recordable and highly integrated.

Another object of the present invention is to provide a semiconductor integrated circuit device which enables efficient defect repair of a semiconductor memory circuit.

The above and other objects and novel features of the present invention will become apparent from the description and the accompanying drawings.

In order to achieve the above object, a brief description will be given below. That is, a memory cell comprising an address selection MOSFET in which a gate is connected to a word line and one of the drain / source is connected to a data line, and a capacitor connected in series to such an address selection MOSFET in a thin insulating film as a dielectric material. On the other hand, in the case of a write operation or a program for defect repair, the address selection MOSFET is turned on, and a high voltage is applied between the data line and the common electrode of the capacitor to the selected capacitor, resulting in insulation breakdown. In the read operation, a voltage different from the precharge voltage supplied to the data line is supplied to the common electrode of the capacitor so that the potential change of the data line is sensed by the sense amplifier and used as a programmable ROM.

According to the above means, the memory cells constituting the programmable ROM can be the same size as the dynamic memory cells, and as a result, highly integrated programmable memory having the same size as the dynamic memory cells in the semiconductor integrated circuit device. ROM can be embedded.

FIG. 1 shows a block diagram of the main part of an embodiment of a dynamic random access memory (RAM) in which random defect relief is performed using a programmable read only memory (ROM) according to the present invention. In the present embodiment, the memory array is composed of one, but it is actually divided into a plurality of mats or blocks depending on the storage capacity. Alternatively, the same figure may be understood as functionally showing one memory array and its address selection circuit among a plurality of divided memory arrays.

Although not particularly limited, the dynamic RAM takes an address multiplex method. In this case, the actual dynamic RAM, together with the main block of FIG. 1, is a timing generation circuit that receives a low address strobe signal, a column address strobe signal, and a write enable signal, which are externally regarded as chip select signals, to form various timing signals. , A refresh control circuit, a back bias voltage generation circuit for forming a negative voltage (back bias voltage) to be supplied to a memory array operated by a positive power supply voltage externally, a word of a memory array A high voltage generation circuit for forming a high voltage to be supplied to a line, a plate voltage generation circuit for forming a voltage of a relatively low level to be supplied to a common electrode of a capacitor of a memory array, and the like. However, since the configuration of these individual circuits is not directly related to the present invention, the illustration is omitted in FIG.

The X address buffer X-AB and the Y address buffer Y-AB receive an address signal ADD input in time series from a common address terminal ADD in response to a timing signal generated by a timing generating circuit (not shown). In synchronism with it, it is accepted according to the address strobe signals RAS and CAS supplied from the respective control terminals. The X address signal received by the X address buffer (X-AB) in synchronization with the low address strobe signal RAS is decoded by the X decoder circuit (X-DEC), and the word driver WD is used. One word line selection operation is performed on the plurality of word lines. The Y address signal received as the Y address buffer (Y-AB) in synchronization with the column address strobe signal (CAS) is obtained by the Y decoder circuit (Y-DEC) through a comparison circuit (CMP), a writing circuit (PROGRAM), and a selection circuit described later. The address signal is read out to form a selection signal of l pairs of bit lines from a plurality of data lines.

In the figure, the signal lines are shown extending from the Y decoder circuit Y-DEC to the memory array section, but this is for representing the memory cells designated by the Y address signal, which actually transmits a complementary signal to the memory array section. A data line pair is arranged, and the data line pair is connected to an input / output line (not shown) through a column switch (not shown) in the Y decoder circuit Y-DEC controlled by the Y decode signal. The Y decoder circuit Y-DEC forms a selection signal for selecting the column switch.

Although not particularly limited, in this embodiment, the memory array as the dynamic RAM includes a memory array (M-ARY) as a regular circuit for performing normal data reading and writing, and a first redundant array for performing defect relief in units of data lines. R-ARY1) and a second redundant circuit R-ARY2 that performs defect relief in units of bits. The first redundant circuit R-ARY1 performs defect relief on a data line basis as in the prior art, and stores a defective Y address, a memory circuit for storing the defective Y address, and the storage information and the Y address buffer Y-AB of such a memory circuit. If the bad Y address is selected by the redundant switching circuit R-YDE having a comparison circuit for comparing the Y address signals inputted through the first redundant circuit R- instead of the data line of the memory array M-ARY. Switch to the data line of ARY1). The bad Y address memory circuit is constructed using a fuse as in the prior art.

The sense amplifier SA1 provided in correspondence with a memory array as the dynamic RAM amplifies the microscopic memory information read out from the complementary data line pair of the memory array M-ARY, and loses the memory charges by the read operation. Rewrite the memory cell that you tried to discard. When the shared sense amplifier method is adopted, memory arrays or memory mats are arranged on the left and right sides of the sense amplifier SA1. In this way, the sense amplifier SA1 is a CMOS latch circuit whose operation is controlled by a timing signal such as a sense amplifier of a conventional dynamic RAM in order to perform an amplification operation of a read signal and a rewrite operation to a memory cell. Is used.

In the drawing, the input / output lines included in the Y decoder circuit Y-DEC and the redundancy switching circuit R-YED are extended in the longitudinal direction of the drawing through the column switch in the Y decoder circuit Y-DEC. It is selectively connected to each data line pair of each memory array. These input / output lines are connected to the input / output circuit I / O through a selection circuit SELECT provided for performing random defect relief in units of bits as described below, and receive data or output data.

The word lines WL0, WL1, ... are also connected to a programmable ROM (ROM-ARY) according to the present invention. The programmable ROM writes or programs data by destroying the dielectric film (insulating film) of the capacitor in the dynamic memory cell having the same structure as the memory array of the dynamic RAM. In this programmable ROM, the Y address signal of a defective cell existing on the word line is recorded.

The programmable ROM has a plate electrode that serves as a common electrode of a capacitor, like a memory array of a dynamic RAM. In this case, the plate electrode of the programmable ROM is electrically separated from the memory array of the dynamic RAM to enable programming by breaking the dielectric film of the capacitor. The details are made clearer by the description referring to FIG.

As a result, the memory cell constituting the programmable ROM is connected to the output signal line of the X decoder circuit X-DEC of the dynamic RAM, in other words, the word line of the dynamic RAM. As a result, the address selection circuit of the programmable ROM can be simplified. For example, twelve bit lines or data lines B0 to B11 intersect with word lines of a memory array, and a round circle ( As shown by), the memory cell is installed.

In this configuration, the programmable ROM is simultaneously accessed by the X address selection operation of the dynamic RAM, and the 12 bit lines B0 to B11 output 1 and 0 signals corresponding to the bad Y addresses. These signals are amplified by the sense amplifier SA2 and supplied to one input of the comparison circuit CMP, and compared with the Y address signals output from the Y address buffer Y-AB by the comparison circuit CMP. As the memory cell of the programmable ROM, the same structure as that of the dynamic memory cell is used as described above. However, since the memory operation principle is different from that of the dielectric film of the capacitor, which causes information storage, the sense amplifier (SA2) is used. ) Does not require a rewrite operation such as a dynamic memory cell. Therefore, the sense amplifier SA2 is constituted by a sense amplifier using a differential amplifier circuit shown in FIG. 12 described later.

In the case where the above-described memory cells are used, the programmable ROM can be integrally formed with the memory array of the dynamic RAM. Furthermore, since the programmable ROM memory cell uses the same structure as the memory cell of the memory array of the dynamic RAM, the programmable ROM is programmable. No special manufacturing process is required to form the ROM. Since the address decoder and the word line can be shared with those normally used in the dynamic RAM, the programmable ROM can significantly reduce the occupied area. In the case of repairing two or more defective cells existing on one word line, the number of bit lines and the comparison circuit CMP as described above may be increased in correspondence with the number of the defective cells to be removed.

The programmable ROM stores, in the memory circuit PROGRAM, the Y address in which the defective cell exists in the X address corresponding to the word line when one random defective cell exists in a specific word line as described above. Although not particularly limited, when a defective cell does not exist on the word line, address writing is not performed by the writing circuit PROGRAM, and the Y address is then set to initial data, for example, all zeros. Therefore, even if there is no defect in each word line, the defective cell is considered to be present at an address corresponding to all zero address signals, and a redundant circuit is selected in place of the memory array which performs normal data writing / reading. Disadvantage occurs.

Therefore, by adding a 1-bit flag to the Y address to be stored and writing 1 to this bit, it may be indicated that the stored Y address is a bad address. In this case, the output signal of the comparison circuit CMP becomes valid only when the flag output from the programmable ROM is one. In this way, even if no defect exists in each word line, it is possible to prevent the defective cell from being regarded as being present at an address corresponding to the initial data of the storage element of the programmable ROM.

In the same figure, when a random defective cell exists at the position illustrated by the black circle, a programmable ROM is assigned to a word line (X address) in which the defective cell exists to store the Y address on the word line. By adopting such a configuration, even in a dynamic RAM having a storage capacity of about 16M bits, the Y address of 12 bits is stored for one defective cell. In the case of the dynamic RAM as described above, since the X address is 4K, the programmable ROM is 4K. We need a small memory of 12 = 48K bits.

Assuming that there are up to one defective cell on each of about 4K word lines as described above, a programmable ROM having a storage capacity of up to about 4K bits as described above and a 48-bit storage cell are operated as described above. It can save by the 2nd redundant circuit R-ARY2 used as one comparison circuit and a redundant cell for 1 column. In this case, even if the defective cell is generated in the first redundant circuit R-ARY1 which performs defect relief of the defective data line DEFECT LINE on a data line basis, it can be repaired. By adopting such a bad address designation method, it is possible to greatly simplify the memory circuit for specifying the random defective cells and the comparison circuit for detecting access to the defective cells.

In the selection operation of the X address of the dynamic RAM of the present embodiment, the memory array in which the defect is present and the redundant circuit are simultaneously accessed. If it is determined that the Y address signal is bad, the data line is switched by the selection circuit SELECT. As a result, since the defective cell is switched to the redundant cell by using the selection time of the Y address, the memory access time can be increased. In this way, there is no difference in time between when a defect is present and when it does not exist, so that memory access can be speeded up when performing a defect repair.

The write circuit PROGRAM is a programmable ROM (ROM-ARY), which is effective during a write operation of a defective Y address, in other words, during a program operation, and at least a common electrode (plate) to which capacitors of memory cells constituting the programmable ROM are connected. When the high voltage corresponding to the selection level of the word line is supplied to the electrode) and the dielectric film of the capacitor is destroyed, the potential of the bit line is the ground potential of the circuit. When the dielectric film of the capacitor is not destroyed, the potential of the bit line is set to the operating voltage. Keep it at the same level. As a result, the write circuit PROGRAM forms the above write signal corresponding to the bad address supplied from the Y address buffer Y-AB, transfers it to each of the data lines B0 to B11 of the programmable ROM, and at the same time the capacitor A data write operation for supplying a high voltage to the connected common electrode is performed.

2 shows a block diagram of an essential part of another embodiment of a dynamic RAM in which random defect relief is performed using a programmable ROM according to the present invention. In this embodiment, the data lines provided in the redundant circuit R-ARY are redundant data lines for performing defect relief of the defective data lines in the memory array M-ARY on a data line basis and in random units on a bit basis. Any of the redundant data lines can be used.

Therefore, the selection circuit of the redundancy circuit R-ARY is used for the redundancy data line for the data line unit relief or the random line for the bit line unit by the selection circuit SELECT1 which performs bit line switching. The data lines used for random rescue are always in a selected state. The input / output lines corresponding to the data lines in the selected state are switched in accordance with the Y address comparison result of the comparison circuit CMP by the selection circuit SELECT2 provided between the input / output circuits I / O. The other configuration is the same as that of the embodiment of FIG.

3 shows a schematic circuit diagram of an embodiment of the memory array of the dynamic RAM and the programmable ROM. The memory arrays R and M-ARY as redundant circuits of the dynamic RAM and regular circuits for performing normal data write / read operations are addressed at the intersections of the plurality of word lines WL and the plurality of data lines DL, respectively. A memory cell including a selection MOSFET MMa and a capacitor Ca for information storage is provided. The gate of each address selection MOSFET MMa is connected to a corresponding word line WL, and its source or drain is connected to a corresponding data line DL. The other source or the drain of the address selection MOSFET MMa is connected to one electrode (accumulation node) of the information storage capacitor Ca. The other electrodes of these capacitors Ca are common to form a plate electrode PLATE1. Is connected to. The plate electrode PLATE1 receives the power supply voltage Vcc and becomes half of the power supply voltage Vcc by a plate voltage generation circuit (not shown) which generates half of the voltage Vcc / 2. As a result, the voltage applied to the dielectric film forming the capacitor for information storage is minimized. That is, the voltage applied to the capacitor of the memory cell through the data line DL is at a low level whose high level is the same as the voltage Vcc and its low level is almost 0V. Therefore, the voltage applied to the dielectric film constituting the capacitor becomes the difference between the voltage of the plate electrode PLATE1 and the high level and the low level, and the maximum value is Vcc / 2. In such a case, the voltage applied to the dielectric film of the capacitor can be reduced, so that the thickness of the dielectric film can be reduced, resulting in a larger capacitance value of the capacitor.

A memory array (ROM-ARY) constituting a programmable ROM is used for address selection in the same form at each intersection of a plurality of word lines and a plurality of data lines DL formed integrally with the word lines of the memory array of the dynamic RAM. A plurality of memory cells constituted by the MOSFET MMb and the capacitor Cb for information storage are provided. However, the gate of each address selection MOSFET MMb is connected to a corresponding word line WL, and one source or drain thereof is connected to a corresponding data line DL. The other source or drain of the address selection MOSFET MMb is connected to one electrode (accumulation node) of the information storage capacitor Cb. The other electrodes of these capacitors Cb are common, but are connected to the plate electrode PLATE2 separated from the plate electrode PLATE1. These memory cells store information by whether an insulating film, which is a dielectric film of a capacitor, is destroyed. For this reason, a ROM capable of electrically recording nonvolatile data in the memory array of the dynamic RAM can be incorporated. This ROM can be used as a programmable ROM by using a specific storage area of the dynamic type RAM in addition to being used for random relief in units of bits as in the above embodiment.

4 is an explanatory diagram of one embodiment of a data write operation and a read operation of a memory cell of the programmable ROM. The word line is set to a high voltage, such as VCH, during programming and during normal operation. As a result, the VCH becomes a voltage which is as high as the threshold voltage of the address selection MOSFET with respect to the operating voltage Vcc. This uses the word line selection voltage VCH corresponding to performing a full write to supply the write signal at the high level of the capacitor through the bit line (data line) to the dynamic memory cell.

The data line becomes VCH or Vss (0V) during programming. Although not particularly limited, in the case of normal operation, the precharge voltage becomes the operating voltage Vcc. In addition, a super Vcc is applied to the plate electrode PLATE2 which is a common electrode of the capacitor, and a half Vcc (Vcc / 2) is applied during normal operation.

Although each said voltage is not specifically limited, Super Vcc is 5V, VCH is 3.6V, Vcc is 2.2V, and half Vcc is 1.1V. Each of these voltages is formed as follows, for example, according to a 2.2V power supply voltage (Vcc) supplied from an external terminal, a booster circuit such as an internal charge pump circuit has a VCH of 3.6V and a supercharger of 5V. Forms Vcc. Half Vcc is formed by dividing the above 2.2V. The external terminal may be supplied with a power supply voltage of 3.3V and stepped down by an internal circuit to form the above-mentioned 2.2V Vcc. In this case, the super Vcc is formed by boosting the power supply voltage of 3.3V to 5V by the charge pump circuit.

As a result, during the programming, a high voltage of 5 V is applied to the capacitor to destroy the insulating film, which is a dielectric film. On the other hand, in the normal write operation, the capacitor is supplied with a 0 V or 2.2 V recording signal only from the bit line centering on the half Vcc of 1.1 V. Since only 1.1 V is applied, no breakdown occurs.

5 is a configuration diagram for explaining an example of the write operation of the programmable ROM. In the same drawing, two word lines WL1 and WL3 which are non-selected between the select word lines WL2 and two which do not destroy the dielectric film of the capacitor between the data lines BL2 which destroy the dielectric film of the capacitor are shown. Data lines BLI and BL3 are exemplarily shown.

In order to set the programmable ROM, the word line WL2 is set to 3.6V corresponding to the VCH. At this time, the other word lines WL1 and WL3 are set to 0V corresponding to Vss. The address select MOSFETs whose gates are connected to the selected word line WL2 are turned on, and the address select MOSFETs whose gates are connected to the other unselected word lines WL1 and WL3 are turned off.

3.6V corresponding to VCH is supplied to the data lines BL1 and BL3, and 0V corresponding to Vss is supplied to the data lines BL2. Then, 5 V corresponding to the super Vcc is applied to the common plate electrode. In the memory cell in which the word line is unselected as described above, since the address selection MOSFET is turned off, no voltage is applied to the capacitors in the data lines BL1 to BL3. On the other hand, in the memory cell in which the address selection MOSFET is turned on by the selection level of the word line WL2, the voltages of the data lines BL1 to BL3 are transferred to the capacitor as they are. For this reason, based on the plate voltage of 5V, 5V is applied to the capacitor of the memory cell in which insulation breakdown of the dielectric film of the capacitor is performed. Only a voltage almost equal to the normal operating state of 1.4 V (5 V to 3.6 V) is applied to a capacitor of a memory cell in which dielectric breakdown is not performed.

6 shows a schematic cross-sectional view of one embodiment of a memory cell of a dynamic RAM and a programmable ROM. In this embodiment, an accumulation electrode for determining the capacitor value of the capacitor is provided above the data line. By providing the storage electrode on the data line in this manner, the area of contact can be increased because the contact portion for connecting the data line and the source or drain diffusion layer of the address selection MOSFET is not affected. As described above, the plate electrode serving as the common electrode corresponding to the storage electrode is provided on the uppermost portion through the thin capacitive insulating film as the dielectric. The word line is formed integrally with the gate electrode of the address selection MOSFET. A field insulating film made of a thick oxide film is formed on the semiconductor substrate except for the portion where the address selection MOSFET is formed.

7 shows a schematic layout diagram of an embodiment of the memory cell. An accumulation node (accumulation electrode) is provided between the word line and the data line. The data line contact is a contact portion for connecting the data line and the source and drain of the address selection MOSFET. The pitch of the word line is small, for example, 1.35 mu m, and the pitch of the data line is small, such as 2.54 mu m. In addition, since the data lines are in a folded bit line system, the data lines are composed of one pair, so that two portions become one pitch. For this reason, the size of one memory cell is 1.35. 2.54 = 3.43, which is about 1/60 when the fuse is used as described above.

8 shows a circuit diagram of an embodiment in which the present invention is applied to defect relief of an EPROM. The memory array (M-ARY) of the EPROM which performs a normal data writing / reading operation is a nonvolatile memory having control gates and floating gates at intersections of a plurality of word lines WL and a plurality of data lines DL, respectively. An element is installed and comprised. As a result, the control gate is connected to the word line WL, and the drain is connected to the data line DL. The source is connected to the source line SL in a flash EPROM in which the erase operation is performed using a tunnel current. A high voltage is supplied to the source line during the erasing operation so that electrons accumulated in the floating gate are drawn out to the source side by the tunnel current.

In the defective memory array ROM-ARY, a plurality of nonvolatile memory elements as described above are provided at an intersection of a plurality of word lines and a plurality of data lines DL formed integrally with the word lines of the memory array M-ARY. It is configured. However, in order to ensure that this memory cell is performed only once, in other words, the Y address is not erased by the erase operation on the memory array (M-ARY) side for the above-mentioned defect repair. In such a flash EPROM, the source is fixed to the ground potential GND of the circuit and becomes impossible to erase. In the configuration in which the erasing operation is performed by ultraviolet irradiation, a film for blocking light such as an aluminum film is provided on the entire portion where the memory array ROM-ARY is formed, or an erasing window is not formed.

The entire block diagram of the EPROM device is constructed similarly to the first diagram above. However, address signals are supplied to the X address buffers X-AB and Y address buffers Y-AB from independent address terminals, respectively. In the flash EPROM, the erase circuit as described above for supplying the erase voltage to the source line during the erase operation is provided.

9 shows a configuration diagram of an embodiment of a personal computer system using the semiconductor memory device to which the present invention is applied. A schematic view of the main part of the appearance is shown in Fig. 9A, and a block diagram is shown in Fig. 9B.

A floppy disk drive (FDD) and a file memory (file M) using a dynamic RAM (DRAM) to which the present invention is applied as a main memory are incorporated. The input / output device includes a keyboard KB and a display DP, and a floppy disk FD is inserted into the floppy disk drive FDD. This provides a desktop type personal computer capable of storing information in the floppy disk FD in software and in the file memory file M in hardware.

Although the present embodiment describes an example applied to a desktop type personal computer, the present invention can also be applied to a notebook type personal computer and the like. A floppy disk is described as an example of an auxiliary function, but is not particularly limited.

In the ninth embodiment (B), the personal computer of the present embodiment includes a central processing unit (CPU) as an information apparatus, an I / O bus, a bus unit, a main memory, an expansion memory, and the like, which are built into the information processing system. MEMORY CONTROL UNIT to access high-speed memory, a dynamic RAM according to the present invention as a main memory, an EPROM (flash memory FEPROM) in which basic control programs, etc. are stored, and a keyboard (KB) connected to the front end. It is configured by keyboard controller (KBDC).

As a display adapter, a display adapter is connected to the I / O bus, and a display is connected to the front end of the display adapter. The I / O bus may include a parallel port I / F, a serial port I / F such as a mouse, a floppy disk drive (FDD), and a hard disk drive (HDD) on the I / O bus. A buffer controller (HDD Buffer) to convert to I / F is connected. In the memory control unit, the bus is connected to the bus, and the dynamic RAM according to the present invention is connected as an extended RAM and a main memory. The extended RAM is also composed of a dynamic RAM (DRAM) according to the present invention.

The operation of this personal computer system will be outlined. When the power is turned on to start the operation, the central processing unit (CPU) first accesses the ROM through the I / O bus to perform initial diagnosis and initial setting. Then, the auxiliary memory device loads the system program into the DRAM of the present invention as the main memory. The central processing unit (CPU) operates by accessing the HDD to the HDD controller via the I / O bus. When the loading of the system program is finished, the process proceeds at the request of the user.

The user proceeds with the input / output of the process by the keyboard controller KBDC or the display adapter on the I / O bus. If necessary, the input / output device connected to the parallel port I / F and the serial port I / F is utilized. In addition, when the main memory is short in the dynamic RAM (DRAM) according to the present invention as the main memory on the main body, the main memory is supplemented by the extended RAM. In addition, although shown as a hard disk drive (HDD) in drawing, it is also possible to replace with the flash file using flash memory (FEPROM).

Figure 10 shows a block diagram of one embodiment of a defect repair LSI in which a programmable ROM according to the present invention is used. Each circuit block of the same figure is formed on one semiconductor substrate like single crystal silicon by a known technique for manufacturing a semiconductor integrated circuit.

The X address buffer (X-AB) and the Y address buffer (Y-AB) have the same functions as the X address buffer and the Y address buffer of the dynamic RAM. As a result, the X address buffer X-AB is an X address signal inputted from the address terminal based on a signal formed through a timing generation circuit (not shown) based on the low address strobe signal / RAS inputted from the control terminal. ADD). The Y address buffer Y-AB accepts the Y address signal input from the address terminal based on the signal formed through the timing generation circuit based on the column address strobe signal / CAS. Here, the slash "/" symbol indicates an over bar indicating that the low level is an active level in the drawing. The same is true for overbars attached to other signals.

The X address comparison circuit 3 is composed of a programmable ROM using the dynamic memory cell. The redundant memory RAM is used to replace a bad chip address (DADD), a rescue flag, and a bad word line by performing memory access by an X address signal. A negative X address is recorded. Here, the bad chip address is a signal which is output when the coincidence is matched by the comparison in the address comparison circuit, and represents a signal which is input to the redundant relief RAM section. If the relief flag is valid by reading the corresponding data by the X address inputted from the address terminal by memory access, the read X address is supplied to the X address selection circuit of the redundant relief RAM section. Although the redundancy relief RAM portion is not particularly limited, it is composed of a static RAM (SRAM), and word lines are selected on the redundant relief RAM portion based on the X address output from the address comparison circuit, so that the Y address buffer (Y-AB) is selected. The selection operation of the Y address is performed by the Y address accepted by (). Although the address comparison circuit 3 is not particularly limited, the / RAS signal is supplied, and the read operation is made effective when this is at the active level, so that the operation in synchronization with the operation of the dynamic RAM is performed.

The read / write switch section 5 determines the write operation when the write enable signal / WE is at the low level, and determines the read operation when the write enable signal / WE is at the low level, and determines the data bus (MO-IO) and the input / output unit. The signal transmission direction of (7) is controlled. The data bus (MO-IO) selecting section 6 connects the input / output data bus (MO) of the redundancy relief RAM section in correspondence with the data bus (IO) to which the dynamic RAM in which there is a defect is connected. The input / output unit 7 corresponds to a data bus to which a plurality of dynamic RAMs are connected, and selects and activates an input / output circuit 7 corresponding to a data bus to which the defective dynamic RAM is connected.

The OE mask section 8 forms an output enable signal / OE in the X address comparison circuit 3 that puts the output circuit of the dynamic RAM in a high impedance state corresponding to the bad chip address DADD. In the case where the dynamic RAM does not have an output enable terminal (/ OE), the / RAS signal may be used instead of the output enable signal (/ OE). In other words, by setting the low address strobe signal / RAS of the defective dynamic RAM to a high level, the non-selected state may be made an output high impedance state. However, in order to cope with such a configuration, the / RAS signal is supplied to each of the dynamic RAMs through the defect relief LSI according to the present invention.

Fig. 11 shows a block diagram of an embodiment of a memory device (memory module SIMM) equipped with the above-mentioned defect repair LSI. This embodiment is for a 72-pin memory module (SIMM). After all, approximately 4M (mega) words A combination of eight four-bit dynamic RAMs constitutes a memory module (SIMM) of approximately 16M bytes.

The eight dynamic RAMs each having the data terminals D0 to D7 have memory accesses in units of 4 bits. It has a storage capacity of about 4M words (about 16M bits in total). Therefore, the address signal is composed of 12 bits A0 to A11 and applied to the address terminal ADD. The data bus of the memory module (SIMM) has 32 (bits) of I00 to I031, and each of the eight dynamic RAMs of each of D0 to D7 is in charge of four bits so that memory access can be performed in 32-bit units. Is done.

Control signals of / RAS, / CAS and / WE input to the memory module SIMM are supplied in parallel to each of the dynamic RAMs having the data terminals D0 to D7. In addition, each of the dynamic RAMs is commonly connected to the power supply voltage Vcc and the ground potential VSS of the circuit. As described above, when eight dynamic RAMs are accessed in parallel, a dynamic RAM having defects as described later by using output enable signals / OE0 to / OE7 which are not used in the conventional memory module. A mask is performed for the read signal at.

In the memory module (SIMM) as described above, a defect repair LSI (S1) shown in FIG. 10 is mounted in order to perform defect repair in units of word lines (refresh addresses) in each dynamic RAM. As described above, the defect repair LSI used as the memory module (SIMM) has the same input interface as the dynamic RAM and a data input / output interface corresponding to the data bus of the memory module (SIMM). The output enable signals / OE0 to / OE7 formed in the mask portion provided in the defect relief LSl are supplied to the output enable terminals / OE0 to / OE7 of the respective dynamic RAMs D0 to D7.

A connector electrode of 72 pins of a memory module (SIMM), not shown, is fitted on a slot for a memory board. A plurality of slots are provided on the memory board, so that a plurality of memory modules (SIMMs) can be mounted as needed. In this manner, the information storage capacity of the storage device such as a computer system as shown in FIG. 9 is determined corresponding to the number of memory modules SIMM.

In FIG. 10, the redundancy repair RAM section of the defect repair LSI selects the Y address through the Y address buffer (Y-AB) and the Y address decoder (Y-DEC) in response to the Y address signal input from the address terminal. An operation is performed to perform memory access in units of four bits. Although not shown, the common data lines are formed in four pairs and connected to the input / output data bus MO. The output enable (OE) mask unit reads the chip address of 3 bits read by the X address comparison circuit, and stores the output enable signal (/ OE) formed by the timing generation circuit (not shown). The output enable signal (/ OE) corresponding to the chip remains at the high level, and the output is brought into a high impedance state.

The OE mask section 8 is substantially stopped during the recording operation. As a result, during the write operation, the output enable signal (/ OE) of the dynamic RAM remains at the high level, so that the recording is performed on the redundant relief RAM section, and at the same time, on the dynamic RAM side where the bad word lines exist. This is done. Although a meaningless write operation is performed on the bad word line as described above, it is ignored in the read operation and the output of the stored data is performed in the redundant relief RAM section. By doing this, a special control circuit such as stopping memory access of the dynamic RAM in which a bad word line exists during a write operation can be avoided and the circuit can be simplified.

The output bus (MO-IO) selecting section connects the input / output line and the input / output section of the redundant RAM section. As a result, on the memory module SIMM, as described above, the dynamic RAM having the data terminals D0 to D7 is distributed by 4 bits on a 32-bit data bus. For this reason, a data bus (MO-IO) selection section is required to arrange the bits corresponding to the dynamic RAM in which the bad word lines exist.

The input / output section includes eight input / output circuits (Dout / Din) in which one circuit performs input / output by four bits through the input / output terminal IO corresponding to each of the dynamic RAMs having the data terminals D0 to D7 as described above. It is composed. On the internal circuit side of the input / output circuit, an input / output circuit corresponding to the data bus to which the input / output terminal of the dynamic RAM in which the bad word line is present is connected to the input / output line of the redundancy relief RAM section through the MO-IO selection section. Since the bad chip address is supplied to the X decoder circuit (X-DEC) from the programmable ROM of the X address comparison circuit, the input / output circuit corresponding thereto is activated, and the memory is used as a redundancy relief RAM instead of a dynamic RAM having a bad word line. Access is made.

In order to perform a write operation on the programmable ROM constituting the address comparison circuit, at the time of the above write operation on such a programmable ROM, eight input circuits of the eight input / output circuits are activated at the same time and relief data is input.

The defect relief LSI of this embodiment is based on the fact that the memory access of the dynamic RAM is inputted by the X address and the Y address in a time division manner, so that the relief is performed only by the X address. As a result, determination of whether or not the defective word line is corrected by input of the X address is started, and the time required for the determination of the relief is adjusted by using the input of the Y address later. As a result, the defective word line generated in the memory module can be repaired without sacrificing a substantial memory cycle.

Fig. 12 shows a circuit diagram of an embodiment of a sense amplifier used for a read operation of a programmable ROM according to the present invention. In this embodiment, a double balanced differential sense amplifier is used to increase the gain for the low amplitude input signal. As a result, since rewriting is unnecessary like a dynamic memory cell, two single-ended differential sense amplifiers are used to connect one of the l-pair input terminals to the data line DL and to reference the other. The voltage Vref is supplied and the complementary output signals of the two single-ended differential sense amplifiers are supplied to the differential amplifier circuit at the output stage. As described above, when the precharge voltage is 2.2V and the half Vcc is 1.1V, the reference voltage Vref is about 1.65V.

As described above, the current source MOSFETs Q5, Q10 and Ql6, which form the operating current of each differential circuit, are turned off by the control signal? Pr to prevent the DC current from flowing through the sense amplifier when the read operation is not performed. In this case, in order to prevent the output signal from becoming unstable, the output unit provided with the P-channel MOSFET Q15 is controlled by the control signal phi pr to fix the output node to a high level. The output signal Vo is not particularly limited, but is supplied to the comparison circuit CMP through the CMOS in-buffer circuit. Although not particularly limited, the main amplifier activation signal can be used as the control signal phi pr.

The working effect obtained in the above embodiment is as follows. In other words,

(1) A memory comprising an address selection MOSFET having a gate connected to a word line and one side of a source / drain connected to a data line, and a capacitor having a dielectric film having a thin insulating film connected in series with the address selection MOSFET. In the write operation, the address selection MOSFET is turned on during the write operation, and a high voltage is applied to the selected capacitor between the data line and the common electrode of the capacitor, resulting in insulation breakdown, and during the read operation. A voltage different from the precharge voltage supplied to the data line is supplied to the common electrode of the capacitor so that the potential change of the data line is sensed by the sense amplifier and used as a programmable ROM. This configuration has the effect that a highly integrated programmable ROM of the same size as a dynamic memory cell can be incorporated in a semiconductor integrated circuit device.

(2) The programmable ROM of (1) is used as a ROM in which access is performed by the X address and the Y address signal in which the defective cell is present is electrically recorded, and is adjacent to the X address selection circuit of the dynamic RAM. By arranging the programmable ROM on the memory array, the circuit can be greatly simplified, and the Y and Y address signals of the programmable ROM are compared and matched with each other. By selecting the redundant circuit, the effect of efficiently resolving random defects in units of bits can be obtained.

(3) A redundant circuit in a dynamic RAM in which the X address signal and the Y address signal are input in time series using a difference in input time between the X address signal and the Y address signal according to (2). Since the switching to the furnace is performed, the effect of speeding up the operation can be obtained.

(4) The common electrode of the memory cells constituting the programmable ROM has the same voltage as the selection level of the word line during the write operation, and the data line on which the write is made becomes the ground potential of the circuit. By setting it to 1/2 and supplying the precharge voltage corresponding to the operating voltage to the data line, the same voltage as that used in the dynamic RAM can be used as it is, so that a special power supply circuit is unnecessary, and the dynamic RAM The effect that the match with can be made favorable is acquired.

(5) The input / output interface unit corresponding to the data bus of the memory device, in which the programmable ROM comprises the same address and control as the dynamic RAM, the plurality of dynamic RAMs, and the substantial chip address of the dynamic RAM. And Y received by the input interface unit when a word line is selected by a comparison coincidence signal between a ROM in which a bad X address is recorded and a X address received by the input interface unit and a bad address stored in the ROM. A redundancy relief RAM section in which the Y address is selected by the address signal, a selection circuit connecting the data input / output bus of the redundant relief RAM section with an input / output circuit corresponding to a bad chip address, and a defective dynamic RAM. Selectively activates an input / output circuit connected to a corresponding data bus In the defect relief semiconductor integrated circuit device comprising a data input / output section and a mask section for outputting a control signal in a high impedance state during a read operation of an output terminal of the defective dynamic RAM, wherein the programmable ROM is used. As a result, the effect that defect relief can be efficiently performed on the memory module is obtained.

(6) a nonvolatile memory circuit including a memory array (regular circuit) and a redundant array in which erasable nonvolatile memory cells are arranged in a matrix, and the nonvolatile memory cell on a bit line such as a memory array of the nonvolatile memory circuit; A memory unit having the same semiconductor structure is provided in an erase-disabled state, and a ROM unit in which a Y address signal in which a defective cell is present is written in the memory array, a read signal in the ROM unit and a Y address of the nonvolatile memory circuit. By using a comparison circuit for comparing signals and a switching circuit for selecting a redundant array instead of the memory array (regular circuit) by the comparison coincidence output of the comparison circuit, a nonvolatile memory device capable of performing defect repair in units of bits can be obtained. Effect is obtained.

As mentioned above, although the invention completed by the present inventor was demonstrated concretely based on the Example, this invention is not limited to the said Example, Of course, various changes are possible in the range which does not deviate from the summary. For example, a plate electrode of a memory cell used as a programmable ROM is formed separately from a plate electrode of a dynamic RAM. During a read operation, the plate electrode of the memory cell is connected to the precharge voltage of the data line as the ground potential of the circuit in addition to the half Vcc. The difference may be increased. In this way, the read level is increased and the margin with the reference voltage Vref can be increased. As the sense amplifier, one of the twelfth single-ended differential amplifier circuits may be configured corresponding to the input signal level in addition to the high sensitivity as shown in FIG. In addition, the modified sense amplifier used for the dynamic RAM may be used. In this case, a reference voltage may be formed using a dummy cell.

Dynamic RAM, which is the target of defect relief, refers to the use of dynamic memory cells as memory cells, and is called a pseudo static RAM that makes the input / output interface compatible with the static RAM. It goes without saying that it also includes a specific use such as image processing having a function.

The programmable ROM using the memory cell having the same structure as the dynamic memory cell according to the present invention is mounted in the dynamic RAM as described above or in the semiconductor integrated circuit device for defect repair of the dynamic RAM. In addition to being used for defect repair, the present invention can be widely used for a programmable ROM embedded in a semiconductor integrated circuit device.

The effect obtained by the typical thing of the invention disclosed in this application is briefly described as follows. That is, a memory cell composed of a capacitor having a dielectric having a thin film insulating film connected in series with the address selection MOSFET and a gate connected to the word line and one side of the source / drain connected to the data line. In the write operation, the address selection MOSFET is turned on, and a higher voltage is applied to the selected capacitor between the data line and the common electrode of the capacitor than in normal operation to cause insulation breakdown. A voltage different from the precharge voltage supplied to the line is supplied to the common electrode of the capacitor so that the potential change of the data line is sensed by the sense amplifier and used as a programmable ROM. This configuration makes it possible to embed a highly integrated programmable ROM of the same size as a dynamic memory cell in a semiconductor integrated circuit device.

The programmable ROM is accessed as an X address and used as a ROM in which a Y address signal in which a defective cell is present is electrically recorded. The programmable ROM is adjacent to an X address selection circuit of a dynamic RAM and is arranged on a memory array of a regular circuit. By arranging the ROM, a large circuit can be simplified, and when the read signal and the Y address signal of the programmable ROM are compared and matched, the Y redundant circuit is selected instead of the memory array (regular circuit). Can be used to efficiently eliminate random defects.

In the dynamic RAM in which the X address signal and the Y address signal are input in time series, the switching from the memory array (regular circuit) to the redundant circuit is performed by using the input time difference between the X address signal and the Y address signal. The speed can be increased.

The common electrode of the memory cell constituting the programmable ROM has the same voltage as the selection level of the word line during the write operation, and the data line on which the write is made becomes the ground potential of the circuit, and half of the operating voltage during the read operation. In addition, since the precharge voltage corresponding to the operating voltage is supplied to the data line, the same voltage as that used in the dynamic RAM can be used as it is, so that a special power supply circuit is not necessary, so that it matches the dynamic RAM. Can make it good.

The programmable ROM has the same address and control input interface unit as the dynamic RAM, an input / output interface unit corresponding to the data bus of the memory device including a plurality of dynamic RAMs, and a substantial chip address and defect X of the dynamic RAM. Y address signal received by the input interface unit when a word line is selected by a comparison matching signal between a ROM in which an address is written and an X address signal received by the input interface unit and a bad address stored in the ROM. A redundancy relief RAM section for selecting columns by means of a redundancy relief section, an input / output circuit corresponding to a bad chip address, and a selection circuit connecting the data input / output data buses of the redundant relief RAM section with a defective dynamic RAM; Data that selectively activates the input / output circuit connected to the bus A defect remedy semiconductor integrated circuit device comprising an input / output section and a mask section for outputting a control signal in a high impedance state during a read operation of an output terminal of a defective dynamic RAM, by using the programmable ROM. Defect repair can be efficiently performed on the memory module.

A nonvolatile memory circuit including a memory array and a redundant array in which erasable nonvolatile memory cells are arranged in a matrix; and a memory cell having a semiconductor structure such as the nonvolatile memory cell on a bit line such as a memory array of the nonvolatile memory circuit. A ROM section in which the erasure disable state is provided, in which a Y address signal in which a defective cell exists in the memory array is written; and a comparison circuit for comparing a read signal and a Y address signal in the nonvolatile memory circuit in the ROM section; In addition, a nonvolatile memory device capable of performing defect repair in units of bits can be obtained by a switching circuit which selects the redundant array instead of the memory array by the comparison coincidence output of the comparison circuit.

1 is a main block diagram showing an embodiment of a dynamic RAM in which random defect relief is performed using a programmable ROM according to the present invention;

2 is a main block diagram showing another embodiment of a dynamic RAM in which random defect relief is performed using a programmable ROM according to the present invention;

3 is a schematic block diagram illustrating an embodiment of a memory array of the dynamic RAM and the programmable ROM;

4 is an explanatory diagram showing one embodiment of a write operation and a read operation for a memory cell of the programmable ROM;

5 is a configuration diagram for explaining an example of a write operation of the programmable ROM;

6 is a schematic cross-sectional view showing an embodiment of a memory cell of the dynamic RAM and the programmable ROM;

7 is a schematic layout diagram illustrating an embodiment of the memory cell;

8 is a circuit diagram showing an embodiment in which the present invention is applied to a defect repair of an EPROM;

9 is a block diagram showing an embodiment of a personal computer system using the semiconductor memory device to which the present invention is applied;

10 is a block diagram showing an embodiment of a defect repair LSI using a programmable ROM according to the present invention;

11 is a block diagram showing an embodiment of a memory device equipped with the defect repair LSI;

12 is a circuit diagram showing an embodiment of a sense amplifier used in the reading device of the programmable ROM according to the present invention.

** Explanation of symbols for main parts of drawings **

X-AB ... X address buffer X-DEC ... X decoder circuit,

WD ... word driver, Y-AB ... Y address buffer,

Y-DEC ... Y decoder circuit, R-YDEC ... redundancy selection circuit,

R-ARY1 ... first redundant circuit, R-ARY2 ... second redundant circuit,

I / O ... input / output circuitry, CPU ... central processing unit,

DP ... display, FDD ... floppy disk drive,

FD ... floppy disk, file M ... file memory,

KB ... keyboard, HDD ... hard disk drive,

SA1, SA2 ... sense amplifier, PROGRAM ... recording circuit.

Claims (10)

A plurality of word lines, a plurality of first data lines, and one side of a source / drain are connected in series to the first address selection MOSFET and the first address selection MOSFET connected to the first data line, and the dielectric is insulated. A memory array comprising a plurality of first memory cells comprising a first capacitor made of A plurality of second word lines, a plurality of second data lines, and one side of a source / drain are connected in series to a second address selection MOSFET and the second address selection MOSFET connected to the second data line A programmable ROM including a plurality of second memory cells made of a second capacitor made of an insulating film, In the write operation, a high voltage is applied between the second data line and the common electrode of the second capacitor to the second capacitor selected by putting the second address selection MOSFET in a conducting state, thereby preventing dielectric breakdown. Produce, And a sense amplifier for sensing a potential change of the second data line by applying a voltage different from the precharge voltage supplied to the second data line to the common electrode of the second capacitor during a read operation. The method of claim 1, The programmable ROM is formed on the same semiconductor substrate as the memory array, accessed by an X address signal of the memory array, and written into a Y address signal corresponding to a defective cell of the first memory cell. And a comparison circuit in which the read signal of the programmable ROM and the Y address signal of the memory array are compared and a redundant circuit is selected in place of the memory array accessed by the dynamic RAM by the comparison matching output. . The method of claim 1, wherein And the second memory cell of the programmable ROM has the same structure as the first memory cell of the memory array, and is commonly connected to a word line selected by an X address selection circuit of the memory array. The method of claim 3, The common electrode of the second memory cell constituting the programmable ROM is set to the same voltage as the word line select level during the write operation, and the second data line to be written is set to the ground potential of the circuit. In the read operation, the common electrode is set to 1/2 of an operating voltage, and a precharge voltage corresponding to the operating voltage is supplied to the second data line. The method of claim 1, The programmable ROM, An input and control input interface unit such as the memory array; An input / output interface unit corresponding to a data bus of a memory device including a plurality of memory arrays, A ROM in which a substantial chip address of the memory array and a bad X address are recorded; Y in response to the Y address signal received by the input interface unit when a word line is selected according to a comparison matching signal between the X address signal fetched by the input interface unit and the bad address stored in the ROM. A redundancy relief RAM section for selecting an address; A selection unit for connecting a data input / output bus of the redundant RAM storage unit with an input / output circuit corresponding to the bad chip address; A data input / output unit for selectively activating an input / output circuit connected to a data bus corresponding to a bad memory array; And a mask unit for outputting a control signal for setting the output terminal of the bad memory array to a high impedance state during a read operation. The method of claim 5, The programmable ROM is used as a ROM of a defect repairing semiconductor integrated circuit device. A nonvolatile memory circuit including a memory array and a redundant array disposed in a matrix form and having a nonvolatile memory cell; A Y address signal having the same semiconductor structure as that of the nonvolatile memory cell of the nonvolatile memory circuit, being provided in an erasable state on the same word line as the nonvolatile memory cell, and indicating that a defective cell exists in the memory array. A ROM unit including a memory cell in which is recorded; A comparison circuit for comparing the read signal from the ROM unit with the Y address signal of the nonvolatile memory circuit; And a switching circuit for selecting a redundant circuit in place of the selected memory array in response to a comparison match output of the comparison circuit. A plurality of word lines, A plurality of first data lines, A plurality of dynamic memory cells provided corresponding to intersections of the plurality of word lines and the plurality of first data lines; Redundant data lines, A plurality of redundant memory cells provided corresponding to intersections of the plurality of word lines and the redundant data lines; A plurality of second data lines, And a plurality of nonvolatile memory cells provided corresponding to intersections of the plurality of word lines and the plurality of second data lines, According to the presence or absence of insulation breakdown of each capacitor in the plurality of nonvolatile memory cells, a program for the plurality of nonvolatile memory cells is performed. When a signal based on an X address signal is supplied to the plurality of word lines, the defect information signal obtained from the plurality of second data lines coincides with the Y address signal, instead of the plurality of first data lines. And a redundant data line is selected. The method of claim 8, The plurality of dynamic memory cells each include a capacitor for information storage. And a manufacturing process is common to each of the capacitors in the plurality of dynamic memory cells and each of the capacitors in the plurality of nonvolatile memory cells. The method of claim 9, And the X address signal and the Y address signal are supplied in time series.