JPH0883497A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To reduce the defects accompanying making integration and efficiency of a semiconductor integrated circuit device higher by producing dielectric breakdown in the memory cell having a capacitor connected in series to the MOSFET for address selection at the time of writing and sensing the memory by impressing a voltage different from the precharge onto the common electrode of the capacitor at the time of reading. CONSTITUTION: One word line is selected by decoding the signal taken into a buffer X-AB in synchronization with the line address strobe signal from a CPU, and a data line is selected for a signal CAS. The memory array is constituted from a normal circuit, a redundancy circuit R-ARY1 which remedies the defect in the unit of data line DL and a R-ARY2 which remedies the defect in the bit unit, and a sense amplifier SA1 corresponding to the memory array conducts re-writing to the memory cell. Input/output lines included in the decoder Y-DEC and R-YED are selectively connected with the data lines in the memory cell array through a line SW and also to the I/O through a selection circuit SELECT. This constitution can incorporate a PROM having high integration of the same size as the D-type memory cell.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a dynamic type R with a large storage capacity.
The present invention relates to a technique effectively used for a defect relief technique for AM (random access memory) and EPROM (erasable & programmable read only memory).

[0002]

2. Description of the Related Art As a defect relief technique in a semiconductor memory device, a defective address is stored by using a fuse, and a row or a column (word line or data line) including a defective bit is collectively stored as a spare row or column for redundancy. Some of them are performed by substituting (preliminary word line or preliminary data line). Defect relief techniques using such fuses are disclosed, for example, in Japanese Patent Laid-Open Nos. 60-89899 and 6-96.
No. 3-79298 is available.

[0003]

As described above, in the case where the defective address is stored by using the fuse, even in the latest semiconductor technology, the pitch is about 10 μm, and a large area such as a length of about 20 μm is required. There is a problem that it ends up. The inventor of the present application has a tendency that the breakdown voltage of the element as a whole tends to decrease with the miniaturization of the element. The problem that the breakdown voltage becomes relatively small as a result of formation is considered to be used as a ROM from the idea of inversion. In other words, if the dynamic memory cell is used as a non-volatile ROM, the area required to store 1 bit can be greatly reduced to about 1/60 of that in the case of using the fuse, and the process of the dynamic RAM is reduced. Since I can use it as it is, I realized that memory access can be made faster by devising the layout.

An object of the present invention is to provide a semiconductor integrated circuit device which is electrically writable and has a highly integrated ROM. Another object of the present invention is to provide a semiconductor integrated circuit device capable of efficiently repairing defects in a semiconductor memory circuit. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0005]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, for a memory cell including a capacitor having a thin insulating film as a dielectric, a gate is connected to a word line, and one source and a drain are connected in series to an address selection MOSFET in which a data line is connected. During the write operation, the address selection MOSFET is turned on to apply a higher voltage to the selected capacitor between the data line and the common electrode of the capacitor than in the normal operation to cause dielectric breakdown. In the read operation, a voltage different from the precharge voltage applied to the data line is applied to the common electrode of the capacitor so that the potential change of the data line is sensed by the sense amplifier, which is used as a programmable ROM.

[0006]

According to the above means, a highly integrated programmable ROM of the same size as a dynamic memory cell can be incorporated in a semiconductor integrated circuit device.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a programmable R according to the present invention.
A dynamic RAM (Random Accees Memor) in which random defect relief is performed using OM (Read Only Memory)
The main part block diagram of one Example of y) is shown. In this embodiment, one memory array is formed, but it is actually divided into a plurality of mats or blocks according to its storage capacity. Alternatively, the drawing shows one memory array of a plurality of divided memory arrays,
It may be understood that the address selection circuit is functionally represented.

The X address buffer X-AB and the Y address buffer Y-AB are synchronized with an address signal input from a common address terminal (not shown) in time series, and an address strobe signal supplied from a control control terminal. Take in according to (RAS, CAS). The X-system address signal taken into the X-address buffer X-AB in synchronization with the row address strobe signal (RAS) is
The X decoder circuit X-DEC decodes the address signal, and the word driver WD selects one word line. The Y-system address signal fetched by the Y-address buffer Y-AB in synchronization with the column address strobe signal (CAS) is a Y-decoder circuit Y-D.
It is input to the EC, where the address signal is decoded and the selection signal of the data line is formed.

In the figure, a signal line is shown extending from the Y decoder circuit YDEC to the memory array portion, but this is for expressing a memory cell designated by a Y address, and in practice. Complementary data lines are arranged in the memory array portion, and the complementary data lines are connected to the input / output line I / O via the column switch. The Y decoder circuit Y-DEC forms a selection signal for selecting the column switch.

In this embodiment, the memory array serving as a dynamic RAM is a memory array serving as a normal circuit, and the first redundancy circuit R for repairing defects in data line units.
-ARY1 and a second redundant circuit R-ARY2 that repairs defects in bit units. The first redundant circuit R-ARY1 is used to repair defects in the conventional data line unit, and includes a memory circuit storing a Y-system defective address, memory information of the memory circuit, and a Y-system address signal. And a redundancy switching circuit R-
When a defective address is selected by YDE, the data line of the first redundant circuit R-ARY1 is switched to the data line of the normal circuit. The Y-system defective address storage circuit is configured using a conventional fuse.

The sense amplifier SA1 provided corresponding to the memory array as the dynamic RAM amplifies the minute memory information read on the complementary data line of the memory array and stores it by the above read operation. The memory cell whose charge is about to be lost is rewritten. When using the shared sense amplifier system,
A memory array or a memory mat is arranged on the left and right around the sense amplifier SA1. As described above, the sense amplifier SA1 performs the amplifying operation of the read signal and the rewriting operation to the memory cell, so that the operation thereof is controlled by the same timing signal as that of the sense amplifier of the conventional dynamic RAM. A latch circuit is used.

In the figure, the Y decoder circuit Y-
The input / output lines included in the DEC and R-YED are extended in the vertical direction and selectively connected to the data lines of the memory array via the column switches. This input / output line is connected to the input / output circuit I / O via a selection circuit SELECT provided for repairing random defects in bit units as described below.

A programmable ROM according to the present invention is also connected to the word line of the memory array. In this programmable ROM (ROM-ARY), the dielectric film (insulating film) of the capacitor in the dynamic memory cell having the same structure as the memory array of the dynamic RAM is destroyed to perform the write operation. The Y address signal of the defective cell existing on the word line is written in the programmable ROM.

That is, the output signal of the X decoder circuit X-DEC of the dynamic RAM, in other words, the word line of the dynamic RAM is connected to the memory cell forming the programmable ROM, and the programmable R
It is intended to simplify the address selection circuit of the OM. For example, 12 for word lines in the memory array
The bit lines or the data lines of the book are crossed, and the memory cell is provided at the crossing portion as indicated by a circle.

With this configuration, the X of the dynamic RAM is
Programmable RO by system address selection operation
The M access is performed, and the signals of 1 and 0 corresponding to the defective Y address are output from the 12 bit lines. This signal is amplified by the sense amplifier SA2, supplied to one input of the comparator CMP, and compared with the Y address signal output from the Y address buffer Y-AB. Although the memory cell having the same structure as the dynamic memory cell is used, the sense amplifier SA2 is a dynamic memory because the memory operation principle itself is different so that the dielectric film of the capacitor causes dielectric breakdown to store information. The rewriting operation is not required unlike the cell.
Therefore, it is composed of a sense amplifier using a differential amplifier circuit as described later.

When the memory cell as described above is used, the programmable ROM can be integrally formed with the memory array of the dynamic RAM, and the program RO
Since the memory cell of M has the same structure as the memory cell of the memory array of the dynamic RAM, no special manufacturing process is required to form the programmable ROM. Since the address decoder and the word line can be shared with those of the normal circuit of the dynamic RAM, the occupied area of the programmable ROM can be greatly reduced. When repairing two or more defective cells on one word line, the number of bit lines and comparators CMP as described above may be increased in accordance with the number of defective cells to be repaired.

When one random defective cell exists in a specific word line as described above, the programmable ROM stores the Y address where the defective cell exists at the address corresponding to that word line. When there is no defective cell on the word line, writing is not performed, and the Y address at that time is set to initial data, for example, all 0s.
Therefore, if there is no defect in each word line, it is considered that a defective cell exists at an address corresponding to all 0s in the Y address signal, and a redundant circuit is selected instead of the normal circuit.

Therefore, a 1-bit flag may be added to the Y address to be stored and 1 may be written in this bit to indicate that the stored Y address is a defective address. In this case, the output signal of the comparator CMP is validated only when the flag output from the programmable ROM is 1. By doing so, it is possible to prevent the defective cell from being considered to exist at the address corresponding to the initial data of the storage element of the programmable ROM when there is no defect in each word line.

In the figure, when a random defective cell exists at the position indicated by a black circle, the programmable ROM is designated by the word line (X address) where the defective cell exists to store the Y address on the word line. By adopting such a configuration, even in a dynamic RAM having a large storage capacity of about 16 Mbits, it is only necessary to store a Y address of 12 bits for one defective cell. In the case of the dynamic RAM as described above, since there are about 4K X-system addresses, the programmable ROM only needs to have a small storage capacity of 4K × 12 = 48K bits.

Provided that there is one defective cell on each of about 4K word lines as described above, a maximum of about 4K bits of defective cells are stored in a programmable ROM having a storage capacity of 48K bits as described above. This can be relieved by one comparator CMP that performs a 12-bit comparison operation and the second redundancy circuit R-ARY2 that includes one column of redundancy cells. In this case, the defective data line (DE
Even if the defective cell occurs in the first redundancy circuit R-ARY1 that performs the FECT LINE) defect relief, it can be relieved. By adopting such a defective address designating method, it is possible to simplify the memory circuit for specifying the random defective cell and significantly simplify the comparator for detecting access to the defective cell.

In the X-system address selection operation of the dynamic RAM of this embodiment, the normal circuit having the above defect and the redundant circuit are simultaneously accessed. Then, when it is determined to be defective by the input of the Y-system address signal, the selector SELECT can switch off. That is, since the defective cell is switched to the redundant cell by using the Y-system address selection time, the memory access time can be shortened. In this way, there is no difference in time between the case where the defect exists and the case where the defect does not exist, so that the memory access can be speeded up when the defect relief is performed.

The write circuit PROGRAM is enabled during the write operation, and applies a high voltage corresponding to the selection level of the word line to the common electrode (plate electrode) to which at least the capacitors of the memory cells forming the programmable ROM are connected. When the dielectric film of the capacitor is supplied and the dielectric film of the capacitor is broken, the potential of the data line is set to the ground potential of the circuit, and when the dielectric film of the capacitor is not broken, the potential of the data line is maintained at a high level such as an operating voltage. That is, the write circuit PROGRAM forms the above-described write signal corresponding to the defective address supplied from the Y address buffer Y-AB and transmits the write signal to the data line, and also applies a high voltage to the common electrode connected to the capacitor. A write operation of supplying is performed.

FIG. 2 is a block diagram showing the main part of another embodiment of a dynamic RAM in which random defect relief is performed using the programmable ROM according to the present invention. In this embodiment, the data line provided in the redundant circuit R-ARY is a redundant data line for performing defect relief of a defective data line (DEFECT LINE) in a normal circuit in units of data line and a redundancy for random relief in units of bit. It is made available selectively for both the data line and the data line.

Therefore, in the selection circuit of the redundancy circuit R-ARY, the selection circuit SELECT1 stores whether the redundancy data line is used for the data line unit rescue or the bit unit random repair. The data line used for random relief is always selected. Then, the input / output line corresponding to the data line thus selected is switched by the select circuit SELECT2 provided between the input / output circuit I / O and the comparator CMP. The other structure is similar to that of the embodiment shown in FIG.

FIG. 3 shows a schematic circuit diagram of an embodiment of the memory array of the dynamic RAM and the programmable ROM. The memory arrays R and N-ARY forming the redundant circuit and the normal circuit of the dynamic RAM are
A memory cell including an address selection MOSFET and an information storage capacitor is provided at the intersection of the word line WL and the data line DL. Address selection MOS
The gate of the FET is connected to the corresponding word line WL,
One of the sources and drains is connected to the corresponding data line DL. The other source and drain of the address selecting MOSFET are connected to one electrode (storage node) of the information storage capacitor. The other electrode of the capacitor is commonly used and connected to the plate electrode PLATE1.

The memory array ROM-ARY forming the programmable ROM has the same address selection as the above at the intersection of the data line DL and the word line integrally formed with the word line of the memory array of the dynamic RAM. A memory cell including a power MOSFET and a capacitor for storing information is provided. However, address selection MOS
The gate of the FET is connected to the corresponding word line WL,
One of the sources and drains is connected to the corresponding data line DL. The other source and drain of the address selecting MOSFET are connected to one electrode (storage node) of the information storage capacitor. The other electrode of the capacitor is commonly used and connected to a plate electrode PLATE2 different from the plate electrode PLATE1. This memory cell stores information depending on whether or not the insulating film, which is the dielectric film of the capacitor, is destroyed. Therefore, a ROM capable of electrically writing non-volatile stored information can be incorporated in the memory array of the dynamic RAM. This ROM is used for random relief on a bit-by-bit basis as in the above embodiment, and a specific storage area of a dynamic RAM is programmable RO.
It can also be used as M.

FIG. 4 is an explanatory diagram of an embodiment of write operation and read operation for the memory cell of the programmable ROM. The word line is set to a voltage like VCH during programming and normal operation. That is,
VCH is an address selection MOS for the operating voltage VCC
The voltage is raised by the threshold voltage of the FET. this is,
In the dynamic memory cell, the word line selection voltage VCH corresponding to performing full write of supplying a high level write signal of a capacitor through a bit line (data line) is used as it is.

The bit line is set to VCH or VSS (0V) during programming. Although not particularly limited, the precharge voltage during normal operation is the operating voltage VC.
C The plate, which is the common electrode of the capacitor, is set to the super VCC during programming and is set to the half VCC (VCC / 2) during normal operation.

Specifically, each of the above voltages is a super VCC.
Is 5V, VCH is 3.6V, and VCC is 2.
It is 2V and half VCC is 1.1V. Each of these voltages receives a power supply voltage VCC of 2.2V supplied from an external terminal, for example, and a booster circuit such as an internal charge pump circuit forms a VCC of 3.6V and a super VCC such as 5V. The half VCC is formed by dividing the above-mentioned 2.2V. The power supply voltage such as 3.3V is supplied from the external terminal, the internal circuit lowers the voltage, and the above 2.2V
May be formed. In this case, Super V
CC is formed by boosting the power supply voltage of 3.3V to 5V by a charge pump circuit.

Therefore, at the time of programming, as described below, a high voltage such as 5 V is applied to the capacitor to destroy the insulating film which is the dielectric film. On the other hand, in normal operation, the capacitor is centered on a half VCC of 1.1V, and 0V or 2.2 from the bit line.
Since only the V write signal is supplied and only the voltage of 1.1 V is applied, the dielectric breakdown does not occur.

FIG. 5 is a block diagram for explaining an example of the write operation of the programmable ROM.
In the same figure, the non-selected 2 are sandwiched by the selected word line WL2.
Two data lines DL1 and DL3 that do not destroy the dielectric film of the capacitor are sandwiched between two word lines WL1 and WL3 and the data line DL2 that destroys the dielectric film of the capacitor, and are shown as representatives.

The word line WL2 is set to 3.6V corresponding to the VCH. At this time, the other word lines WL1 and WL3 are set to 0V such as VSS. Address selection MOS whose gate is connected to the selected word line WL2
Address selection MOSFE in which the FET is turned on and the gates are connected to the other unselected word lines WL1 and WL3.
All T are turned off.

The data lines DL1 and DL3 are supplied with 3.6V corresponding to VCH, and the data line DL2 is supplied with 0V corresponding to VSS. Then, 5V corresponding to the super VCC is applied to the plate. In the memory cell in which the word line is not selected as described above, the address selecting MOSFET is turned off, so that the voltage from the data lines DL1 to DL3 is not applied to the capacitor. On the other hand, in the memory cell in which the address selecting MOSFET is turned on by the selection level of the word line WL2, the voltages of the data lines DL1 to DL3 are transmitted to the capacitors as they are. Therefore, based on the plate voltage of 5V, 5V is applied to the capacitor of the memory cell in which the dielectric film of the capacitor is dielectrically broken down. Only a voltage of 1.4V (5V-3.6V), which is almost the same as in the normal operating state, is applied to the capacitor of the memory cell in which the dielectric breakdown is not performed.

FIG. 6 is a schematic sectional view of an embodiment of the memory cells of the dynamic RAM and the programmable ROM. In this embodiment, the storage electrode that determines the capacitance value of the capacitor is provided above the bit line.
By providing the storage electrode above the bit line in this manner, the bit line and the address selection MOSFET are
The area can be increased without being affected by the contact portion for connecting the source and drain diffusion layers. Corresponding to the storage electrode as described above, the plate electrode serving as a common electrode is provided on the uppermost part through a thin capacitive insulating film as a dielectric. Word line is MO for address selection
It is formed integrally with the gate electrode of the SFET. A field insulating film made of an oxide film having a large thickness is formed on the semiconductor substrate except the portion where the address selecting MOSFET is formed.

FIG. 7 shows a schematic layout diagram of an embodiment of the memory cell. A storage node (storage electrode) is provided between the word line and the bit line. The bit line controller is the source of the address selection MOSFET,
It is a contact portion that connects the drain and the bit line. The word line pitch is reduced to 1.35 μm and the bit line pitch is reduced to 2.54 μm. Since the bit line is of the folded bit line type and is composed of a pair, two lines have one pitch. Therefore, the size of one memory cell is
The ratio is 1.35 × 2.54 = 3.43, which is about 1/60 of the case where the fuse is used as described above.

FIG. 8 shows a circuit diagram of an embodiment in which the present invention is applied to defect repair of an EPROM.
Memory array N-AR forming a normal circuit of EPROM
In Y, a nonvolatile memory element having a control gate and a floating gate is provided at the intersection of the word line WL and the data line DL. That is, the control gate is connected to the word line WL and the drain is the data line D.
Connected to L. The source is connected to the source line SL in the flash EPROM in which the erase operation is performed using the tunnel current. A high voltage is supplied to the source line during the erase operation so that the electrons accumulated in the floating gate are extracted to the source side by the tunnel current.

Memory array ROM-ARY for defect relief
In the memory array N-ARY of the normal circuit, a nonvolatile memory element similar to the above is provided at the intersection of the word line formed integrally with the word line and the data line DL. However, in order to prevent this memory cell from performing the write operation only once, in other words, the Y address for defect relief as described above is erased by the erase operation on the normal circuit side. Therefore, in the flash EPROM as described above, the source is fixed to the ground potential GND of the circuit and cannot be erased. In the case where the erasing operation is performed by irradiation with ultraviolet rays, the memory array R
A film for blocking light such as aluminum is not provided on the entire portion where the OM-ARY is formed, or the erasing window itself is not formed.

The entire block diagram of the EPROM device has a structure similar to that of FIG. However, the X address buffer X-AB and the Y address buffer Y-AB are supplied with address signals from independent external terminals.
Further, the flash EPROM is provided with the erasing circuit as described above which supplies the erasing voltage to the source line during the erasing operation.

FIG. 9 shows a block diagram of an embodiment of a personal computer system using a semiconductor memory device to which the present invention is applied. FIG. 1A shows a schematic view of the main part of its appearance, and FIG. 2B shows its block diagram.

This is a system incorporating a floppy disk drive FDD, a file memory fileM by a DRAM to which the present invention is applied as a main memory, and an SRAM as a battery backup. The input / output device is the keyboard KB and the display DP, and the floppy disk FD is inserted into the floppy disk drive FDD. As a result, a desktop type personal computer capable of storing information in the floppy disk FD as software and the file memory fileM as hardware is obtained.

In this embodiment, the example applied to the desktop type personal computer has been described, but the present invention can also be applied to the notebook type personal computer and the like, and the floppy disk has been described as an example of the auxiliary function, but it is not particularly limited.

In (B), the personal computer of this embodiment is the central processing unit CP as this information device.
U, I / O bus built in the above information processing system, B
USUnit, a memory control unit for accessing a high-speed memory such as a main memory or an extended memory, Memory C
The control unit is composed of an control unit, a DRAM according to the present invention as a main memory, an EPROM (flash EPROM) in which a basic control program and the like are stored, a keyboard controller KBDC having a keyboard connected to its tip, and the like.

Display a as a display adapter
The adapter is connected to the I / O bus, and
A display is connected to the tip of the ay adaptor. The I / O bus includes a parallel port Parallel Port I / F, a serial port Serial Port I / F such as a mouse, a floppy disk drive FDD, and an HDD from the I / O bus.
Buffer controller HDD buf for converting to I / F
fer is connected. The memory control unit Memo
D according to the present invention as an extended RAM and a main memory connected to a bus from the ry Control Unit.
RAM is connected. The expansion RAM is also composed of the DRAM according to the present invention.

An outline of the operation of this personal computer system will be described. When the power is turned on and the operation is started, the central processing unit CPU first sets the ROM
Is accessed through the I / O bus to perform initial diagnosis and initialization. Then, the system program is loaded from the auxiliary storage device into the DRAM of the present invention as the main storage memory. The central processing unit CPU operates to access the HDD to the HDD controller through the I / O bus. When the loading of the system program is completed, the processing proceeds according to the processing request from the user.

The user selects the keyboard controller KBDC or the display adapter Display a on the I / O bus.
Work is carried out while inputting / outputting processing by the adapter. And, if necessary, the parallel port Para
lell Port I / F, serial port Seri
Utilize the input / output device connected to the al Port I / F. Further, when the DRAM according to the present invention as the main memory on the main body is insufficient in the main memory capacity, the extended RA
The main memory is supplemented by M. In addition, although it is shown as a hard disk drive HDD in the figure, a flash memory FE
It is also possible to replace with a flash file using PROM.

FIG. 10 shows a block diagram of an embodiment of a defect relief LSI using the programmable ROM according to the present invention. Each circuit block in the figure is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

X address buffer (Xadd) 1 and Y
The address buffer (Yadd) 2 is a dynamic type R
This is the same as the X address buffer and the Y address buffer of AM. That is, the X address buffer 1 fetches the X-system address signal in synchronization with the row address strobe signal / RAS. The Y address buffer 2 fetches a Y-system address signal in synchronization with the column address strobe signal / CAS. Here, / (slash) represents an overbar indicating that the low level is the active level in the drawing. This is
The same applies to the overbars attached to other signals.

The X address (Xadd) comparing section 3 is a programmable R using the dynamic memory cell.
A redundant relief RA which is composed of an OM and is used for replacing a defective chip address, a relief flag, and a defective word line by performing memory access by an X-system address signal.
The X address of the M section 4 is written. Then, the corresponding data is read by the X address input by the memory access, and if the repair flag is valid, the read X address is the redundant repair RAM section 4.
Is supplied to the X system selection circuit. Redundancy repair RAM unit 4
Is composed of a static RAM, though not particularly limited, and a word line is selected by the X address output from the comparison unit 3, and the Y address buffer 2
The Y-system selecting operation is performed by the Y address fetched by. The comparison unit 3 is not particularly limited, but / RAS
When a signal is supplied and the read operation is enabled when the signal is at the active level, the operation synchronized with the operation of the dynamic RAM is performed.

The read / write (Read, Write) switching section 5 determines that the write operation is a write operation if the write enable signal / WE is at a low level, determines that the read operation is from a high level, and outputs signals from the selection section 6 and the input / output section 7. Control the direction of transmission. The selection unit 6 connects the input / output data bus MO of the redundancy relieving RAM unit to the data bus IO to which the defective dynamic RAM is connected. The input / output unit 7 has an input / output circuit corresponding to a data bus to which a plurality of dynamic RAMs are connected, and selects an input / output circuit corresponding to the data bus to which the defective dynamic RAM is connected. And activate it.

The OE max section 8 forms an output enable signal / OE for bringing the output circuit of the dynamic RAM into a high impedance state in response to the defective chip address from the comparison section 3. In addition, dynamic RA
If M does not have the output enable terminal / OE, the / RAS signal may be used instead. That is, the row address strobe signal / RAS of the defective dynamic RAM may be set to a high level to bring it into a non-selected state to create an output high impedance state. However, in order to deal with such a configuration, the / RAS signal is supplied to each dynamic RAM through the defect relief LSI according to the present invention.

FIG. 11 is a block diagram showing an embodiment of a memory device (memory module SIMM) equipped with the defect relief LSI. This embodiment is directed to a 72-pin memory module SIMM. In other words, a memory module SIMM of about 16 Mbytes is configured by combining eight dynamic RAMs each having a configuration of about 4 M (mega) words × 4 bits.

Each of the eight dynamic RAMs D0 to D7 is accessed in units of 4 bits, and has a storage capacity of about 4 M words (about 16 M in total).
Bit) has a storage capacity of. Therefore, the address signal is composed of 12 bits A0 to A11.
The data bus of the memory module SIMM is IO0 to 31
Each of the eight dynamic RAMs D0 to D7 is responsible for 4 bits, and memory access is performed in units of 32 bits as a whole.

Each dynamic RA consisting of D0 to D7
M is input to the memory module SIMM / RA
A control signal composed of S, / CAS and / WE is supplied in parallel. Also, they are commonly connected to the power supply voltage VCC and the ground potential VSS of the circuit. When the eight dynamic RAMs are accessed in parallel as described above, the output enable signals / OE0 to / OE7, which are not used in the conventional memory module, are used,
The read signal from the dynamic RAM having a defect as described later is masked.

In the memory module SIMM as described above, in order to perform defect relief in word line units (refresh address) in each dynamic RAM, the defect relief LSI (shown in FIG. 1) is used. S
1) is installed. Memory module SI as above
The defect relief LSI viewed as an MM is a dynamic type R
It has the same input interface as AM and a data input / output interface corresponding to the data bus of the memory module SIMM. Then, the defect relief LS
The output enable signals / OE0 to / OE7 formed by the mask portion provided in I are supplied to the output enable terminals / OE0 to / OE7 of the dynamic RAMs D0 to D7.

The contact electrode, which is composed of 72 pins of the memory module SIMM (not shown), is inserted into the slot for the memory board. A plurality of slots are provided on the memory board so that a plurality of memory module SIMMs can be mounted as needed. The information storage capacity of a storage device such as a computer system as shown in FIG. 9 is determined according to the number of such memory modules SIMM.

In FIG. 10, the redundancy repair RAM section 4 of the defect repair LSI is subjected to a column selection operation by the Y address (Yadd), and memory access is performed in units of 4 bits. The common data line consists of 4 pairs and MO
Connect to the bus. The OE mask unit 8 uses the 3-bit chip address (chip ad
d) is decoded by the decoder, the output enable signal / OE formed by the timing generation circuit is masked, and the output enable signal corresponding to the chip of the dynamic type RAM that has been rescued is kept at the high level. Put the output in a high impedance state.

The OE max section 8 is substantially stopped during the writing operation. That is, during the write operation, since / OE of the dynamic RAM is kept at the high level, writing is performed on the redundant relief RAM section 4 and also on the dynamic RAM side having the defective word line. A write operation is performed. As described above, a meaningless write operation is performed on the defective word line, but since it is ignored during the read operation and the stored data is output from the redundancy repair RAM section 4, there is a practical problem. Absent. By doing so, a special control circuit for stopping the memory access of the dynamic RAM in which the defective word line exists during the write operation becomes unnecessary, and the circuit can be simplified.

The selecting section 6 connects the input / output line of the redundant relief RAM section 4 and the input / output section 7. That is, on the memory module SIMM, as described above, the dynamic RAM composed of D0 to D7 is distributed on the 32-bit data bus by 4 bits. Therefore, the selection unit 6 is required to fit in the bit corresponding to the dynamic RAM having the defective word line.

The input / output unit 7 has the above-mentioned D0-D.
Corresponding to 7 dynamic RAMs, eight I / O circuits Dout /
It is composed of Din. On the internal circuit side of the input / output circuit, an input / output circuit corresponding to the data bus connected to the input / output terminal of the dynamic RAM in which the defective word line exists is connected to the redundant relief RAM section 4 via the selection section 6. Connected to the output line. Since the address of the defective chip from the programmable ROM of the comparison unit 3 is supplied to the decoder circuit, the input / output circuit corresponding thereto is activated, and redundancy repair is performed instead of the dynamic RAM in which the defective word line exists. Memory access is performed to the RAM 4 for use.

Programmable ROM constituting the comparison unit 3
In order to perform the write operation to the programmable ROM, in the above write operation to the programmable ROM, eight input circuits of the eight input / output circuits are simultaneously activated and the relief data is input.

In the defect relief LSI of this embodiment, attention is paid to the fact that the memory address of the dynamic RAM inputs the X address and the Y address in a time division manner, and the relief of only the X address is performed. It is a thing. That is, the determination of whether or not the defective word line is repaired is started by inputting the X address, and the time required for the above repair determination is adjusted by utilizing the input of the Y address with a delay. As a result, the defective word line generated in the memory module can be relieved without sacrificing a substantial memory cycle.

FIG. 12 shows a circuit diagram of an embodiment of the sense amplifier used for the read operation of the programmable ROM according to the present invention. In this embodiment, a double-balanced differential sense amplifier is used to increase the gain for a low-amplitude input signal. That is,
Since rewriting is not required unlike a dynamic memory cell, two single-ended differential sense amplifiers are used, one of a pair of input terminals is connected to the data line DL, and the other is supplied with the reference voltage Vref. Then, the complementary output signals of the two single-ended differential sense amplifiers are supplied to the differential amplifier circuit of the output stage. As described above, when the precharge voltage is 2.2V and the half VCC is 1.1V, the reference voltage Vref is set to about 1.65V which is the intermediate value.

When the read operation is not performed as described above,
In order to prevent a DC current from flowing through the sense amplifier, a current source MOSFE that forms the operating current of each differential circuit.
The control signal φpr causes T to be turned off. At this time, in order to prevent the output signal from becoming an indefinite level, a P-channel type MOSFET is provided in the output part, and the output node is fixed to a high level by switch control by the control signal φpr. is there. The output signal Vo is supplied to the comparison circuit CMP through a CMOS inverter circuit, although not particularly limited.

The operational effects obtained from the above embodiment are as follows. That is, (1) a gate is connected to a word line, and one source,
Address selection MOS with drain connected to data line
For a memory cell composed of a capacitor having a thin insulating film as a dielectric connected in series with the FET, the address selecting MOSFET is turned on during a write operation, and a data line is connected to the selected capacitor. A higher voltage is applied to the common electrode of the capacitor than during normal operation to cause dielectric breakdown, and a voltage different from the precharge voltage applied to the data line during read operation is applied to the common electrode of the capacitor to cause data The potential change of the line is sensed by a sense amplifier and used as a programmable ROM. With this configuration, it is possible to obtain an effect that a highly integrated programmable ROM having the same size as the dynamic memory cell can be incorporated in the semiconductor integrated circuit device.

(2) Programmable RO of the above (1)
M is accessed by an X-system address and a Y-system address signal in which a defective cell exists is electrically written R
By placing the programmable ROM above the memory array of the regular circuit adjacent to the X-system selection circuit of the dynamic RAM and used as an OM, the read signal of the programmable ROM and the Y signal can be obtained while greatly simplifying the circuit. If the address signals of the system are compared and they match, Y
By selecting a Y-system redundant circuit in place of the system normal circuit, it is possible to effectively repair a random defect in bit units.

(3) Dynamic RAM in which X-system address signals and Y-system address signals are input in time series
In (2), the X-system address signal and Y
Since the normal circuit is switched to the redundant circuit by using the input time difference between the system address signals, the operation speed can be increased.

(4) The common electrode of the memory cells forming the programmable ROM is set to the same voltage as the selection level of the word line during the write operation, and the data line to be written is set to the ground potential of the circuit. Yes,
The same voltage used for the dynamic RAM can be used as it is by setting the voltage to be half the operating voltage during the read operation and applying the precharge voltage corresponding to the operating voltage to the data line. Since a special power supply circuit is not required, the dynamic type R
An effect that the compatibility with AM can be improved is obtained.

(5) With the programmable ROM, the same address and control input interface unit as the dynamic RAM, and the input / output interface unit corresponding to the data bus of the memory device composed of a plurality of dynamic RAMs, Dynamic type R
A word line is selected by a ROM in which a substantial chip address of AM and a defective address of X system are written, and a comparison match signal between the X address signal fetched by the input interface section and the defective address stored in the ROM. Then, the redundancy relief RAM section for performing column selection by the Y address signal fetched by the input interface section and the data input / output bus of the redundancy RAM section are connected to the input / output circuit corresponding to the defective chip address. Selector to be activated and defective dynamic RA
A data input / output unit for selectively activating an input / output circuit connected to a data bus corresponding to M, and a control signal for setting the output terminal of the defective dynamic RAM to a high impedance state during a read operation. By using it as the ROM in the defect relief semiconductor integrated circuit device including a mask portion for outputting the defect, it is possible to obtain an effect that the defect relief on the memory module can be efficiently performed.

(6) A nonvolatile memory circuit including a normal array in which erasable nonvolatile memory cells are arranged in a matrix and a Y-system redundant array, and the same word line as the memory array of the nonvolatile memory circuit. A ROM in which a memory cell having the same semiconductor structure as the nonvolatile memory cell is provided in a non-erasable state and a Y-system address signal in which a defective cell in the normal array exists is written.
Section, a comparison circuit for comparing a read signal from the ROM section with a Y-system address signal of the nonvolatile memory circuit, and a comparison-match output of the comparison circuit selects a Y-system redundant array instead of the normal array. With such a switching circuit, it is possible to obtain an effect that it is possible to obtain a non-volatile memory device capable of relieving defects in bit units.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the plate electrode of a memory cell used as a programmable ROM is formed separately from the plate electrode of a dynamic RAM, and at the time of a read operation, it is set to the ground potential of the circuit in addition to the half VCC, and the data line The difference from the charge voltage may be increased. By doing so, the read level is increased and the margin with the reference voltage Vref can be increased. As the sense amplifier, a high-sensitivity one as shown in FIG. 12 may be used, or one single-ended differential amplifier circuit shown in FIG. 12 may be configured corresponding to the input signal level. Also, a sense amplifier such as that used in a dynamic RAM may be used. In this case, a dummy cell may be used to form the reference voltage.

Dynamic RA that is the target of defect relief
M is a memory cell that uses a dynamic memory cell as a memory cell, such as a pseudo static RAM having an input / output interface compatible with a static RAM, or serial input / output in an input / output section. It goes without saying that it also includes those having a specific purpose such as image processing for image processing.

Programmable R using a memory cell having the same structure as the dynamic memory cell according to the present invention.
The OM is mounted on the dynamic RAM as described above, or mounted on the defect relief semiconductor integrated circuit device of the dynamic RAM to obtain the dynamic RA.
In addition to the one used for M defect repair, the present invention can be widely used for a programmable RAM embedded in a semiconductor integrated circuit device.

[0073]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, for a memory cell including a capacitor having a thin insulating film as a dielectric, a gate is connected to a word line, and one source and a drain are connected in series to an address selection MOSFET in which a data line is connected. During the write operation, the address selection MOSFET is turned on to apply a higher voltage to the selected capacitor between the data line and the common electrode of the capacitor than in the normal operation to cause dielectric breakdown. In the read operation, a voltage different from the precharge voltage applied to the data line is applied to the common electrode of the capacitor so that the potential change of the data line is sensed by the sense amplifier, which is used as a programmable ROM. With this configuration, a highly integrated programmable ROM having the same size as the dynamic memory cell can be incorporated in the semiconductor integrated circuit device.

The programmable ROM described above is used as a ROM which is accessed by an X-system address and in which a Y-system address signal in which a defective cell exists is electrically written, and a normal type RAM is provided adjacent to the X-system selection circuit of the dynamic RAM. By arranging the programmable ROM on the memory array of the circuit, the circuit is greatly simplified,
By comparing the read signal of the programmable ROM with the Y-system address signal and selecting the Y-system redundant circuit instead of the Y-system normal circuit when they match, random defects in bit units are efficiently relieved. can do.

In the dynamic RAM in which the X-system address signal and the Y-system address signal are input in time series, the normal time is obtained by utilizing the input time difference between the X-system address signal and the Y-system address signal as described above. Since the circuit is switched to the redundant circuit, the operation speed can be increased.

The common electrode of the memory cells forming the programmable ROM is set to the same voltage as the selection level of the word line during the write operation, and the data line to be written is set to the ground potential of the circuit, and the read is performed. In operation, the voltage is set to ½ of the operating voltage, and the data line is provided with a precharge voltage corresponding to the operating voltage, so that the same voltage used in the dynamic RAM can be used as it is. No special power supply circuit is required, and compatibility with the dynamic RAM can be improved.

By the programmable ROM, the same address and control input interface unit as the dynamic RAM, the input / output interface unit corresponding to the data bus of the memory device composed of a plurality of dynamic RAMs, and the dynamic RAM Of the ROM in which the substantial chip address and the defective address of the X system are written, and the word line is selected by the comparison match signal of the X address signal fetched by the input interface section and the defective address stored in the ROM. ,
Redundancy relief RAM in which column selection is performed by the Y address signal fetched by the input interface section
Section, a selecting section for connecting the data input / output bus of the redundant RAM section to an input / output circuit corresponding to the defective chip address, and an input / output connected to the data bus corresponding to the defective dynamic RAM. Defect relief comprising a data input / output unit for selectively activating the circuit and a mask unit for outputting a control signal for bringing the output terminal of the defective dynamic RAM into a high impedance state during a read operation. By using it as the ROM in the semiconductor integrated circuit device for use in the semiconductor device, defect repair on the memory module can be efficiently performed.

A non-volatile memory circuit including a normal array in which erasable non-volatile memory cells are arranged in a matrix and a Y-system redundant array, and the non-volatile memory on the same word line as the memory array of the non-volatile memory circuit. A ROM section in which a memory cell having the same semiconductor structure as the memory cell is provided in a non-erasable state and a Y-system address signal in which the defective cell in the normal array exists is written, a read signal from the ROM section and the above A comparison circuit that compares the Y-system address signal of the non-volatile memory circuit, and a comparison match output of the comparison circuit replaces the normal array with Y
With the switching circuit that selects the redundant array of the system, it is possible to obtain a non-volatile memory device capable of relieving defects in bit units.

[Brief description of drawings]

FIG. 1 is a principal block diagram showing an embodiment of a dynamic RAM in which random defect relief is performed using a programmable ROM according to the present invention.

FIG. 2 is a principal block diagram showing another embodiment of a dynamic RAM in which random defect relief is performed using the programmable ROM according to the present invention.

FIG. 3 shows the dynamic RAM and programmable R
It is a schematic circuit diagram which shows one Example of the memory array of OM.

FIG. 4 is an explanatory diagram showing an example of a write operation and a read operation for a memory cell of the programmable ROM.

FIG. 5 is a configuration diagram for explaining an example of a write operation of the programmable ROM.

FIG. 6 is a schematic cross-sectional view showing one embodiment of the memory cells of the dynamic RAM and programmable ROM.

FIG. 7 is a schematic layout diagram showing an embodiment of the memory cell.

FIG. 8 is a circuit diagram showing an embodiment when the present invention is applied to defect repair of an EPROM.

FIG. 9 is a configuration diagram showing an embodiment of a personal computer system using a semiconductor memory device to which the present invention is applied.

FIG. 10 is a block diagram showing an embodiment of a defect relief LSI using a programmable ROM according to the present invention.

FIG. 11 is a block diagram showing an embodiment of a memory device equipped with the defect relief LSI.

FIG. 12 is a circuit diagram showing an embodiment of a sense amplifier used for the read operation of the programmable ROM according to the present invention.

[Explanation of symbols]

X-AB ... X address buffer, X-DEC ... X decoder circuit, WD ... Word driver, Y-AB ... Y address buffer, Y-DEC ... Y decoder circuit, R-YDEC
... Redundant selection circuits, SELECT, SELECT1,2
... Selector, CMP ... Comparator, PROGRAM ...
Write circuit, SA1, SA2 ... Sense amplifier, RA
RY1 ... First redundant circuit, R-ARY2 ... Second redundant circuit, ROM-ARY ... Programmable ROM, I / O ...
Input / output circuit, CPU ... Central processing unit, DP ... Display, FDD ... Floppy disk drive, FD ... Flappy disk, file M ... File memory, KB
… Keyboard, KBDC… Keyboard controller, H
DD ... Hard disk drive.

Continuation of front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location H01L 21/8246 27/112 27/108 21/8242 // H01L 21/82 H01L 27/10 433 7735-4M 691 21/82 R (72) Inventor Goro Tachibagawa 1-280 Higashi Koikekubo, Kokubunji, Tokyo Inside Hitachi Central Research Laboratory (72) Inventor Takayuki Kawahara 1-280 Higashi Koikeku, Tokyo Kokubunji City Inside Hitachi Research Center (72) Inventor Hidetoshi Iwai 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd.

Claims (6)

[Claims] 1. An address selection MOSFET having a gate connected to a word line and one source and drain connected to a data line, and a capacitor having a thin insulating film as a dielectric connected in series with the MOSFET. In the write operation, a high voltage is provided between the data line and the common electrode of the capacitor for the selected capacitor by turning on the address selecting MOSFET during the write operation. Programmable ROM in which a voltage different from the precharge voltage applied to the data line is applied to the common electrode of the capacitor during the read operation so that the potential change of the data line is sensed by the sense amplifier.
A semiconductor integrated circuit device comprising: 2. The programmable ROM is adapted to be accessed by an X-system address signal of a dynamic RAM formed on the same semiconductor substrate to write a Y-system address signal having a defective cell, The read signal of the programmable ROM and the Y-system address signal of the dynamic RAM are compared by the comparison circuit, and the dynamic type R is output by the comparison coincidence output.
2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is used to select a Y-system redundant circuit in place of the Y-system normal circuit in AM. 3. The memory cell of the programmable ROM has the same structure as the memory cell of the dynamic RAM, and is commonly connected to a word line selected by an X-system address selection circuit of the dynamic RAM. The semiconductor integrated circuit device according to claim 2, wherein the semiconductor integrated circuit device is a device. 4. The common electrode of the memory cells constituting the programmable ROM is set to the same voltage as the selection level of the word line in the write operation, and the data line to be written is set to the ground potential of the circuit. 2. The read operation, the common electrode is set to ½ of the operating voltage, and the data line is given a precharge voltage corresponding to the operating voltage. The semiconductor integrated circuit device according to claim 2 or claim 3. 5. The programmable ROM comprises the same address and control input interface section as the dynamic RAM, an input / output interface section corresponding to a data bus of a memory device composed of a plurality of dynamic RAMs, and a dynamic interface. ROM in which the substantial chip address of the type RAM and the defective address of the X system are written, and the word line is generated by the comparison match signal of the X address signal fetched by the input interface section and the defective address stored in the ROM. A redundant relief RAM unit that is selected and performs column selection by the Y address signal taken in by the input interface unit, and a data input / output bus of the redundant RAM unit is used as an input / output circuit corresponding to a defective chip address. The selection part to be connected, and the The data input / output unit that selectively activates the input / output circuit connected to the data bus corresponding to the dynamic RAM, and the output terminal of the defective dynamic RAM are set to the high impedance state during the read operation. 2. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is used as the ROM in a defect relief semiconductor integrated circuit device comprising a mask section for outputting a control signal for controlling the defect. 6. A non-volatile memory circuit including a normal array in which erasable non-volatile memory cells are arranged in a matrix and a Y-system redundant array, and the same word line as the memory array of the non-volatile memory circuit. A ROM section in which a memory cell having the same semiconductor structure as the nonvolatile memory cell is provided in a non-erasable state and a Y-system address signal in which the defective cell in the normal array exists is written,
A comparison circuit for comparing the read signal from the ROM section with the Y-system address signal of the nonvolatile memory circuit, and a switching circuit for selecting a Y-system redundant array instead of the normal array by the comparison match output of the comparison circuit. A semiconductor integrated circuit device comprising: