KR100349510B1 - Phase lock loop module for a combined use of difference frequency - Google Patents

Abstract

The present invention provides an oscillator for generating a constant frequency signal of a specific frequency band, a dual voltage controlled oscillator for generating different heterogeneous reference frequencies corresponding to a voltage input by a user's selection or system control signal, and a dual voltage. The present invention relates to a dual frequency controlled oscillator module having a PLL that receives a reference frequency generated from a control oscillator and a frequency signal generated from an oscillator and changes a magnitude of a voltage applied to a dual voltage controlled oscillator. A reference frequency oscillator for generating and outputting a DCS oscillation frequency signal according to a system control signal or multiplying and outputting the generated DCS oscillation frequency signal, an amplifier for firstly amplifying and outputting the output of the reference frequency oscillator; Receives the output signal from the amplifier and re-amplifies P PCS amplification unit for generating a reference frequency for CS, DCS amplifier for generating a reference frequency for the DCS by receiving the output signal of the amplification unit, and a pad unit for receiving the output signal of the amplification unit and delivered to the PLL side By providing a heterogeneous frequency-locked phase-locked loop module that multiplies the DCS reference frequency by a simple method of packaging the PLL module or semiconductor chip, the number of transistors that occupy the most space is basically used. Minimize the effect.

Description

Phase lock loop module for a combined use of difference frequency}

The present invention provides a PLL (Phase Lock Loop) that can be used in both a Digital Cellular System (hereinafter referred to as DCS) terminal and a Personal Communication System (hereinafter referred to as PCS) terminal serviced in a mobile communication system. The reference frequency of the PLL) method is related to the generator. Especially, in order to reduce the size of the device and to reduce the production cost, the two frequency controlled oscillators provided for each frequency are combined into one and returned to the PLL circuit side. The present invention relates to a heterogeneous frequency-locked phase locked loop module that simultaneously generates a signal.

In general, the digital method of the existing DCS uses the CDMA method like the PCS, the biggest difference in the hardware implementation of the DCS and PCS is that the frequency band and the channel spacing is different. That is, the channel spacing of the DCS is 30 kHz, the channel spacing of the PCS is 50 kHz, and the reference frequencies of each PLL use 19.68 MHz (30 kHz × 656) and 24.6 MHz.

However, there has been a case in which the same terminal should be used as a PCS or a DCS according to local characteristics or user needs. In this case, a technical necessity arises that one terminal needs a PLL module capable of satisfying all of the heterogeneous use frequencies as described above.

Accordingly, the conventional PLL module proposed by the above technical necessity has a PLL module (hereinafter referred to as a "dual PLL module") for generating a separate reference frequency, as shown in FIG. .

That is, it includes a DCS-related PLL module corresponding to the reference numerals 10a, 20a, and 30a and a PCS-related PLL module corresponding to the reference numerals 10b, 20b, and 30b, so as to control the microprocessor according to a user's selection mode or a specific operating method. In this case, when used as a DCS terminal, the frequency generated by the D-VCO 30a, which is a DSC VCO, is used as a reference frequency, and when used as a PCS terminal, the frequency generated by the P-VCO 30b, which is a PCO VCO, is used. It was used as a reference frequency.

At this time, the D-VCO 30a and the P-VCO 30b have the same structure, as shown in FIG. 2 attached in hardware.

The voltage controlled oscillator shown in FIG. 2 is largely comprised of the reference frequency oscillator 31, the negative feedback resistor 32, and the amplifier 33. As shown in FIG.

Among the components, the reference frequency oscillator 31 has a first coil L1 having one end connected to an input terminal In and receiving a control voltage generated from a PLL connected to the input terminal In, and the first coil L1. The cathode terminal is connected to the other end of L1), and the anode terminal is connected to the ground terminal, and the first and second capacitors are connected in series and are connected in parallel with the varactor diodes (VD). A second coil L2 having one end connected to a connection point of the two capacitors C1 and C2, the first capacitor C1 and the second capacitor C2, and the other end connected to the ground terminal, and the first capacitor. And a third capacitor C3 having one end connected to the connection point of the C1 and the second capacitor C2.

In addition, the amplifier 33 receives the first transistor Q1 receiving an arbitrary positive voltage Vcc through the third coil L3 and the positive voltage applied to the third coil L3. A first resistor C4 charged by Vcc and a voltage applied to the third coil L3 are received at one end and the other end thereof is connected to the base terminal of the first transistor Q1. R1), a fifth capacitor C5 connected to the base terminal and the ground terminal of the first transistor Q1 and charged by a voltage output through the first resistor R1, and the first transistor C1. The second transistor Q2 having the collector terminal connected to the emitter terminal of Q1), the sixth capacitor C6 charged by the voltage applied to the collector terminal of the second transistor Q2, and the first transistor The second resistor R2 is connected to the base terminal of Q1 and the base terminal of the second transistor Q2. It consists of.

Finally, the negative feedback resistor unit 32 includes a seventh capacitor C7 connected to the base terminal and the emitter terminal of the second transistor Q2, and the base terminal and the ground terminal of the second transistor Q2. A third resistor R3 connected therebetween, an eighth capacitor C8 charged by a voltage applied to an emitter terminal of the second transistor Q2, and an eighth capacitor C8 in parallel; The fourth resistor R4 forms a discharge path of the voltage charged in the eighth capacitor C8.

Therefore, the operation of the conventional dual PLL module illustrated in FIG. 1 or 2 will be briefly described as follows.

First, assuming that only the PCS related part operates, a control voltage output from the P-PLL 20b is applied to the input terminal In of the P-VCO 30b.

In this case, LC resonance is performed by the second capacitor C2 and the second coil L2 only when the control voltage flowing through the input terminal In is greater than or equal to the threshold voltage of the varistor diode VD. A specific frequency corresponding to the intrinsic value of the C2 and the second coil L2 and the magnitude of the applied voltage is generated.

Accordingly, the resonance frequencies of the second capacitor C2 and the second coil L2, which are components of the reference frequency oscillator 31, of the first and second transistors Q1 and Q2 of the amplifier 33 are formed. It is caught by the base terminal, and the first and second transistors Q1 and Q2 are turned on / off according to the voltage state of the resonance frequency applied to the base terminal.

Therefore, the output terminal (Out) connected to the collector terminal of the first transistor (Q1) during the on / off operation of the first and second transistors (Q1, Q2), the first frequency of the reference frequency oscillator (31) The resonance frequency generated by the two capacitors C2 and the second coil L2 is amplified and output.

At this time, since the operation as described above occurs in the D-VCO 30a in the conventional dual PLL module, the switching unit 40 actually generates and inputs both the DCS reference frequency and the PCS reference frequency.

Therefore, in this situation, the user outputs any one reference frequency by operating the switching unit 40 while both the DCS reference frequency and the PCS reference frequency are generated. It will be available for PCS.

However, the conventional dual PLL module as described above has hardware redundancy and its volume is large, and thus technically includes a limitation in satisfying the consumer's taste that is gradually reduced in size and weight.

In addition, the use of redundant hardware also increases the cost of production.

In addition, since the conventional dual PLL module had to provide an additional circuit to detect the signal tracked to the PLL side, it was not suitable both in terms of production cost and signal stability described above.

An object of the present invention for solving the above problems is to combine the two voltage control oscillators provided for each frequency into one in order to reduce the size of the device and to reduce the production cost at the same time and simultaneously generate a signal for feedback to the PLL circuit side The present invention provides a PLL type dual frequency phase locked loop module that can be used in both a DCS terminal and a PCS terminal.

1 is a block diagram illustrating a conventional phase locked loop module in a dual frequency wireless communication system;

2 is an exemplary circuit configuration of the voltage controlled oscillator shown in FIG.

3 is an exemplary block diagram of a phase locked loop module according to the present invention;

4 is an exemplary circuit configuration of the voltage controlled oscillator shown in FIG.

5A and 5B are exemplary diagrams of spectra of a frequency signal finally output according to the operation of the switching filter shown in FIG.

A feature of the present invention for achieving the above object is to generate an oscillator for generating a constant frequency signal of a specific frequency band, and to generate different heterogeneous reference frequencies corresponding to a voltage input by a user's selection or a system control signal. A dual voltage controlled oscillator having a dual voltage controlled oscillator and a PLL that receives a reference frequency generated by the dual voltage controlled oscillator and a frequency signal generated by the oscillator and changes a magnitude of a voltage applied to the dual voltage controlled oscillator A synchronous loop module, comprising: a reference frequency oscillator configured to generate and output a DCS oscillation frequency signal by a system control signal, or to multiply and output the generated DCS oscillation frequency signal; An amplifier for first amplifying and outputting the output of the reference frequency oscillator; An amplifying unit for the PCS which receives the output signal of the amplifying unit and re-amplifies and generates a reference frequency for the PCS; A DCS amplifier for generating a DCS reference frequency by receiving and re-amplifying the output signal of the amplifier; And a pad unit receiving the output signal of the amplifying unit and transferring the output signal to the PLL side.

The above objects and various advantages of the present invention will become more apparent from the preferred embodiments of the invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram illustrating a concept of a phase locked loop module according to the present invention, and FIG. 4 is a circuit diagram illustrating a voltage controlled oscillator according to the present invention.

As shown in FIG. 3, the present invention includes a dual voltage controlled oscillator for generating a voltage reference oscillator with a different reference frequency according to a selection signal, and voltage control by a user's selection or a system control signal. The oscillator 300a is switched to a DCS related mode or a PCS related mode, and receives a reference frequency control voltage output from the PLL 200 to generate a reference signal suitable for the converted mode.

At this time, the voltage-controlled oscillator 300a generates a primary frequency related to DCS or PCS according to the input system control signal, and the DCS-related secondary amplifier 300c and PCS-related secondary amplifier 300b and the PLL. It will be delivered to (200).

The DCS related secondary amplifier 300c amplifies and outputs the frequency signal output from the voltage controlled oscillator 300a according to a normal amplification operation, but the PCS related secondary amplifier 300b controls the voltage. The frequency signal output from the oscillator 300a is multiplied and then amplified and output.

The reason is that in the case of DCS, the frequency band is about 900 MHz, while in the case of PCS, it is about twice as much as about 1.8 GHz.

Therefore, when the multiplication means is added to the VCO for generating the reference frequency for the DCS, it is possible to easily obtain a heterogeneous reference frequency.

4 is a circuit diagram illustrating the concept of the phase-locked loop module according to the present invention as a circuit.

4 is an exemplary circuit configuration of a voltage controlled oscillator according to the present invention, which generates and outputs a DCS oscillation frequency signal by a system control signal, or a reference frequency oscillator for multiplying and outputting the generated DCS oscillation frequency signal ( 31a), an amplifier 32a for first amplifying and outputting the output of the reference frequency oscillator 31a, and a PCS for receiving and re-amplifying the output signal of the amplifier 32a to generate a reference frequency for the PCS. The amplifier 32b, the DCS amplifier 32c for generating a DCS reference frequency by re-amplifying the output signal of the amplifier 32a, and the output signal of the amplifier 32a. It is composed of a pad part (not given a reference number) to be received and delivered to the PLL side.

At this time, in addition to the above configuration, the first negative feedback resistor 33a for maintaining the amplification operation of the amplifier 32a and the second negative feedback for maintaining the amplification operation of the PCS amplifier 32b. A resistor 33b and a third negative feedback resistor 33c for maintaining the amplification operation of the DCS amplifier 32c are further configured.

Looking at the configuration of the main summary of the configuration, the main portion corresponds to the reference frequency oscillator 31a, the reference frequency oscillator 31a is connected to the input terminal (In), one end is connected to the input terminal (In) A first coil L1 receiving the control voltage generated from the PLL, a cathode terminal connected to the other end of the first coil L1, an anode terminal connected to a ground terminal, and two capacitors; Are connected in series and connected to the connection points of the second and third capacitors C2 and C3 and the second capacitor C2 and the third capacitor C3 which are generally connected in parallel with the varactor diode VD. And a second coil L2 having the other end connected to the ground terminal, and a fourth capacitor C4 having one end connected to the connection point of the second capacitor C2 and the third capacitor C3, It is generally in contact with the system control signal input Two resistors Ra and Rb connected between the terminals, a diode Da having an anode terminal connected to the connection point of the resistors Ra and Rb and one end of the second coil L2 in common; The coil La is connected between the cathode terminal of the diode Da and the ground terminal, and the capacitor Ca is connected in parallel with the coil La.

Since the other than that structure is a normal structure, detailed description is abbreviate | omitted.

In addition, FIGS. 3 and 4 of the present invention represent the same technical idea, and FIG. 3 is a schematic representation of the technical idea of FIG. 4 so that the block structure of FIG. 3 exactly matches the circuit of FIG. 4. Make it clear.

Looking at the operation of the voltage controlled oscillator during the operation of the PLL module having a voltage controlled oscillator according to the present invention configured as described above, the control voltage output from the PLL (200) flowing through the input terminal (In) is a varistor diode Only when the voltage is equal to or greater than the threshold voltage of VD, LC resonance is performed by the third capacitor C3 and the second coil L2, and the intrinsic value of the third capacitor C2 and the second coil L2 and the applied voltage A specific frequency corresponding to the magnitude is generated.

At this time, if the system controller wants to use the system as a DCS, the system control signal is maintained at a high state.

Therefore, the divided voltage is kept high through the resistors indicated by reference numerals Ra and Rb, so that the frequency signal oscillated by the third capacitor C2 and the second coil L2 is changed without any change. It is transmitted to the amplification part 32a of the rear end via the capacitor C4.

On the other hand, when the system controller wants to use the system as a PCS, the system control signal is kept low.

Therefore, the divided voltage is kept low through the resistors indicated by reference numerals Ra and Rb, and thus the frequency signal oscillated by the third capacitor C2 and the second coil L2 is connected to the diode Da. It is applied to the coil La and the capacitor Ca through. Accordingly, the coil La and the capacitor Ca oscillate by the input frequency signal to multiply the input frequency signal.

The frequency signal multiplied by the coil La and the capacitor Ca is again applied to the fourth capacitor C4 through the diode Da, and the fourth capacitor C4 receives the received frequency signal. It is delivered to the amplification part 32a side of a rear end.

The subsequent operation is used as a reference frequency signal suitable for the mode selected by the system controller by the switching path control of FIG. 3.

In addition, parts indicated by reference numerals L11a and C11a are configurations for reducing external noise, and parts denoted by reference numerals L11b and C11b are used to provide signal components of the PCS frequency band to a device at a later stage through an output (Out). As part, it is for selecting the second frequency band of the output frequency as shown in the accompanying FIG. 5B reference.

While the invention has been shown and described in connection with specific embodiments thereof, it will be appreciated that various modifications and changes can be made without departing from the spirit and scope of the invention as indicated by the claims. Anyone who owns it can easily find out.

A device that occupies the most space in the work of packaging a PLL module or a semiconductor chip by a simple method of multiplying the DCS reference frequency by providing a heterogeneous frequency-locked phase-locked loop module according to the present invention operating as described above. Minimization is possible by minimizing the number of phosphorus transistors.

Claims (3)

An oscillator for generating a constant frequency signal of a specific frequency band, a dual voltage controlled oscillator for generating different heterogeneous reference frequencies corresponding to a voltage input by a user's selection or system control signal, and the dual voltage controlled oscillator In the heterogeneous frequency-locked phase-locked loop module having a PLL for receiving a reference frequency generated by and a frequency signal generated by the oscillator to vary the magnitude of the voltage applied to the dual voltage controlled oscillator: The dual voltage controlled oscillator, A reference frequency oscillator for generating and outputting a DCS oscillation frequency signal by a system control signal or multiplying and outputting the generated DCS oscillation frequency signal; An amplifier for first amplifying and outputting the output of the reference frequency oscillator; An amplifying unit for the PCS which receives the output signal of the amplifying unit and re-amplifies and generates a reference frequency for the PCS; A DCS amplifier for generating a DCS reference frequency by receiving and re-amplifying the output signal of the amplifier; And And a pad unit configured to receive an output signal of the amplification unit and transfer the output signal to the PLL side. The method of claim 1, A first negative feedback resistor unit for maintaining an amplification operation of the amplification unit, a second negative feedback resistor unit for maintaining an amplification operation of the amplification unit for the PCS, and amplification operation of the amplification unit for the DCS unit And a third negative feedback resistor unit. The method of claim 1, The reference frequency oscillator comprises: a first coil having one end connected to an input terminal and receiving a control voltage generated from a PLL connected to the input terminal; A varistor diode having a cathode terminal connected to the other end of the first coil and an anode terminal connected to a ground terminal; Second and third capacitors in which two capacitors are connected in series and are connected to the varactor diode in parallel; A second coil having one end connected to the connection point of the second capacitor and the third capacitor and the other end connected to the ground end; A fourth capacitor having one end connected to a connection point of the second capacitor and the third capacitor; Two resistors Ra and Rb connected in series and connected between the system control signal input terminal and the ground terminal as a whole; A diode having an anode terminal connected to a connection point of the resistors Ra and Rb of the donor and one end of the second coil in common; A coil connected between the cathode terminal of the diode and a ground terminal; And The dual phase frequency loop module, characterized in that consisting of a capacitor connected in parallel to the coil.