KR100348263B1 - apparatus for digital interface - Google Patents

Abstract

The present invention is to provide a digital interface device that transmits and receives by reconstructing a continuous data value when a discontinuity occurs in transmitting MPEG2 signals using a 1394 interface to a system, and decodes and synchronizes a specific channel selected by a tuner. A VSB (Vestigial-Side Band) section for performing detection, a formatter section for restoring a format of a first signal transmitted from the VSB section or a second signal transmitted through an external cable to a predetermined format, and the formatter A selection unit for selecting and outputting any one of a second signal restored through the unit and a signal received through the VSB unit, and a display unit for extracting, restoring, and displaying a single program transport stream from the signal output from the selection unit; Can display a clear screen without deterioration of image quality. .

Description

Apparatus for digital interface

The present invention relates to an interface device, and more particularly, to an apparatus for transmitting an MPEG2 transport stream in a system in which signal discontinuity is generated.

In the rapidly developing electronic communication, high speed transmission between digital electronic devices is required. Accordingly, the use of the IEEE 1394 serial bus has been recently applied in various fields for high speed transmission between digital electronic devices.

In this IEEE 1394 serial bus protocol, isochronous transmission proceeds first according to cycle synchronization of 8 KHz, and then asynchronous data transmission proceeds after a predetermined gap.

Therefore, the isochronous transmission, in which a predetermined channel is allocated and periodically transmitted, is used for transmission of data in which timing is important, such as a video signal or an audio signal, and the asynchronous transmission capable of retransmission and reception through an acknowledgment (ACK). Is used to transmit and receive data that must be guaranteed that data is received safely.

When the IEEE 1394 interface, which is emerging as an interface method between digital devices, is applied to STB (Set Top Box) and DTV, the VSB (Vestigial-Side Band) output format in DTV can be directly received by 1394 LLC. If the output is not a problem, in other cases, the signal discontinuity must be compensated for by using a separate formatter according to the signal format.

FIG. 1 is a diagram illustrating devices connected by a 1394 serial interface between a digital STB (D_STB) 1, a digital TV (DTV) 2, and a digital video cassette recorder (DVCR) 3.

2 shows an internal configuration diagram of a DTV system in which a general D_STB or tuner 10 is embedded.

Referring to FIG. 2, a tuner unit 10 that receives an RF signal and filters a signal of a specific frequency band, and VSB (Vestigial) which decodes a specific channel selected by the tuner unit 10 and performs synchronous detection A side band unit 20, a TP demux unit 30 which extracts a single program transport stream from the MPEG2 transport stream output from the VSB unit 20, and the TP demux unit 30 are selected. A Moving Picture Experts Group Decoder (40) for decoding MPEG2 data having a single PID (Protocol IDentifier), and a video display unit (50) supporting various video display formats by inputting the decoded MPEG2 data; And a CPU 60 that performs and controls mutual communication with each component.

However, when the VSB output type meets a field sync interval, the digital interface device according to the related art described above is divided into several byte data. When the separated data signal is directly transmitted and received through the 1394 interface, In the DTV on the receiving side, a problem of uneven display is generated.

Accordingly, the present invention has been made to solve the above problems, and when a discontinuity occurs in the transmission of the device and the MPEG2 signal applying the 1394 interface to the system as described above to restore the continuous data value to transmit and receive digital The purpose is to provide an interface device.

1 is a view connecting a 1394 serial interface between D_STB, DTV, and DVCR.

2 is a diagram illustrating an internal configuration of a DTV system in which a general D_STB or tuner 10 is incorporated.

3 is a block diagram of a digital interface device to be implemented in the present invention.

4 is a block diagram showing an operation of a formatter unit according to the present invention.

* Explanation of symbols for main parts of the drawings

10: Tuner 20: VSB Part

30: TP demux portion 40: MPEG decoder portion

50: VDP section 60: CPU

70: selector 80: formatter

90: LLC part 100: PHY part

200: memory 270: musbu

A feature of the digital interface device according to the present invention for achieving the above object is a VSB (Vestigial-Side Band) section for decoding a specific channel selected by the tuner and performing synchronous detection, and transmitted from the VSB section A formatter unit for restoring a format of a first signal or a second signal transmitted through an external cable to a predetermined format, and selecting and outputting any one of a second signal restored through the formatter unit and a signal received through the VSB unit And a display unit for extracting, restoring, and displaying a single program transport stream from the signal output from the selector.

Another feature of the present invention is to select and transmit any one of the received MPEG2 data and the output data of the VSB unit.

According to still another aspect of the present invention, an adder for adding an enable signal, a clock, and field synchronization, which are output signals of the VSB unit, and a memory for writing / reading broadcast data using the signal generated by the adder, And a first enable generator configured to generate an enable signal for writing / reading the memory using the signal generated by the adder, and data stored in the memory according to a signal output from the enable generator. And a second enable generator configured to selectively output a multiplex unit and a enable signal indicating an effective range of the final data output value using the read enable signal output from the enable generator.

According to an aspect of the present invention, by restoring the MPEG2 data output in a discontinuous form in a specific section using a formatter before transmission and then transmitting the same to the 1394 interface LLC, the viewer can view a clean picture without deterioration of image quality. .

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

A preferred embodiment of the digital interface device according to the present invention will be described below with reference to the accompanying drawings.

3 is a block diagram of a digital interface device to be implemented in the present invention.

Referring to FIG. 3, a tuner unit 10 for receiving an RF signal and filtering a signal of a specific frequency band, and VSB (Vestigial) for decoding a specific channel selected by the tuner unit 10 and performing synchronous detection Side Band unit 20, a CPU 60 for performing and controlling communication with each component, and a first signal transmitted from the VSB unit 20 or a second signal transmitted through an external cable A formatter unit 80 for restoring a format of the format to the corresponding format, a second signal restored through the formatter unit 80 by receiving a control signal from the CPU 60, and a signal received through the VSB unit 20; A selector 70 for selecting and outputting any one of them, a TP demux 30 for extracting a single program transport stream from the MPEG2 transport stream output from the selector 70, and the TP demux part Decode MPEG2 data with a single PID selected in 30. Consists of the MPEG decoder unit (Moving Picture Experts Group Decoder) (40), and a video display unit (50) to support a variety of video display formats the decoded MPEG2 data as input.

In addition, the PHY (Physical Layer) unit 100 is physically connected to the external cable between the external cable and the formatter unit 80, and generates a data packet for an interface, and checks various protocols through mutual communication with the CPU. It consists of a LLC (Link Layer Controller) unit 90 for holding.

Looking at the operation of the digital interface device according to the present invention configured as described above in detail as follows.

First, the VSB unit 20 decodes a specific channel selected by the tuner unit 10, detects a single channel, and transmits the detected channel to the selection unit SEL 70, or a formatter unit (for a 1394 interface). 80).

Subsequently, the formatter unit 80 transmits a signal transmitted from the VSB unit 20 to an external display device through the 1394 interface, or when receiving the MPEG2 data transmitted through the 1394 interface from the outside, Convert data with other formats into the correct format for your system.

Because MPEG2 data received from the outside is usually transmitted in DVB (Digital Video Broadcasting) format, when the field sync interval is met, 188 bytes of data are not transmitted in the form of continuous data during that interval, but are separated into 96 bytes and 92 bytes. do.

When the DTV receives the data format through the 1394 interface, the displayed screen does not display a normal video and displays a broken screen.

Therefore, in order to solve this problem, a separate formatter unit 80 is provided to convert discontinuous data into restored continuous data.

Next, the selector 70 receives a control signal from the CPU 60 and selects whether to transmit a signal received through the 1394 interface or a signal output from the VSB unit 20 to select one of the signals. send.

The LLC (Link Layer Controller) unit 90 generates a data packet for the 1394 interface, and also identifies and maintains various protocols through mutual communication with the CPU 60.

In addition, the physical layer (PHY) unit 100 maintains a physical connection with other nodes on a 1394 bus and is responsible for data transmission / reception on a 1394 bus.

The operation of the formatter in the present invention configured as described above will be described in detail with reference to the accompanying drawings.

4 is a block diagram showing an operation of a formatter unit according to the present invention.

Referring to FIG. 4, first, the output of the VSB unit 20 includes data (7: 0), an enable signal indicating an effective range of data values, and a clock (CLK) as a reference for the data and the VALID signal. ) And PSYNC, which is a field synchronization constituting a VSB data frame, is applied to the formatter unit 80.

Then, the formatter unit 80 recovers the synchronization section to compensate for this, since the output data of the VSB unit 20 meets the field synchronization section.

The reconstruction adds the VALID signal, the inverted sync signal PSYNC, and the original sync signal PSYNC.

In this case, since the synchronization period to be restored does not coincide with the time point at which the actual data is separated, the time point at which the data is separated is completely covered by adding a clock obtained by increasing the main clock by six times.

The signal generated through the addition is used to write / read to the memory. In this case, the dual port SRAM (MEM) 200 is divided into two memories A and B.

First, the memory B reads while writing data to the memory A, and the memory A reads while writing the data to the memory B, and thus, it is possible to output continuous data values which are perfectly restored even when the data is separated. have.

Therefore, with the restored VALID signal, the address pointer WR_ADDR 110, which is first written to the memory, is generated using the counter value.

At this time, the address pointer value WR_ADDR 110 and the timing at which the actual data are stored in the memory 200 do not coincide with each other, so the timing pointer delay unit A_DELAY 130 adjusts the timing.

In addition, an enable signal for memory A and memory B is generated with a VALID signal. First, VSBSEL_A 120 and VSBSEL_B 140 are made with each memory selection signal, and then each memory A is considered in consideration of timing. In addition, the write enable signals B_WE 150 and A_WE 160 necessary for the memory B are generated and input to the memory 200.

The logic is then designed so that all operations operate at the clock rising edge and the enable signal is high.

This ensures more stable operation.

Subsequently, the data (7: 0) input from the VSB unit 20 to the formatter unit 80 is controlled by the D_Delay unit 190 to synchronize with the generated enable signals B_WE 150 and A_WE 160. The memory 200 is input to the memory 200 accordingly.

The data stored in the memory 200 is read at a location stored by the read address pointer RD_ADDR 180, where the read address pointer RD_ADDR 180 receives the same VALID signal used when creating the write address pointer WR_ADDR 110. Create by counting

In addition, since the read address pointer RD_ADDR 180 also has a valid value according to the read enable signal, the A_Delay unit 190 applies the timing to the memory 200 at a timing.

In addition, enable signals LLCEN_S1 210 and LLCEN_S2 210 necessary for reading memory A and memory B using the VALID signal are generated, and respective selection signals LLCSEL_A 230 and LLCSEL_B 240 are made in consideration of timing. .

In this case, the selection signal LLCSEL_A 230 is a signal generated by receiving the inverter signal of the enable signal LLCEN_S1 210, and the selection signal LLCSEL_B 240 is generated by receiving the signal of the enable signal LLCEN_S1 210. It is a signal.

The enable signal LLCEN_S2 220 is added to the generated select signals LLCSEL_A 230 and LLCSEL_B 240 to generate an enable signal B_RE 250 and an A_RE 260 for a final memory read, respectively, to generate a read enable signal. To the memory 200 as an example.

Data stored by the read enable signal B_RE 250 and A_RE 260 and the address pointer RD_ADDR 180 are output. The output data values are stored in the memory A and the memory through a multiplexer (MUX) 270. Each of them is selected in the order in which they were stored in B and output to the LLC unit 90.

The output data is synchronized with a clock rising (LATCH) 280 to output data (7: 0).

In addition, the read enable signal B_RE 250 and A_RE 260 are added, and the clock rising signal is synchronized (LATCH) 290 to output the enable signal Data_valid indicating the effective range of the final data output value to the LLC unit 90. do.

The digital interface device according to the present invention as described above has the following advantages.

First, by extracting the signal selection position from the VSB unit and transmitting the DVB data format as it is, a screen different from that displayed on the DTV can be transmitted and recorded to the DVCR (Digital Video Cassette Recorder) through the 1394 interface.

Second, if there is a discontinuity of the MPEG signal, it can be applied to a digital STB or a DTV with a tuner to display a clear screen with no breakage of image quality.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (6)

A VSB (Vestigial-Side Band) section that decodes a specific channel selected by the tuner and performs synchronous detection, A formatter unit for restoring a format of the first signal transmitted from the VSB unit or the second signal transmitted through an external cable to a predetermined format; A selection unit for selecting and outputting any one of a second signal restored through the formatter unit and a signal received through the VSB unit; A TP demux unit for extracting a single program transport stream from the MPEG2 transport stream output from the selecting unit; An MPEG decoder which decodes MPEG2 data having a single PID selected by the TP demux; And a video display unit which supports various video display formats as the decoded MPEG2 data as an input. delete The method of claim 1, wherein the signal output from the VSB unit Broadcast Data, An enable signal representing a valid range of data, A clock that is a reference of the enable signal, and And a field synchronization constituting a data frame of a VSB unit to transmit to the formatter unit. The method of claim 3, wherein An adder for adding the enable signal, a clock, and field synchronization; A memory for writing / reading broadcast data using the signal generated by the adder; A first enable generator configured to generate an enable signal for writing / reading the memory using the signal generated by the adder; A multiplex unit selectively outputting data stored in the memory according to a signal output from the enable generator; And a second enable generator configured to output an enable signal indicating an effective range of a final data output value by using the read enable signal output from the enable generator. The method of claim 4, wherein And said memory comprises a first memory and a second memory for intersecting reads and writes of data. The method of claim 3, wherein And the clock increases the main clock by six times.