JP2002353920A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To insert a DIT to a partial TS with proper timing. SOLUTION: When generating the DIT and inserting it to the partial TS, the DIT is generated by a DIT inserting processing part 6 which is configured as hardware and as soft ware processing by a system controller 11; and in such a case, timing for insertion of the DIT is instructed. Thus, functions are selectively used for hardware and software, when generating/inserting the DIT, so that the DIT can be generated/inserted to the partial TS extremely at much higher speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to stream data such as a transport stream for transmitting program data in digital satellite broadcasting, for example, IEEE 1
The present invention relates to a data processing device for transmitting data via a predetermined data bus conforming to a standard such as a 394 data interface.

[0002]

2. Description of the Related Art In recent years, digital satellite broadcasting has been widely used. Digital satellite broadcasting is more resistant to noise and fading than, for example, existing analog broadcasting, and can transmit high-quality signals. Further, the frequency use efficiency has been improved, and multi-channels have been realized.

[0003] Under the current standard of such digital satellite broadcasting, video data and audio data as a program (program) are MPEG (Moving Pictur).
e Experts Group) 2. Then, the data of the compression-encoded program is multiplexed with various types of additional information such as program information and reception-limited information, and is called a so-called transport stream (hereinafter also referred to as TS (TransportStream)). The data is transmitted in the form of stream data.

[0004] By connecting a digital satellite broadcast receiver to a digital storage device such as a digital VTR or an HDD (hard disk), a program received by the digital satellite broadcast receiver can be transferred to a digital storage device in the form of a TS. It is proposed to configure the system so that it can be forwarded and recorded,
It has been realized. With such a system,
Since the received program data is recorded in a compressed and encoded state without demodulation, the signal processing for recording becomes efficient, and the image quality and sound quality of the reproduced program are also reduced. Degradation is avoided. Furthermore, it is a feature in digital satellite broadcasting,
Since various types of additional information are also recorded, if these additional information are used at the time of reproduction, it is possible to obtain a more complete reproduction function.

At present, IEEE (Ins.) Is used as a digital data interface for connecting the digital satellite broadcast receiver and the digital storage device.
One employing a 1394 data interface has been known. IE
The EE1394 data interface is, for example, SCS
The data transfer rate is faster than I or USB,
As is well known, Isochronous communication that ensures that a required data size is periodically transmitted and received is enabled. For this reason, the IEEE 1394 data interface is advantageous for transferring stream data such as AV (Audio / Video) in real time.

In practice, for a TS transmitted from, for example, a digital satellite broadcast receiver to a digital storage device via an IEEE 1394 bus, information on a specific program is selected from the received original TS. The stream data extracted as described above is called partial TS.

[0007] By the way, for example, the continuity of the partial TS may be lost due to, for example, a change in the content due to the switching of the reception channel, a failure to receive the signal due to the deterioration of the reception condition and the interruption of the received radio wave. When transmitting a partial TS having discontinuity in this manner, DIT (Discontinuity Inf
It is stipulated by the standards that an ormation table) should be inserted at the discontinuous position of the partial TS. DI
T is additional information indicating that a discontinuity has occurred in the partial TS based on a predetermined condition and a position where the discontinuity has occurred, and has a predetermined packet data structure.

Conventionally, the processing for inserting the DIT into the partial TS has been performed, for example, as follows. Additional information as packet data to be inserted into the partial TS is, for example, DI
In addition to T, PAT, PMT, SIT and the like are defined. Here, the additional information (P
AT, PMT, SIT) are not described. Therefore, for example, in a device on the transmission side, the additional information is generated by software processing as necessary, and inserted into the partial TS at a required timing. That is, the DIT is generated and inserted by software processing, like other additional information.

[0009]

The DIT is used, for example, by a device receiving a partial TS to identify a discontinuous position and perform decoding. For proper decoding, the DIT insertion timing is important. For example, it is required that the time interval from the occurrence of a discontinuous position to the insertion of the DIT is within an allowable range. However, when the DIT is generated by software processing as described above, the processing load is very heavy and the processing becomes slow. For this reason, it is difficult to generate and insert a DIT at a sufficiently fast timing that falls within an allowable range required by the above-described system. This will be described with reference to FIG.

Here, the insertion of the DIT described above should ideally be performed, for example, as shown in FIG. FIG. 10A shows a partial TS
Are shown over time. In this case, first, it is assumed that the partial TS having the content of the program 1 is transmitted. As shown, the partial TS has a data length of 188 bytes and a time length of about 50 μs.
(acket) is formed by a continuous data unit.

Then, for example, it is assumed that the program 1 is interrupted at time t1 due to the switching of the channel, and the program 2 is newly switched to. This means that the content in the partial TS has changed, and therefore, a discontinuous point has occurred in the partial TS. When a discontinuous point occurs in this way, the sending device generates a DIT, and inserts the generated DIT following the data position at which the program 1 has been completed. Here, the DIT is data of a TS packet unit of 188 bytes, and in fact, as shown as a first DIT and a second DIT, two TS packets having different data contents are provided.
It is stipulated that et units be inserted continuously. When the first DIT and the second DIT are inserted as described above, for example, the content as a new program 2 is transmitted from time t2.

On the device side that receives and decodes the transmitted partial TS, the discontinuous position of the partial TS can be recognized based on the DIT inserted as described above. Then, appropriate processing corresponding to the recognized discontinuous position is performed at an appropriate timing. Since the process corresponding to the discontinuous position is a process involving a change in a program or the like, it is preferable that the process be performed as quickly as possible. Therefore, as DIT,
Ideally, as schematically shown in FIG. 10A, DIT is composed of program 1 and program 2
It is preferable that the insertion is performed such that no time gap is generated between them. If inserted at such a timing, the receiving side can immediately recognize that the partial TS becomes discontinuous immediately after the end of the program 1 and quickly and appropriately execute data processing as a new program 2. Can be.

However, as described above, it takes a considerable amount of time to generate a DIT by software processing. Therefore, the DIT is actually inserted at the timing illustrated in FIG. Would be. That is, in the flow of the partial TS, the time t1
Even if it is recognized that the program 1 has been completed, it takes time to generate the first DIT by the software. For example, as shown in FIG. One DIT is inserted. In addition, the second DIT to be inserted after the first DIT is also inserted, for example, at time t1-3 at which a corresponding time has elapsed from time t1-2 immediately after the insertion of the first DIT.

For example, in reality, the time intervals shown as the time points t1 to t1-1 and the time points t1-2 to t1-3 in FIG. 10B may be as long as several ms. is there. If the time interval is too vacant in this way, there is a high possibility that the receiving side will not be able to appropriately execute the process corresponding to the discontinuous position of the partial TS.

[0015]

In view of the above-mentioned problems, the present invention is configured as a data processing device as follows. That is, input means for inputting stream data in accordance with a predetermined standard, and discontinuity information formed as hardware, which indicates that the stream data is discontinuous, generate stream data input by the input means. A discontinuous information processing means that can be output by inserting the discontinuous information into the stream data, and a timing at which the discontinuous information is to be inserted into the stream data input by the input means. And timing control means for performing the operation.

In the above arrangement, the discontinuous information processing means for generating the discontinuous information and inserting it into the stream data in a predetermined format is formed by hardware. Then, for example, as a control process by software, the timing of inserting the discontinuous information is instructed. That is, in the present invention, the discontinuous information is generated by the operation of hardware so that the discontinuous information is generated at high speed. Compared to the case where discontinuous information is generated, it is possible to insert discontinuous information into stream data at more ideal timing.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A data processing apparatus according to an embodiment of the present invention will be described below. The data processing apparatus according to the present embodiment will be described as an example in which the data processing apparatus is mounted on a digital satellite broadcast receiving apparatus that can receive and demodulate digital satellite broadcasts and output video / audio signals. The following description will be made in the following order. 1. Digital satellite broadcast receiver 2. DIT 3. IEEE 1394 communication unit

1. Digital Satellite Broadcast Receiver FIG. 1 shows a configuration example of a digital satellite broadcast receiver according to the present embodiment. As is well known, in digital satellite broadcasting, a digital broadcasting signal is output from a communication satellite or a broadcasting satellite. The parabolic antenna 12 receives a broadcast signal from this satellite, and a built-in LNB (Low Noize Block).
Downconverter) converts the signal into a predetermined high-frequency signal and supplies it to the digital satellite broadcast receiver 1.

In the digital satellite broadcast receiver 1, a reception signal received by the parabolic antenna 12 and converted to a predetermined frequency is input by the front end unit 2. In the front end unit 2, the system controller 1
Based on a setting signal in which transmission data and the like are set from No. 1, a carrier (reception frequency) determined by the setting signal is received and subjected to, for example, a Viterbi demodulation process or an error correction process. Stream).

[0020] TS according to this digital satellite broadcasting standard
As is well known, for example, MPEG2 (Moving Picture
According to the Experts Group Layer 2) method, compressed data obtained by compressing video signals and audio signals of a plurality of programs (programs) and various types of additional information are multiplexed. The compressed data obtained by compressing the video signal and the audio signal are multiplexed as an ES (Elementary Stream). The additional information inserted by the broadcasting side is PAT
(Program Association Table), PMT (Program Map Ta
ble) and other tables that store tables such as PSI (Program Specifi
c Information: Program specific information) and SI (Service Info)
rmation: program arrangement information). The multiplexing of the information is performed by forming a TS by using a transport stream packet (TS packet) of 188 bytes.
This is performed by storing S and various additional information. The TS obtained by the front end unit 2 is supplied to a descrambler 3.

In the front end unit 2, the TS sends PSI (Program Specific Information).
And update its tuning information,
Component PID of each channel in TS (Pro
gram ID) and transmits it to, for example, the system controller 11. In the system controller 11, the acquired PI
D will be used for received signal processing.

The descrambler 3 receives descrambling key data prepared in advance from the system controller 11 and, at the same time,
D is set. Then, a descrambling process is executed based on the descrambling key data and the PID. In this case, the TS descrambled by the descrambler 3 is supplied to the terminal T1 of the switch 8 and is branched and supplied to the IEEE 1394 communication unit 4. . Also, for confirmation, as the TS output from the descrambler 3, there is a possibility that ESs of a plurality of programs are multiplexed, and additional information such as PSI is also removed. It is multiplexed without being.

The switch 8 is connected to the system controller 11
The terminal T3 or the terminal T1 with respect to the terminal T3.
Switching is performed such that 2 is alternatively connected. Then, the received broadcast signal is decoded and the video /
When outputting as an audio signal, the terminal T1 is connected to the terminal T3, so that the TS output from the descrambler 3 is supplied to the demultiplexer 9.
On the other hand, when the external TS received by the IEEE 1394 communication unit 4 is decoded and output as a video / audio signal, the terminal T2 is connected to the terminal T3 so that the IEEE 1394 communication unit 4 The received TS is output to the demultiplexer 9. The configuration of the IEEE 1394 communication unit 4 will be described later.

The demultiplexer 9 separates necessary TS packets from the TS supplied from the descrambler 3 in accordance with the filter conditions set by the system controller 11. Thereby, for example, the demultiplexer 9
In, T for one target program
As S packets, TS packets of video data compressed by the MPEG2 system and TS packets of audio data compressed by the MPEG2 system are obtained. Then, the compressed video data and the compressed audio data thus obtained are output to the MPEG decoder 10.

The individual packets of the compressed video / audio data separated by the demultiplexer 9 are P
Each is input to the MPEG decoder 10 in a format called ES (Packetized Elementary Stream). The setting of the filter conditions described above is performed, for example, in the demultiplexer 9 in the PA included in the TS.
T, PMT, etc. are extracted and the system controller 11
To be forwarded to. Then, the system controller 11 sets a filter condition for the demultiplexer 9 based on the information content described in the transferred PAT, PMT, and the like.

The MPEG decoder 10 decodes (decompresses) compressed video data in accordance with the MPEG2 format and decodes compressed audio data in synchronization with the video data output in accordance with the MPEG2 format. And an audio decoder. And
The input compressed video data is decoded by a video decoder, and the input compressed audio data is decoded by an audio decoder. In this case, for example, for decoded video data, for example, NTS
A required signal processing is performed so that an image is properly displayed in accordance with a predetermined television system such as the C system, and the resultant is output as an analog video signal. Also,
For decoded audio data, for example, D
/ A conversion and output as an analog audio signal.

The IEEE 1394 communication unit 4 is provided to enable communication between the digital satellite broadcast receiver 1 and external devices via the IEEE 1394 bus 13. And as a basic configuration for this, as is well known, in terms of hardware and firmware, a physical layer, a link layer,
A configuration is provided in which a transaction layer and a serial bus management are provided, and an application is provided above the transaction layer. Further, according to the present embodiment, a filter unit 5 and a DIT insertion unit 6 are provided.

In this case, the IEEE 1394 communication unit 4
A TS received by the digital satellite broadcast receiver 1 and descrambled by the descrambler 3 is input, and can be transmitted and output to an external device connected via the IEEE 1394 bus 13. . For example, if a digital storage device such as a digital VTR or HDD is connected as an external device, data received and acquired by the digital satellite broadcast receiver 1 can be recorded and stored in the digital storage device in the form of TS. .

The operation of transmitting the TS received and obtained as described above to an external device is roughly as follows. As described above, the TS input from the descrambler 3 to the IEEE 1394 communication unit 4 is in a state in which data of a plurality of programs is multiplexed, and various additional information is multiplexed. So IE
In the EE1394 communication unit 4, the TS input from the descrambler 3 is first supplied to the filter unit 5. In the filter unit 5, the input T
From S, a TS packet of only a required program (content) is separated. Also in this case, as described above as the operation of the demultiplexer 9, the filter condition for extracting a necessary TS packet based on the contents of the additional information such as PAT and PMT included in the TS, for example, Is set.

Here, depending on the TS packet separated by the filter unit 5, a transmission TS is reconstructed. This TS corresponds to a program required from the original TS. Since only the information is partially extracted, it is called a “partial transport stream (partial TS)”.

Then, in the IEEE 1394 communication unit 4,
If necessary, the DIT is inserted into the partial TS obtained by the functioning of the filter unit 5 using the DIT insertion processing unit 6.

The details of DIT will be described later.
T is an abbreviation of “Discontinuity Information Table”, and is additional information in TS packet units, which is unique to the partial TS. Then, the insertion of the DIT indicates that discontinuity has occurred at the insertion position in the partial TS. For example, in the case of the present embodiment, the digital satellite broadcast receiver 1
In this case, there is a possibility that the reception channel is switched, or that the reception condition at the parabolic antenna 12 is deteriorated and a normal reception signal is interrupted. If such a situation occurs, the received and obtained TS loses continuity.
The discontinuity is also given to the partial TS obtained by the 394 communication unit 4. It is specified as a standard that DIT should be inserted when a discontinuous position occurs in a partial TS in this way. The determination of the discontinuity can be made, for example, by the system controller 11 monitoring the signal processing status in the front end unit 2 or the descrambler 3.

The partial TS into which the DIT is inserted as needed is transmitted to the transmission / reception unit 7, for example, by the IEEE.
Packetization is performed according to the format of the E1394 data interface, and transmitted to a target device (node) via the IEEE1394 bus 13.

In the IEEE 1394 communication unit 4 of the present embodiment, for example, the transmission / reception unit 7 functions so that the data in the form of TS transmitted from the external device is transmitted to the IEEE 1394 communication unit.
It is possible to receive and acquire the data via the 94 bus 13. Then, by outputting the received and obtained TS to the demultiplexer 9 via the switch 8, the MPEG decoder 10 eventually outputs the TS as an analog video / audio signal.

That is, in the digital satellite broadcast receiver 1 of the present embodiment, the provision of the IEEE 1394 communication unit 4 makes it possible to transmit the received and acquired TS to an external device. Further, for example, it is possible to receive data as a TS reproduced by an external digital storage device and output a video / audio signal obtained by the TS.

2. DIT By the way, generation of DIT and DIT to partial TS
As described above, the insertion of the "" has conventionally been performed by software processing. Since the processing load for generating the DIT is heavy, it has been difficult to generate and transmit the DIT at a high speed, for example, to the extent required by the receiving side. Therefore, in the present embodiment, the DIT insertion processing unit 6 in the IEEE 1394 communication unit 4 is formed by hardware. If the DIT is generated by hardware, the speed will be higher than that generated by software processing. Further, by adopting the circuit configuration and operation described later, D
It is possible to efficiently generate IT.

Here, prior to describing a circuit configuration for generating and inserting a DIT according to the present embodiment, the DI
A description of T will be given. As described earlier, DIT (Discontinuity Information T
“able” is additional information in units of TS packets specific to the partial TS. In order to indicate that a discontinuity has occurred in the partial TS, it is specified that the partial TS be inserted at the position where the discontinuity has occurred. For reference, DI
About T, DVB ETS 300 468 Specification for Se
rvice information (SI) in DVB systems, ARIB-STD B1 /
It is defined in the standards of B21 and ARIB TR-B15, in which the conditions for inserting the DIT are specifically described, but the description is omitted here.

The restriction for inserting the DIT is, as shown in FIG. 10A, TS packets having two different data structures of the first DIT and the second DIT are continuously inserted. Between the first DIT and the second DIT TS packet.
It is stipulated that other TS packets having a valid structure must not be inserted. Note that, in this specification, the first DIT and the second DIT are simply referred to as “DIT” unless particularly distinguished. In addition, after the DIT is inserted, the TS packet forming the partial TS is inserted before the DIT is inserted, and the partial TS that should be after the DIT is inserted before the DIT is inserted. The insertion of the TS packet constituting the above is prohibited.

FIG. 4 shows the data structure of the first DIT. As shown in this figure, the first DIT is 188
It has a basic structure as a byte TS packet.
In this regard, the same applies to the structure of a second DIT described later. In the first DIT shown in FIG. 4, according to the format of the TS packet, a 4-byte area from the first byte to the fourth byte has a TS packet header (Transpo).
rt Packet Header). In this case, the remaining 184-byte area from the fifth byte to the 188-byte is treated as an adaptation field for storing specific additional information. The information content in the TS packet header is also shown in the table of FIG. 6, and the information content in the adaptation field is also shown in the table of FIG.

As shown in FIGS. 4 and 6, in the TS packet header, sync_byte (8 bits) transport_error_indicator (1 bit) payload_unit_start_indication (1 bit) transport_priority (1 bit) PID (13 bits) transport_scrambling_control ( 2bit) Each area of adaptation_field_control (2bit) continuity_counter (4bit) is arranged.

When the TS packet header is DIT, the following values are to be stored in each of the above areas. First, 0x47 is stored in sync_byte (8 bits) as a unique synchronization pattern. transp
The ort_error_indicator (1 bit) indicates presence / absence of an error in the TS, but normally stores '0' to indicate that there is no error. payload_unit_start_indication (1bit) is
This indicates whether or not the current packet is the first packet of the table and the PES. Since the DIT is not the table and the PES, it is fixed to “0”. The transport_priority (1 bit) may be any one of '0' and '1' as DIT.
Further, the PID (13 bits) is defined by the standard document as 0x001E for DIT. transport_scra
Regarding mbling_control (2 bits), “00” is stored when scrambling is not performed, and a value other than “00” is stored as needed when scrambling is performed. adaptation_f
ield_control (2bit) is '10' for the first DIT
Is stored, adaptation_field only, no paylo
It is shown to be ad. In other words, only the adaptation field is arranged following the TS packet header, and the payload is a TS packet without any payload, which indicates the first DIT structure in FIG. However, in the case of the second DIT described later, “01” is stored, so that no adaptation_field,
It is made to indicate that it is payload only. 2nd DI
As described later, T has no adaptation field and has a DIT section payload. continuity_counter (4 bits) is a counter indicating the continuity of TS packets having the same value stored in the PID, and is 0x0 unless the first value is specified, and thereafter, one by one as the packet is inserted The incremented value is stored. Then, when a value of 0xF is taken, it is wrapped around to 0x0. This means that the system should automatically count up each time a packet is inserted by the system.

In addition, in the adaptation field, as shown in FIGS. 4 and 7, adaptation_field_length (8 bits) discontinuity_indicator (1 bit) random_access_indicator (1 bit) elementary_stream_priority_indicator (1 bit) PCR_flag (1 bit) OPCR_flag (1 bit) ) splicing_point_flag (1bit) transport_private_data_flag (1bit) adaptation_field_extension_flag (1bit) is arranged and the remaining area is stuffing_byte as
ALL'1 'is stored.

The adaptation_field_length (8 bits) is
The data length as an adaptation field is indicated. Also, there are eight flags in the adaptation field. For these flags, when the TS packet is a DIT, first, the discontinuity_in
'1' is stored in the dicator, and the remaining seven flags (rand
om_access_indicator, elementary_stream_priority_in
dicator, PCR_flag, OPCR_flag, splicing_point_fla
g, transport_private_data_flag, adaptation_field_e
xtension_flag) specifies to store '0'.

FIG. 5 shows a structure diagram of the TS packet as the second DIT. As shown in FIG.
In the DIT, the 4-byte area from the first byte to the fourth byte is also a TS packet header.
ader). And in this case, the fifth
A 5-byte area from byte to ninth byte is defined as a DIT section, and the remaining area from byte 9 to 188 is filled with stuffing_byte.

The structure of the TS packet header in the second DIT is the same as that of the first DIT described with reference to FIGS.
It is similar to the case of However, as described above, the 2D
In the TS packet header of IT, adaptation_f
'01' is stored as a fixed initial value for ield_control (2bit).

The structure of the DIT section is also shown by the table in FIG. As shown in FIG. 5 and FIG. 8, the DIT section is, in order from the head position, pointer_field (8 bits) table_id (8 bits) section_syntax_indicator (1 bit) reserved (1 bit) reserved (2 bits) section_length (12 bits) transition_flag (1 bit) reserved (7bit) is allocated and stuffing_byte is set in the remaining area, for example, AL
L'1 'is stored.

Then, in the above DIT section,
0x00 is stored in the pointer_field (8 bits), which indicates that the first data of the table continues immediately after the pointer_field. In table_id (8 bits), 0x7E indicating that the table is a DIT section is stored. By storing '0' in section_syntax_indicator (1 bit), the table as the DIT section is indicated to be a so-called Short section. Also, section_length is 0x001
Is stored, and following this field, table information is 1
It is made to indicate that it is a byte. transition_fla
g is '0', according to a predetermined condition for inserting DIT.
Any value of '1' is set. 6 to 8.
The uimsbf and bslbf shown in are each ident
It shows the bit string notation method as ifier, uimsbf
Is an unsigned integer with the most significant bit first.
integer, most significant bit first). In addition, bslbf indicates that the left bit is the first bit string (bit string, left bit first).

3. IEEE 1394 Communication Unit Next, the internal configuration of the IEEE 1394 communication unit 4 will be described in terms of DIT generation / insertion processing according to the present embodiment. FIG. 2 illustrates a configuration for transmitting a partial TS to an external device as an internal configuration of the IEEE 1394 communication unit 4 illustrated in FIG. In this figure, the same parts as those of FIG. 1 are denoted by the same reference numerals, and the description of the same contents as those of FIG. 1 will be omitted.

The TS output from the descrambler 3 (FIG. 1) is input to the filter unit 5, and as described above, the TS of the required program (content) is
It is output as a partial TS formed only from packets. And this partial TS is a TS FIF
Input to O22.

The TS FIFO 22 is provided as a buffer for absorbing jitter (delay time) when transferring data in the MPEG2 format by isochronous transfer of the IEEE 1394 data interface. The partial TS input to the TS FIFO 22 is transmitted to the switch unit 2 at a predetermined transfer rate.
3 is serially transferred. In this case, TS
The FIFO 22 is a flash instruction signal (Flash) output from the DIT insertion processing unit 6 having an internal configuration described later.
, Data stored therein can be flushed.

In practice, the IEEE 1394 communication unit 4
In TS, additional information in units of TS packets to be inserted into a partial TS is, for example, PSI, SI, etc.
However, the additional information is generated by the system controller 11 executing software processing.
These types of additional information generated by the system controller 11 are stored in the packet FIFO at a predetermined timing corresponding to the timing of insertion into the partial TS.
21. The packet FIFO 21 transfers the additional information transferred from the system controller 11 to the switch unit 33 at a predetermined transfer rate.

The DIT insertion processing unit 6 also shown in FIG. 1 is constituted by hardware. This DI
In the T insertion processing unit 6, in accordance with an instruction from the system controller 11, the DI having the structure described with reference to FIGS.
T is generated and transferred to the switch unit 6 for insertion into the partial TS. Also, in this case, the DIT insertion processing unit 6 can output a flash instruction signal (Flash) for flashing data held in the TS FIFO 22 according to a timing instruction from the system controller 11. The internal configuration of the DIT insertion processing unit 6 will be described later.

In the switch section 23, the partial TS input from the TS FIFO 22 is normally used.
And outputs it to the transmission processing unit 24 after passing through the data string. Then, when additional information (excluding DIT) is input from the packet FIFO 21, the additional information is passed at an appropriate timing and output to the transmission processing unit 24. When the DIT is output from the DIT processing unit 6, the DIT is output from the transmission processing unit 24 through the DIT output from the DIT processing unit 6. By switching the data to be passed by the switch unit 23 in this manner, the transmission processing unit 24 is provided with the partial T in which the necessary additional information is inserted at the appropriate position.
S is transferred.

In the transmission processing unit 24, for example, the partial TS in which the additional information is inserted
According to the format of the IEEE 1394 data interface, for example, processing such as packetization suitable for isochronous transfer is performed, and the data is transmitted and output to a target device (node) via the IEEE 1394 bus 13.

By the way, DIT is performed on the partial TS.
Is inserted, for example, in the DIT insertion processing unit 6, in response to a timing instruction from the system controller 11,
The flash instruction signal is output to the TS FIFO 22. At this time, the system controller 11 monitors a signal processing state in the front end unit 2 or the descrambler 3 and detects a discontinuous position of data in the TS. When the discontinuous position is detected, an instruction signal is output at a required timing.

According to the flash instruction signal input from the DIT insertion processing unit 6 as described above, the TS FIFO
O22 flushes the data held therein. In practice, the DIT is inserted in accordance with the timing at which the data in the TS FIFO 22 is flushed, and thereafter, the partial TS of the new content is output to the switch unit 23 via the TS FIFO 22. Will be. Thus, the FIFO 2 for TS
By flushing the data of No. 2, the DIT is appropriately inserted at the discontinuous point of the partial TS.

Next, an example of the internal configuration of the DIT insertion processing section 6 and its operation will be described with reference to FIG. The DIT insertion processing unit 6 according to the present embodiment includes a first register 31 and a second register 32 as shown in FIG.
The first register 31 holds the data of the data structure portion that is validated in the TS packet as the first DIT. As can be seen from FIG. 4 described above, the valid data structure part of the first DIT includes a 4-byte TS header,
The area is a total of 6 bytes, that is, the upper 2 bytes in the adaptation field that follows. That is, the first
The register 31 holds the data structure of the upper 6 bytes in the TS packet having the structure shown in FIG. Then, for example, at an initial time such as at the time of activation, an initial value to be described later is set in each area in the 6-byte data structure.

The second register 32 holds the data of the data structure portion that is valid in the TS packet as the second DIT. In the case of the second DIT, the effective data structure portion is a 9-byte area of a 4-byte TS header followed by a 5-byte DIT section as shown in FIG. Therefore, the second register 3
2 is designed to hold this 9-byte data structure. In this case as well, at an initial time such as at the time of activation, an initial value described later is set for each area in the 6-byte data structure. In this manner, the DIT insertion processing unit 6 of the present embodiment stores and holds the basic structure of the DIT in the register. Then, in this case, the first DI
Only a total of 15 bytes are required for T and the second DIT, so that the registers to be prepared as hardware can be small.

The generation / output control unit 33 generates a DIT of data contents required as needed. For this reason, in the valid data structure portion of the first DIT and the second DIT stored in the first register 31 and the second register 32, an appropriate value is set for an area that needs to be changed. Then, the valid data structure portions of the first DIT and the second DIT in which the required values are set as described above are read from the first register 31 and the second register 32, and stuffing_byte of a required number of bytes is added.
As a result, the first DIT and the second DIT having a size of a TS packet unit are obtained. Then, the TS packets as the first DIT and the second DIT generated in this way are output to the switch unit 23 at appropriate timing. And in order to realize the above operation,
Functionally, the generation / output control unit 33 includes a flag setting unit 33a and an increment unit 3 as shown in the figure.
3b, a byte embedding unit 33c, and an insertion output unit 33d
And is configured. Note that the generation / output control unit 33 is also formed by hardware.

The output processing for generating the DIT and inserting it into the partial TS by the above-described circuit configuration is performed as follows. First, the first register 3
In the first and second registers 32, the first DIT, the second D
The initial value set for the valid data structure portion of the IT will be described. In this description, FIGS. 4 to 8 are referred to again.

An initial value is set in the first register 31 for the valid data structure portion of the first DIT as follows. As described above, the valid data structure portion of the first DIT stores the TS packet header (4 bytes) and the upper 2 bytes in the adaptation field following the TS packet header. First, TS packet
In the header, 0x47 which is a synchronization pattern is set in sync_byte (8 bits). This sync_byte (8bit) is
Initial value set because it is specified as a fixed value
0x47 is fixedly used. In the following, an initial value that is not fixed and is not changed is referred to as a “fixed initial value”. Transport_error_indicator (1 bit) stores '0' as a fixed initial value, and indicates that there is no error. Also,
Since payload_unit_start_indication (1 bit) is stored in the packet as DIT and is not a table or PES, '0' is set as a fixed initial value. Transport_priority (1bit) is the DIT
Since it is supposed to be either '0' or '1',
Any arbitrary value is set as a fixed initial value. The PID (13 bits) is set to 0x001E for the DIT according to the standard, so this may be set as a fixed initial value. However, the system side may rewrite the PID (13bit) as necessary. It does not matter. Regarding transport_scrambling_control (2 bits), here, a fixed initial value '00' is set so as not to perform scramble processing.
However, if the specification for performing the scramble processing is set, a value other than '00' may be set as necessary. As described above, the adaptation_field_control (2 bits) is fixed at “10” for the first DIT, so this value is set as a fixed initial value. It should be noted that, in the case of the second DIT, no ada
'01' indicating ptation_field, payload only is stored as a fixed initial value. continuity_c
ounter (4bit) is set to 0x0 as an initial value. And the value of this continuity_counter is PID
Each time the same packet indicated by is inserted, the packet is incremented and set.

Further, of the upper two bytes in the adaptation field, the upper one byte adaptation_f
In ield_length (8 bits), 0xB7 indicating 183 bytes is set as a fixed initial value. Then, for each of the eight flags forming the 1-byte area following this, fixed initial values are set as follows in accordance with the regulations. In other words, the discontinuity_indicator is '1'
And set the remaining seven flags (random_access_indi
cator, elementary_stream_priority_indicator, PCR_f
lag, OPCR_flag, splicing_point_flag, transport_pri
vate_data_flag, adaptation_field_extension_flag)
Is set to '0'.

The second DI in the second register 32
The initial values to be set for the valid data structure portion of T are as follows. First, the upper four bytes of the TS packet header in the valid data structure portion of the second DIT are the same as in the case of the valid data structure portion as the first DIT described above. However, as described above, “01” is set as a fixed initial value for adaptation_field_control (2 bits).

Then, for each area forming 5 bytes as a DIT section, an initial value is set as follows. In other words, pointer_field (8bit) contains 0x0
0 will be set as the fixed initial value. Also, tab
In le_id (8 bits), 0x7E is set as a fixed initial value. As described above in the description of the data structure, the system can change the value as needed. Also, section_syntax_indicator (1bit)
Is set as a fixed initial value, and '0' is set as the section_length. Also, transition_f
lag is '0', according to a predetermined condition for inserting DIT.
Since the value is to be changed to any one of '1', any of '0' and '1' is temporarily set as the initial value. In the DIT section, a 3-bit area following the section_syntax_indicator and a 7-bit area following the transition_flag are reserved.
But here, each of these reserved
ALL'1 'is set for each of the regions.

Then, as described above, the first register 3
1st DIT and 2nd DI in the first and second registers 32
Under the state where the initial value is set for the valid data structure portion of T, the system controller 11 detects the discontinuous position of the TS currently being processed, and sets the DIT insertion condition as the detection status at this time. Assume that it is determined that the condition is satisfied. Then, the system controller 11
Outputs a transmission instruction command to the generation / output control unit 33 at a required timing according to the detection timing of the discontinuous position. Further, the system controller 11 sets the second D
The transition_flag in the IT is determined as to which of “0” and “1” should be set, and a flag set command indicating a value to be set as the transition_flag is generated / output controller 33 based on the determination result. Output to

In response to this, the generation / output control unit 33 to which the transmission instruction command is input increments the count value of the counter assumed to be included in the increment unit 33a. Then, the count value obtained by the increment is set to the first DIT in the first register 31.
Is set as the value of the continuity_counter possessed by. Then, similarly, the second DI in the second register 32
The value of the continuity_counter of T is set.

At this time, in the flag setting section 33a, transi specified by the flag set command is used.
generation_flag value, and the generated value is
Transition_f of the second DIT in the register 32
Set as the value of lag.

Then, assuming that the necessary values have been set as described above, the generation / output control unit 33
Then, for example, first, a 6-byte first DIT valid data structure portion is read from the first register 31. Then, by the byte embedding unit 33c, stuffing_byt
As e, 176 bytes of ALL'1 'data are generated and added to the end of the read valid data structure portion of the first DIT.

By performing the above operation, the first DIT based on the size of the TS packet is generated. Then, the insertion output processing unit 33d sends the TS packet as the first DIT generated in this way to the switch unit 23.

Subsequently, the generation / output control unit 33
Reads a 9-byte valid data structure portion of the second DIT from the second register 32. Then, the stuffing_byte is set to 17 by the byte embedding unit 33c.
By generating 9-byte ALL'1 'data and adding it after the valid data structure portion of the read first DIT, a second DIT based on the size of the TS packet is generated. Then, the insertion output processing unit 33d sends out the TS packet as the second DIT to the switch unit 23.

Further, the system controller 11 is provided with a DI
Along with the T transmission instruction, a flush instruction command for flushing the TS FIFO 22 is output to the generation / output control unit 33 at a required timing. In response to the input of the flash instruction command, the insertion / output unit 33d causes the TS FIFO
A flash instruction signal (Flash) is output to the CPU 22.
As a result, as described above, DIT becomes partial T
S is inserted properly at a discontinuous position in S.

Conventionally, for example, in the configuration shown in FIG. 2, the configuration in which the DIT insertion unit 6 is deleted has been adopted. In other words, DIT, like other additional information,
It is generated by software processing by the system controller 11 and transferred to the packet FIFO 21. The processing of generating such additional information having a size of 188 bytes is heavy for the CPU constituting the current system controller 11, and therefore, it takes a considerable time until the generation is completed. In particular, since DIT is to be inserted at a discontinuous position of the partial TS, this DIT
If the insertion timing of the partial TS is delayed, the timing of recognizing the discontinuous position by the system for inputting the partial TS is delayed, which may cause a problem in decoding the partial TS, for example.

On the other hand, in the present embodiment,
As shown in FIG. 2, a DIT insertion processing unit 6 is newly provided, and the DIT insertion processing unit 6 generates the first DIT and the second DIT and outputs the first DIT and the second DIT for insertion into the partial TS. Is done. And such DI
The operation for generating and outputting the DIT by the T insertion processing unit 6 is performed by the hardware configured as shown in FIG. 3, and the software control of the system controller 11 is only the transmission timing control. Therefore, the first DIT and the second DIT can be quickly generated and output. Therefore, according to the present embodiment, as shown in, for example, FIG.
It becomes possible to output the partial TS into which the IT has been inserted. In addition, as understood from the above description, the DIT has an area whose value is changed every time insertion is performed, for example, continuity_counter (4 bits), transition_fla
It is limited to g (1 bit), etc., and there are far more areas where fixed values are stored. Also, the size of the area where these values are changed is very small. For this reason, the circuit configuration for changing and setting the value is very simple, and the processing as hardware is also very light.

By the way, depending on the DIT insertion condition, T
In some cases, it may not be necessary or necessary to flush data before the discontinuous position held in the S FIFO 22. A specific example of such a case will be described with reference to FIG. FIG. 9A shows a state where the partial TS is output as time elapses. For example, as shown in this figure, first, it is assumed that a partial TS formed with content relating to only the program 1 is received. Then, it is assumed that, at a certain point in time, the data of the content related to the program 2 is changed to the multiplexed TS with respect to the content of the program 1.

Even in such a case, according to the standard, DIT
Since the insertion condition is satisfied, the DIT should be inserted with the position where the program 2 is added as a discontinuous position. However, in this case, the PCR (Program Clock
Reference), as shown in FIG. 9B, is continuous regardless of the discontinuous position of the partial TS. Note that PCR is time information serving as a reference for synchronous playback with video / audio. In the case of the digital satellite broadcast receiver 1 of the present embodiment, for example, the PCR is extracted and separated from the TS by the demultiplexer 9. It can be configured to play.

In the above case, however, it is necessary to insert the DIT, but on the other hand, since the PCR is continuous, to maintain this continuity, the TS
There is no need to flush the data before the discontinuous position held in O22. For example, in the conventional configuration as described above, since the processing itself for inserting the DIT has a heavy load, when inserting the DIT, the TS FIFO 22 is flushed without exception. . In this case, since the continuity of the PCR is lost, there is a possibility that a failure may occur in the decoding on the side where the partial TS is input and decoded.

Therefore, in the present embodiment, under the configuration of the DIT insertion processing unit 6 of the present embodiment shown in FIG.
By giving the operation of the generation / output control unit 33 as described below, the TS FIFO can be changed according to the DIT insertion condition.
Switching between valid / invalid for flashing of data held in O22 is performed.

Transition_flag stored in the second DIT
Is, as described above, '0',
Although it is defined that any value of '1' is set, it actually depends on the presence or absence of continuity of PCR. That is, '0' is set in the DIT insertion condition where discontinuity is caused by changing all contents including the PCR in the partial TS. On the other hand, in the DIT insertion condition in which the discontinuity occurs in the partial TS after the continuity of the PCR is maintained, '1' is set.

Therefore, the insertion / output processing unit 3 of the present embodiment
In 3d, a function circuit unit for detecting which of "0" and "1" is instructed to be set as a flag set command input from the system controller 11 is formed. Then, when it is detected that the flag set command indicates the setting of '0', as described above,
A flush instruction signal is output to the TS FIFO 22 to cause the TS FIFO 22 to perform flushing. In contrast, the flag set command is '1'
When it is detected that the instruction is to set the flash instruction signal, the flash instruction signal to the TS FIFO 22 is not output. Thereby, the FI for TS
In the FO 22, the transfer operation is continued without flushing the data. By adopting such a configuration, in the present embodiment, it is possible to prevent the TS FIFO 22 from being flushed as necessary even when the DIT is inserted.

In order to actually realize the above operation as a circuit, a detection circuit for detecting the instruction content of the lag set command and a flash instruction to the TS FIFO 22 using the detection output of the detection circuit are simply provided. A circuit for controlling signal output / stop may be provided as hardware. Therefore, such an operation can be realized by a simple circuit configuration, and the high-speed operation is maintained.

The present invention is not limited to the configuration described in the above embodiment. For example, in the above-described embodiment, the case where the data processing device of the present invention is applied to a digital satellite broadcast receiver is taken as an example. The present invention is applicable to a case where data in a partial TS format is transmitted by IEEE1394 in a reproducing apparatus or the like. Also, data to be processed by the data processing device may be data according to a standard other than stream data according to the digital satellite broadcasting standard. Further, the present invention can be applied to data communication formats other than IEEE1394.

[0082]

As described above, the present invention provides a DIT
When the (discontinuous information) is generated and inserted into the partial TS (stream data), the DIT is generated by hardware, and the software processing at this time includes an instruction of the DIT insertion timing. To be done. In this way, the functions of the hardware and the software are selectively used for the generation / insertion of the DIT, so that the generation / insertion of the DIT is performed as compared with the conventional case where all the generation / insertion of the DIT is performed by hardware. The insertion of the DIT into the partial TS can be performed much faster. Therefore, for example, even when a partial TS is input and decoded, it is possible to execute appropriate processing.

As a hardware configuration for generating the DIT, for example, a register holding at least a valid data structure portion of the DIT is provided, and an initial value is set for data held in this register. When the DIT is inserted, a required value is set in a required information area that needs to be changed for the data held in the register. By providing such a configuration as hardware, it is possible to generate a DIT more efficiently and at a higher speed.

Further, according to the present invention, an instruction for instructing the TS FIFO (buffer) to flush data based on a value to be set in a predetermined area such as a transition_flag indicating a DIT insertion condition. Configured to set output / stop for the signal;
This is also configured in hardware. Due to this, while having a simple circuit configuration, D
Data flash in the TS FIFO can be appropriately controlled according to the IT insertion condition.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a digital satellite broadcast receiver including a data processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of an internal configuration of an IEEE 1394 communication unit 4 according to the present embodiment.

FIG. 3 is a block diagram illustrating a configuration example of a DIT insertion processing unit according to the present embodiment.

FIG. 4 is a data structure diagram showing a data structure of a first DIT.

FIG. 5 is a data structure diagram showing a data structure of a second DIT.

FIG. 6 is a table showing the structure of a TS packet header in DIT.

FIG. 7 is a table showing the structure of an adaptation field in DIT.

FIG. 8 is a table diagram showing a structure of a DIT section (DIT Table).

FIG. 9 is an explanatory diagram schematically showing a case where PCR is continuous as an example of a state of occurrence of discontinuity in a partial TS.

FIG. 10 is an explanatory diagram schematically showing a process of inserting a DIT into a partial TS.

[Explanation of symbols]

1 digital satellite broadcast receiver, 2 front end section,
3 descrambler, 4 IEEE1394 communication section, 5
Filter section, 6 DIT insertion section, 7 transmission / reception section, 8
Switch section, 9 demultiplexer, 10 MPEG decoder, 11 system controller, 12 parabolic antenna, 13 IEEE1394 bus, 21 packet FIFO, 22 TS FIFO, 23 switch section, 24 transmission processing section, 31 first register, 32 second
Register, 33 generation / output control unit, 33a
Flag setting part, 33b increment part, 33c byte embedding part, 33d insertion output part

Continued on the front page F term (reference) 5C059 KK12 MA00 RA04 RB02 RC01 SS02 UA02 UA38 5C064 DA10 DA12 DA14 5K028 BB05 CC02 CC05 DD06 EE05 KK01 KK12 LL12 MM04 RR02 5K032 AA02 BA16 CC12 DA01 DA08 DB20 DB24

Claims (3)

[Claims] An input means for inputting stream data conforming to a predetermined standard, and discontinuity information formed as hardware and indicating that the stream data is discontinuous are generated and input by the input means. Discontinuous information processing means that can be output by being inserted into stream data that has been inserted, and a timing at which the discontinuous information is to be inserted into the stream data input by the input means, A data processing device, comprising: timing control means for instructing the processing means. 2. The discontinuous information structure, wherein the discontinuous information processing means is capable of holding at least an effective information structure part of the discontinuous information and is capable of setting an initial value for the held information content. Holding means; and information value setting means for setting a required value for a required information area which needs to be changed, among information areas in the discontinuous information structure held by the discontinuous information structure holding means. The data processing device according to claim 1, comprising: 3. A flash instruction capable of outputting an instruction signal for instructing a buffer to output and output data by performing buffering on stream data input by the input means. Means for outputting the instruction signal based on an information value to be stored in a predetermined information area in the discontinuous information to be generated.
The data processing apparatus according to claim 1, further comprising: setting means for setting a stop.