KR100346110B1 - Apparatus for generating mask signal of quasi orthogonal code in cdma communication system - Google Patents

Abstract

The present invention relates to an apparatus for generating a mask sequence masked to an orthogonal sequence in order to generate a quasi-orthogonal sequence in a mobile communication system using an orthogonal code. According to an embodiment of the present invention, an apparatus for generating a mask having a quasi-orthogonal sequence inputs a counter for generating eight first counter signals X1-eighth counter signals X8 representing a vent function, and the first counter signals X1-eighth counter signals X8. X1 * X2 + X1 * X3 + X1 * X4 + X1 * X5 + X1 * X7 + X1 * X8 + X2 * X6 + X2 * X7 + X3 * X4 + X3 * X5 + X3 * X6 + X4 * X5 + X4 * X6 + X4 * X7 + X4 * X8 + X5 * X7 + X7 * X8 + X1 + X2 + X5 + X7 and a logic operator for generating a first mask signal and the first counter signal X1-8th counter signal Input X8 to calculate X1 * X2 + X1 * X4 + X1 * X6 + X2 * X8 + X3 * X4 + X3 * X5 + X4 * X6 + X4 * X7 + X5 * X8 + X7 + X8 to calculate the second mask signal. Inputs the first counter signal X1 through the eighth counter signal X8 and X1 * X2 + X1 * X3 + X1 * X5 + X1 * X6 + X1 * X7 + X2 * X3 + X2 * X4 + X2 * X7 + X3 * X6 + X3 * X8 + X4 * X5 + X5 * X7 + X5 * X8 + X6 * X8 + X7 * X8 + X5 + X6 + X7 + X8 to generate a third mask signal It is characterized in that the configuration.

Description

Mask generation device of semi-orthogonal code of mobile communication system {APPARATUS FOR GENERATING MASK SIGNAL OF QUASI ORTHOGONAL CODE IN CDMA COMMUNICATION SYSTEM}

The present invention relates to an encoding apparatus of a mobile communication system, and more particularly, to an apparatus for generating a mask sequence masked to an orthogonal code to generate a quasi-orthogonal code. A code division multiple access (CDMA) mobile communication system (hereinafter, referred to as a CDMA system) is one of methods for increasing capacity, and performs channel seperation using orthogonal codes. An example of classifying channels using orthogonal codes as described above may be a forward link of IS-95 / IS-95A, and a time alignment may be applied to a reverse link. Can be.

Channel division by an orthogonal code in the forward link of the IS-95 / IS-95A is performed as shown in FIG. 1. In FIG. 1, orthogonal codes are denoted by w, and each channel is divided by a pre-assigned orthogonal code. In FIG. 1, 'W' may be a Walsh code. The IS-95 / IS-95A forward link uses a convolution code of R = 1/2, performs bi-phase shift keying modulation, and has a bandwidth of 1.2288 MHz. /(9.6k*2)=64. Accordingly, as shown in FIG. 1, the forward link of the IS-95 / IS-95A can perform 64 channel division using an orthogonal code.

When an arbitrary modulation method is determined as described above and a minimum data rate is determined, the number of available orthogonal codes is determined. However, future code division multiple access systems (CDMA) attempt to increase the channels allocated to users for improved performance. To this end, the next generation CDMA system adopts a method of increasing capacity by providing a traffic channel, a pilot channel, and a control channel.

However, even in the above scheme, when the channel usage increases, the number of orthogonal codes available is limited. In this case, even if the channel capacity is increased, there is a limit to the increase in the channel capacity according to the limitation of the number of orthogonal codes that can be used. Therefore, as a method for solving the above problems, generating and using a pseudo orthogonal code that gives a minimum interference to the orthogonal code and can also give a minimum interference to a variable data rate. Preferably, this code is called a quasi-orthogonal code.

The generation of such quasi-orthogonal codes is described in the P1997-47257 patent filed in September 97 by the applicant. In order to generate such orthogonal codes, mask values (hereinafter referred to as masks of orthogonal codes) masked by orthogonal codes are generally stored in a memory in order to generate quasi-orthogonal sequences, and accessed and used whenever necessary. However, for example, if the mask value is 64 bits, 64 bits of memory should be used. In other words, storing mask values in a memory and accessing them whenever necessary requires a problem of hardware complexity corresponding to the memory.

Accordingly, an object of the present invention is to provide a mask generating apparatus capable of generating a mask value of a quasi-orthogonal code giving minimal interference to the orthogonal code in a mobile communication system using an orthogonal code.

Another object of the present invention is to provide an apparatus capable of generating a mask value of a quasi-orthogonal code using a bent function in a mobile communication system using an orthogonal code.

An apparatus for generating a mask sequence masked to an orthogonal sequence to generate a quasi-orthogonal sequence in a mobile communication system for achieving the above objects generates eight first counter signals X1 -8 counter signals X8 representing the vent function. A counter and the first counter signal X1-eighth counter signal X8 are inputted, and X1 * X2 + X1 * X3 + X1 * X4 + X1 * X5 + X1 * X7 + X1 * X8 + X2 * X6 + X2 * X7 + X3 * X4 + X3 * X5 + X3 * X6 + X4 * X5 + X4 * X6 + X4 * X7 + X4 * X8 + X5 * X7 + X7 * X8 + X1 + X2 + X5 + X7 A logic operator for generating a signal and inputting the first counter signal X1-the eighth counter signal X8 to X1 * X2 + X1 * X4 + X1 * X6 + X2 * X8 + X3 * X4 + X3 * X5 + X4 * X6 + X4 * X7 + X5 * X8 + X7 + X8 and a logic operator for generating a second mask signal and the first counter signals X1-8th counter signals X8 are inputted to perform X1 * X2 + X1 * X3 + X1 * X5 + X1 * X6 + X1 * X7 + X2 * X3 + X2 * X4 + X2 * X7 + X3 * X6 + X3 * X8 + X4 * X5 + X5 * X7 + X5 * X8 + X6 * X8 + X7 * X8 + X5 + X6 + X7 + X8 operation to generate a third mask signal is characterized by consisting of a logical operator.

1 is a view for explaining channel classification characteristics by orthogonal codes.

2 shows an apparatus for generating a mask of quasi-orthogonal sequences;

3 shows six clocks output in the binary count of FIG.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in adding the reference numerals to the components of each drawing, the same components have the same reference numerals as much as possible even if displayed on different drawings. In describing the present invention, when it is determined that a detailed description of a related known function or configuration may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted.

The present invention provides a device that can simply obtain the mask value of the quasi-orthogonal sequence by using the bent function (see "The Theory of Error-Correcting Codes" by Macwilliams / Sloane). The mask value of the quasi-orthogonal sequence (patent application P1997-47257) is a Kasami sequence obtained by exclusively adding two Pien sequences. Here, the Kasami sequence may be expressed in the form of secondary binding of Bent functions. Therefore, the present invention expresses the mask value of the quasi-orthogonal sequence in the form of the second combination of the vent functions, and implements it in hardware.

For example, the Bent function required to obtain a mask for a quasi-orthogonal sequence of length 64 is shown in Table 1 below.

x1 = 0101010101010101010101010101010101010101010101010101010101010101x2 = 0011001100110011001100110011001100110011001100110011001100110011x3 = 0000111100001111000011110000111100001111000011110000111100001111x111 = 111111111

At this time, the mask value of the quasi-orthogonal array of length 64 is calculated using the six bent functions of Table 1, as shown in Table 2 below.

M1 = X1 * X2 + X1 * X3 + X2 * X3 + X2 * X4 + X1 * X5 + X4 * X6 M2 = X1 * X2 + X1 * X3 + X3 * X4 + X2 * X5 + X3 * X5 + X2 * X6 + X4 * X6 + X5 * X6M3 = X1 * X2 + X2 * X4 + X3 * X4 + X1 * X5 + X4 * X5 + X1 * X6 + X5 * X6, where + is the modulo 2 operator

By the calculation as shown in Table 2, the mas value of the quasi-orthogonal sequence of length 64 as shown in Table 3 is generated.

M1 = 0001011100100100010000100111000100010111110110110100001010001110M2 = 0001010000011011001010000010011100100111110101111110010000010100M3 = 0001000100101101010001001000011101000100011110001110111000101101

In the Bent function of Table 1, it can be seen that there is regularity. For an orthogonal sequence of length 64 = 2 ⁶ , the first Bent function repeats 0 and 1 alternately 2 ⁰ = 1 times, and the second The Bent function repeats 0 and 1 alternately 2 ¹ = 2 times, the third Bent function repeats 0 and 1 alternately 2 ² = 4 times, and the fourth Bent function repeats 0 and 1 alternately 2 ³ = 8 times In the 5th Bent function, 0 and 1 are repeated 2 ⁴ = 16 times, and in the 6th Bent function, 0 and 1 are repeated 2 ⁵ = 32 times. Each of the vent functions X 1 -X 6 described above is repeated for length 64.

Considering this regularity, we need 8 Bent functions for a quasi-orthogonal sequence of length 256 = 2 ⁸ . This means that the six Bent functions in Table 1 are repeated four times to satisfy 256 lengths, and the 7th Bent function alternates 0 and 1 with 2 ⁶ = 64 times, and the 8th Bent function with 0 and 1 is 2 ^7. = Repeated alternately 128 times. Each sequence is repeated until a length of 256 is satisfied. With these Bent functions, the mas- ter value of the quasi-orthogonal sequence of length 256 is generated as a result of the following Table 4.

M1 = X1 * X2 + X1 * X3 + X2 * X4 + X1 * X5 + X4 * X5 + X2 * X6 + X3 * X6 + X4 * X6 + X1 * X7 + X4 * X7 + X5 * X7 + X3 * X8 + X4 * X8M2 = X1 * X2 + X1 * X3 + X1 * X4 + X3 * X4 + X3 * X5 + X4 * X5 + X1 * X6 + X3 * X6 + X4 * X6 + X5 * X6 + X1 * X7 + X3 * X7 + X4 * X7 + X6 * X7 + X1 * X8 + X2 * X8 + X4 * X8 + X6 * X8M3 = X1 * X2 + X2 * X3 + X2 * X4 + X3 * X4 + X2 * X5 + X4 * X5 + X1 * X6 + X5 * X6 + X3 * X7 + X4 * X7 + X5 * X7 + X1 * X8 + X3 * X8 + X4 * X8 + X5 * X8 + X7 * X8M4 = X1 * X2 + X2 * X3 + X1 * X4 + X1 * X5 + X2 * X5 + X3 * X5 + X4 * X5 + X2 * X6 + X4 * X7 + X6 * X7 + X2 * X8 + X4 * X8 + X5 * X8 + X6 * X8 + X7 * X8M5 = X1 * X2 + X2 * X4 + X3 * X4 + X2 * X5 + X3 * X5 + X4 * X6 + X3 * X7 + X4 * X7 + X6 * X7 + X5 * X8 + X7 * X8M6 = X1 * X2 + X1 * X3 + X2 * X3 + X2 * X4 + X1 * X5 + X3 * X5 + X1 * X6 + X2 * X6 + X3 * X6 + X5 * X6 + X1 * X7 + X4 * X7 + X6 * X7 + X1 * X8 , + Is modulo 2 operator

In order to generate a quasi-orthogonal sequence having a length of 64, when the terms of each Xi in Table 1 are put into each equation in Table 2, the I-th terms of the masks of M1, M2, and M3 are calculated. The calculation results are shown in Table 2 above. In other words, for each of the 64 terms, the mask M1 is generated when the M1 expression in Table 2 is used. Thus, the masks can be expressed in terms of quadratic combinations of Bent functions.

As described above, the masks are represented by the quadratic combination of bent functions as shown in Table 4 below. an arbitrary vent function with k variables When is given,

Two Boolean functions with k-1 variables satisfying and Is unique. With this, the period is 2 ^m is found using the function expression of any cycle the function expression 2 sequence ^m-1 of the sequence, and the period 2 ^m-1 the sequence which is a function expression period 2 ^m-2 Can be represented as a function representation of a sequence Repeat this method m-1 times to find a function representation of any sequence with a period of 2 ^m .

For example, 00010111 is a quasi-orthogonal code mask of length 8. At this time, the second coupling equation of the bent function is obtained.

In order to express the first 000 bundles of four terms as two-dimensional bents having a length of four using the above method, the bundles 00,01 of two terms are expressed as one-dimensional bents having a length of two, resulting in 0 and x1. At this time, the bundle 0001 of the preceding four terms of length 4 is Becomes

In addition, in order to express the bundle 0111 of the four terms later as a two-dimensional bent of length 4 using the above method, the bundles 01 and 11 of two terms are expressed as a one-dimensional bent of length 2, and thus x1 and 1. At this time, the bundle 0111 of the four term after said length 4 is Becomes

Then, the entire mask function 00010111 is represented using the two-dimensional bent expressions x1x2 and x1 + x2 + x1x2 of length 4 above.

Becomes Therefore, the quadratic coupling equation of the bent function of the mask function 00010111 becomes x1x2 + x1x3 + x2x3.

As described above, a method of expressing a mask function as a quadratic coupling equation is implemented as an algorithm (Equation 1 for finding a function expression of a Boolean function).

1 N: = 2 m; flag: = 0; period: = 1;

2 WHILE period <N DO

3 count: = 0

4 FOR i = 1 TO N

5 IF flag = 1 THEN DO

6 f [i] = f [i] + f [i-period]

7 count: = count + 1

8 IF count = period THEN DO

9 flag = flag + 1

10 period: = period 2

Complex quasi-orthogonal codes are represented by sign and phase components. Here, the sign component of the complex quasi-orthogonal code can be represented by a quadratic coupling equation using the method described above. The following <Table 6> and <Table 8> are complex quasi-orthogonal codes having lengths of 256 and 512. The secondary bonding formulas for the <Table 5> and <Table 7> cases, respectively, are shown.

M1 Sign 0111001000101000110101110111001001001110111010111110101110110001111010110100111010110001111010111101011110001101100011010010100000100111100000101000001011011000000110110100000110111110000110110100000100011011000110111011111001111101110110000010011101111101 M2 Sign 0001000101001011000111100100010001000100111000010100101111101110111011100100101111100001010001001011101111100001101101001110111011011101100001110010110101110111100010000010110101111000110111010010001010000111110100100111011101110111001011011000011111011101 M3 Sign 0001011100100100101111010111000110110010100000010001100011010100100011101011110111011011000101110010101100011000011111101011001011100111110101001011001001111110101111011000111011101000001001001000000110110010001010111110011111011011111010000111000110111101

M1 = X1 * X2 + X1 * X3 + X1 * X4 + X1 * X5 + X1 * X7 + X1 * X8 + X2 * X6 + X2 * X7 + X3 * X4 + X3 * X5 + X3 * X6 + X4 * X5 + X4 * X6 + X4 * X7 + X4 * X8 + X5 * X7 + X7 * X8 + X1 + X2 + X5 + X7M2 = X1 * X2 + X1 * X4 + X1 * X6 + X2 * X8 + X3 * X4 + X3 * X5 + X4 * X6 + X4 * X7 + X5 * X8 + X7 + X8M3 = X1 * X2 + X1 * X3 + X1 * X5 + X1 * X6 + X1 * X7 + X2 * X3 + X2 * X4 + X2 * X7 + X3 * X6 + X3 * X8 + X4 * X5 + X5 * X7 + X5 * X8 + X6 * X8 + X7 * X8 + X5 + X6 + X7 + X8, where + is the modulo 2 operator

M1 Sign 01001101110110111101101110110010001001000100110101001101110110110010010001001101010011011101101110110010001001000010010001001101001001000100110101001101110110111011001000100100001001000100110110110010001001000010010001001101110110111011001010110010001001000100110111011011110110111011001000100100010011010100110111011011001001000100110101001101110110111011001000100100001001000100110100100100010011010100110111011011101100100010010000100100010011011011001000100100001001000100110111011011101100101011001000100100 M2 Sign 00010001010010110111100000100010000111100100010001110111001011010100010011100001001011011000100010110100000100011101110101111000011110000010001011101110101101001000100011010010000111100100010011010010011101110100010011100001110111010111100001001011111011100001111001000100100010001101001011101110101101000111100000100010101101000001000100100010100001111011101100011110001011011000100001110111001011010001111001000100011110000010001000010001010010110010001010000111010010111110111011010010011101111011101100011110 M3 Sign 01110100000100101101111001000111001011100100100010000100000111011110001010000100101101110010111001000111001000010001001010001011110111100100011101110100000100100111101111100010110100011011011101001000110100010001110101111011000100101000101101000111001000010100011111011110111011011000101111100010011110110100100000101110110100010100100010000100111000101000101100010010110111101011100000010010011101001011100000100001010010000010111011100010011110111000010011100010110100010100100000100001010001110111010011101101

M1 = X1 * X2 + X1 * X3 + X1 * X4 + X1 * X5 + X1 * X6 + X1 * X7 + X1 * X8 + X2 * X3 + X2 * X4 + X2 * X5 + X2 * X6 + X2 * X7 + X2 * X8 + X3 * X4 + X3 * X5 + X3 * X6 + X3 * X7 + X3 * X8 + X4 * X5 + X4 * X6 + X4 * X7 + X4 * X8 + X5 * X6 + X5 * X7 + X5 * X8 + X6 * X7 + X6 * X8 + X7 * X8 + X1 + X3 + X4 + X5M2 = X1 * X2 + X1 * X4 + X1 * X5 + X1 * X7 + X1 * X8 + X2 * X5 + X2 * X8 + X3 * X4 + X3 * X5 + X3 * X6 + X3 * X8 + X3 * X9 + X4 * X7 + X5 * X8 + X5 * X9 + X6 * X7 + X6 * X8 + X6 * X9 + X7 * X8 + X7 * X9M3 = X1 * X2 + X1 * X4 + X1 * X5 + X1 * X6 + X1 * X7 + X1 * X8 + X2 * X3 + X2 * X4 + X2 * X7 + X2 * X9 + X3 * X6 + X3 * X7 + X4 * X5 + X4 * X8 + X4 * X9 + X5 * X7 + X6 * X7 + X6 * X8 + X6 * X9 + X8 * X9 + X1 + X2 + X5 + X7 + X8, where + is modulo 2 operator

As described above, the mask of the quasi-orthogonal array is expressed in the form of the secondary coupling of the vent functions. Hereinafter, a hardware implementation capable of generating a mask of quasi-orthogonal sequences represented by the quadratic combination of the vent functions.

2 illustrates a mask generator for generating a mask value of a quasi-orthogonal sequence using a vent function according to an exemplary embodiment of the present invention. In particular, FIG. 2 illustrates an apparatus for generating a mask value of a quasi-orthogonal sequence of length 64.

Referring to FIG. 2, the binary counter 110 outputs six first counter signals X1-6th counter signal X6 corresponding to the vent function. These counter signals are shown in FIG. That is, the first counter signal X1, which is twice the pulse width of the base clock and the second counter signal X2, which is twice the pulse width of the first counter signal X1, is input as the basic clock. A third counter signal X3 that is twice the pulse width of the second counter signal X2, a fourth counter signal X4 that is twice the pulse width of the third counter signal X3, and twice the pulse width of the fourth counter signal X4. The fifth counter signal X5 and the sixth counter signal X6 that are twice the pulse width of the fifth counter signal X5 are output. The logical product 120 performs an AND operation on the first counter signal X1 and the second counter signal X2 among the output counter signals of the binary counter 110 and outputs Y12. The logical multiplication 121 performs a logical AND operation on the first counter signal X1 and the third counter signal X3 among the output counter signals of the binary counter 110 and outputs Y13. The logical product 122 performs an AND operation on the first counter signal X1 and the fifth counter signal X5 among the output counter signals of the binary counter 110 and outputs Y15. The logical product 123 performs an AND operation on the first counter signal X1 and the sixth counter signal X6 among the output counter signals of the binary counter 110 and outputs Y16. The logical product 124 performs an AND operation on the second counter signal X2 and the third counter signal X3 among the output counter signals of the binary counter 110 to output Y16. Logical multiplier 125 performs a logical AND operation on the second counter signal X2 and the fourth counter signal X4 among the output counter signals of the binary counter 110 and outputs Y16. The logical product 126 performs an AND operation on the second counter signal X2 and the fifth counter signal X5 among the output counter signals of the binary counter 110 and outputs Y16. Logical multiplier 127 performs an AND operation on the second counter signal X2 and the sixth counter signal X6 among the output counter signals of the binary counter 110 and outputs Y16. The logical multiplication 128 performs an AND operation on the third counter signal X3 and the fourth counter signal X4 among the output counter signals of the binary counter 110 to output Y16. The logical product 129 performs an AND operation on the third counter signal X3 and the fifth counter signal X5 among the output counter signals of the binary counter 110 to output Y16. The logical product 130 performs an AND operation on the fourth counter signal X4 and the fifth counter signal X5 among the output counter signals of the binary counter 110 and outputs Y16. The logical product 131 performs an AND operation on the fourth counter signal X4 and the sixth counter signal X6 among the output counter signals of the binary counter 110 and outputs Y16. The logical multiplication 132 performs an AND operation on the fifth counter signal X5 and the sixth counter signal X5 among the output counter signals of the binary counter 110 and outputs Y16. The exclusive adder (XOR) 140 performs an exclusive addition by inputting Y12, Y13, Y23, Y34, Y15, and Y46 among the outputs of the logical products 120-132, and then performs a sequence for mask 1 (M1). Output The exclusive adder 141 performs an exclusive addition by inputting Y12, Y13, Y34, Y25, Y35, Y26, Y46, and Y56 among the outputs of the logical products 120-132, and then the sequence for the mask 2 (M2). Outputs The exclusive adder 142 outputs a sequence of masks 3 (M3) for performing exclusive addition by inputting Y12, Y24, Y34, Y15, Y45, Y16, and Y56 among the outputs of the logical products 120-132. .

The operation based on the configuration will be described below.

First, the binary counter 110 operates to generate six signals. These clocks represent the Bent function in Table 1 as shown in FIG. As an example, the binary counter 110 may be implemented as something like 74HC161. As described above, among the counter signals representing the bent function output from the binary counter 110, the first counter signal X1 and the second counter signal X2 are input to the logical multiplier 120, and are logically multiplied, and then Y12 is output. This Y12 represents a sequence of signals in which X1 * X2 in M1, M2, and M3 in Table 2 is calculated. In addition, the first counter signal X1 and the third counter signal X3 are input to the logical product 121 and logically operated to output Y13, and Y13 is a sequence of signals for which X1 * X3 in M1 and M2 is calculated in Table 2 above. Indicates. In this way, logical products 120 to 132 are operated. The respective output signals (Y) generated by the logical AND operator are inputted to the corresponding exclusive adders 140, 141 and 142, respectively, and are exclusively added to the mask sequence M1 as shown in Table 2 above. , M2 and M3 occur. That is, according to the formula for the mask M1 shown in Table 2, Y12 (= X1 * X2), Y13 (= X1 * X3), Y23 (= X2 * X3), Y24 (= X2 * X4), Y15 ( = X1 * X5), Y46 (= X4 * X6) are input to the exclusive adder 140 to generate the sequences of the mask M1. In the same way, Y12 (= X1 * X2), Y13 (= X1 * X3), Y34 (= X3 * X4), Y25 (= X2 * X5), Y35 (= X3 * X5), Y26 (= X2 * X6 ), Y46 (= X4 * X6), Y56 (= X5 * X6) are input to exclusive adder 141 to create mask M2, Y12 (= X1 * X2), Y24 (= X2 * X4), Y34 (= X3). * X4), Y15 (= X1 * X5), Y45 (= X4 * X5), Y16 (= X1 * X6), Y56 (= X5 * X6) are input to exclusive adder 142 to generate mask M3.

At this time, in order to generate a quasi-orthogonal sequence of length 128, the output speed of the output of the quasi-orthogonal sequence of length 64 is doubled to generate a mask of length 128 by repeating the generated mask twice.

To generate a quasi-orthogonal sequence of length 256, it is similar to the method of quasi-orthogonal sequence of length 64. In this case, a generator of a quasi-orthogonal sequence of length 256 can be implemented by setting a clock of a binary counter according to a length and setting a logical product operator as described above corresponding to the terms shown in Table 4 above. In addition, when the complex quasi-orthogonal code corresponds to the sine component of length 256, the mask generators are implemented by configuring the operators according to the calculation formula of Table 6 above, and when the length is 512, the masks are configured by the calculation formula of Table 8 above. Implement the generator.

In other words, the sequence corresponding to the sinusoidal component of the complex quasi-orthogonal code (see Table 5 and Table 7) can also be expressed as an expression of the vent functions as in the binary quasi-orthogonal sequence (see Table 3). It is shown in 8. Accordingly, when the length is 256, the mask generators are implemented by configuring the operators in the calculation formula of Table 6, and when the length is 512, the mask generator is implemented by configuring the calculators by the calculation formula of Table 8.

As described above, the present invention provides an advantage that the mask sequence can be more easily generated by implementing the mask of the quasi-orthogonal sequence by implementing it with simple hardware.

Claims (21)

An apparatus for generating a mask sequence masked to an orthogonal sequence to generate an orthogonal sequence of length 256 in a communication system, A counter for generating eight first signals X1-eighth signal X8 representing a vent function, And a logic operator configured to logically operate the first signals X1 to X8 to generate the mask sequence having a length of 256. The method of claim 1, wherein the logical operator, By inputting the first signal X1-the eighth signal X8, X1X2 + X1 * X3 + X1 * X4 + X1 * X5 + X1 * X7 + X1 * X8 + X2 * X6 + X2 * X7 + X3 * X4 + X3 * X5 + X3 * x6 + x4 * x5 + x4 * x6 + x4 * x7 + x4 * x8 + x5 * x7 + x7 * x8 + x1 + x2 + x5 + x7 to generate the mask sequence. The method of claim 1, wherein the logical operator, X1 * X2 + X1 * X4 + X1 * X6 + X2 * X8 + X3 * X4 + X3 * X5 + X4 * X6 + X4 * X7 + X5 * X8 + X7 by inputting the first signal X1-eighth signal X8 + X8 operation to generate the mask sequence. The method of claim 1, wherein the logical operator, X1 * X2 + X1 * X3 + X1 * X5 + X1 * X6 + X1 * X7 + X2 * X3 + X2 * X4 + X2 * X7 + X3 * X6 + X3 by inputting the first signal X1-eighth signal X8 And * x8 + x4 * x5 + x5 * x7 + x5 * x8 + x6 * x8 + x7 * x8 + x5 + x6 + x7 + x8 to generate the mask sequence. An apparatus for generating a mask sequence masked to an orthogonal sequence to generate a quasi-orthogonal sequence of length 512 in a communication system, A counter for generating nine first signals X1-ninth signal X9 representing a vent function; And a logic operator configured to logically operate the first signal X1 to the ninth signal X9 to generate the mask sequence having a length of 512. The method of claim 5, wherein the logical operator X1 * X2 + X1 * X3 + X1 * X4 + X1 * X5 + X1 * X6 + X1 * X7 + X1 * X8 + X2 * X3 + X2 * X4 + X2 by inputting the first signal X1-ninth signal X9 * X5 + X2 * X6 + X2 * X7 + X2 * X8 + X3 * X4 + X3 * X5 + X3 * X6 + X3 * X7 + X3 * X8 + X4 * X5 + X4 * X6 + X4 * X7 + X4 * X8 + X5 * X6 + X5 * X7 + X5 * X8 + X6 * X7 + X6 * X8 + X7 * X8 + X1 + X3 + X4 + X5 to generate the mask sequence. The method of claim 5, wherein the logical operator X1 * X2 + X1 * X4 + X1 * X5 + X1 * X7 + X1 * X8 + X2 * X5 + X2 * X8 + X3 * X4 + X3 * X5 + X3 by inputting the first signal X1-ninth signal X9 * X6 + X3 * X8 + X3 * X9 + X4 * X7 + X5 * X8 + X5 * X9 + X6 * X7 + X6 * X8 + X6 * X9 + X7 * X8 + X7 * X9 to generate the mask sequence Device characterized in that. The method of claim 5, wherein the logical operator X1 * X2 + X1 * X4 + X1 * X5 + X1 * X6 + X1 * X7 + X1 * X8 + X2 * X3 + X2 * X4 + X2 * X7 + X2 by inputting the first signal X1-ninth signal X9 * X9 + X3 * X6 + X3 * X7 + X4 * X5 + X4 * X8 + X4 * X9 + X5 * X7 + X6 * X7 + X6 * X8 + X6 * X9 + X8 * X9 + X1 + X2 + X5 + X7 + X8 operation to generate the mask sequence. An apparatus for generating a mask sequence masked to an orthogonal sequence to generate a quasi-orthogonal sequence of length 64 in a communication system, A counter for generating six first signals X1-6th signal X6 representing a vent function; And a logic operator configured to logically operate the first signals x1-6th signal x6 to generate the mask sequence having a length of 64. The method of claim 9, wherein the logical operator, And inputting the first signals x1-6th signals x6 to perform X1 * X2 + X1 * X3 + X2 * X4 + X1 * X5 + X4 * X6 to generate the mask sequence of length 64. The method of claim 10, And repeating the mask sequence of length 64 output from the logic operator twice to generate a mask sequence of length 128. The method of claim 9, wherein the logical operator, A mask having a length of 64 by inputting the first signals x1-6th signals x6 and calculating X1 * X2 + X1 * X3 + X3 * X4 + X2 * X5 + X3 * X5 + X2 * X6 + X4 * X6 + X5 * X6 Device for generating a sequence. The method of claim 12, And repeating the mask sequence of length 64 output from the logic operator twice to generate a mask sequence of length 128. The method of claim 9, wherein the logical operator, Input the first signals x1-6th signals x6 to generate X1 * X2 + X2 * X4 + X3 * X4 + X1 * X5 + X4 * X5 + X1 * X6 + X5 * X6 to generate a mask sequence of length 64 Device characterized in that. The method of claim 14, And repeating the mask sequence of length 64 output from the logic operator twice to generate a mask sequence of length 128. The method of claim 1, wherein the logical operator, X1 * X2 + X1 * X3 + X2 * X4 + X1 * X5 + X4 * X5 + X2 * X6 + X3 * X6 + X4 * X6 + X1 * X7 + X4 by inputting the first signal x1-eighth signal x8 * X7 + x5 * x7 + x3 * x8 + x4 * x8 to generate a mask sequence of length 256. The method of claim 1, wherein the logical operator, X1 * X2 + X1 * X3 + X1 * X4 + X3 * X4 + X3 * X5 + X4 * X5 + X1 * X6 + X3 * X6 + X4 * X6 + X5 by inputting the first signal x1-eighth signal x8 A device characterized in that a mask sequence of length 256 is generated by computing * X6 + X1 * X7 + X3 * X7 + X4 * X7 + X6 * X7 + X1 * X8 + X2 * X8 + X4 * X8 + X6 * X8 . The method of claim 1, wherein the logical operator, X1 * X2 + X2 * X3 + X2 * X4 + X3 * X4 + X2 * X5 + X4 * X5 + X1 * X6 + X5 * X6 + X3 * X7 + X4 by inputting the first signal x1-eighth signal x8 * X7 + X5 * X7 + X1 * X8 + X3 * X8 + X4 * X8 + X5 * X8 + X7 * X8 to generate the mask sequence of length 256. The method of claim 1, wherein the logical operator, X1 * X2 + X2 * X3 + X1 * X4 + X1 * X5 + X2 * X5 + X3 * X5 + X4 * X5 + X2 * X6 + X4 * X7 + X6 by inputting the first signal x1-eighth signal x8 * X7 + X2 * X8 + X4 * X8 + X5 * X8 + X6 * X8 + X7 * X8 to generate a mask sequence of length 256. The method of claim 1, wherein the logical operator, X1 * X2 + X2 * X4 + X3 * X4 + X2 * X5 + X3 * X5 + X4 * X6 + X3 * X7 + X4 * X7 + X6 * X7 + X5 by inputting the first signal x1-the sixth signal x6 * X8 + x7 * x8 to generate the mask sequence of length 256. The method of claim 1, wherein the logical operator, X1 * X2 + X1 * X3 + X2 * X3 + X2 * X4 + X1 * X5 + X3 * X5 + X1 * X6 + X2 * X6 + X3 * X6 + X5 by inputting the first signals x1-6th signal x6 * X6 + X1 * X7 + X4 * X7 + X6 * X7 + X1 * X8 to generate the mask sequence of length 256.