KR100345309B1 - Apparatus and method for controlling memory and peripheral device with chip outer connection and error repair - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a control device and a method of controlling a memory / peripheral device capable of external chip connection and error recovery. The present invention performs external chip connection and error recovery, and the ASB is a basic connection. A system controller making an APB connection; An AMBA ASB connector for manipulating signals input through the ASB to generate signals of the system controller, and converting the signals generated by the system controller into signals suitable for the ASB timing standard and outputting the signals to the ASB bus; An AMBA APB access unit for generating signals of the system controller by manipulating signals input through the APB, and converting the signals generated by the system controller into signals suitable for the APB timing standard and outputting the signals to the APB bus; If the data size of the system controller differs from the data size outside the system controller, the dynamic data path logic unit performs dynamic data size reprocessing to adjust the data size. The recovery function will be supported.

Description

Apparatus and method for controlling memory and peripheral device with chip outer connection and error repair}

The present invention relates to the control of a programmable memory / peripheral device with an external chip access method and an error recovery function. In particular, the present invention strictly complies with the AMBA standard so as to be fully compatible with application chips employing the AMBA. The present invention relates to a control device and a method of controlling an external chip and an error recoverable memory / peripheral device for storing the information, selecting a connection method according to the stored information, and supporting an error recovery function.

Recently, a number of application chips based on ARM's CPU core series have been announced. This is because ARM is providing an effective and cost-effective core solution for many chip manufacturers that are in the race to develop low-power SoCs.

In this situation, ARM's Advanced Microcontroller Bus Architecture (AMBA) is expected to become a standard for product development using ARM core.

1 is a block diagram of a typical AMBA.

Here, reference numeral 1 is an external bus interface, 2 is an ARM processor, 3 is a single chip RAM inside the chip, 4 is a bridge for accessing the Advanced Peripheral Bus (APB), 5 is a UART (Universal Asynchronous Receiver Transmitter, General purpose asynchronous transceiver), 6 is a timer, and 7 is a PIO.

Therefore, AMBA is divided into two areas, namely, Advanced System Bus (ASB) area and Advanced Peripheral Bus (APB) area. The ASB plays the same role as a typical general bus structure, and the APB is a dedicated bus for modules with less bus usage in the conventional bus structure. Therefore, it can be implemented by latching the register of the APB, and the low power structure can be realized.

The present invention is intended to significantly improve the compatibility of the chip by allowing the user to programmatically select various connection methods of the application chip and external peripherals in such product development.

The memory / peripheral controller acts as a bridge to ensure accurate multiplexed access of data to bus transfers between 8, 16, and 32 bit internal / external chips.

To this end, the present invention considers largely four parts.

1) A design suitable for low-power architecture is assumed to be an on-chip chip with AMBA-based system for designing the model, ensuring full AMBA compatibility.

2) User program function is guaranteed by having external device status information register which can read / write and control it by ARM core.

3) The "error status information" bit is allocated to the external device status information register to record the error type and address / data when an error occurs, thereby improving the function of the error recovery routine (normal trap handler). do.

4) Multiple cycle function is supported for read / write when the memory data width is smaller than the internal bus data width.

A development example similar to the present invention is MITEL's Butterfly chip, which is similar in function, but not compatible with the purpose and scope of the present invention because it is not compatible with AMBA, and also MITEL's Butterfly chip The disadvantage is that it does not support error recovery.

Accordingly, the present invention has been proposed to solve the above-mentioned conventional problems, and an object of the present invention is to strictly comply with the AMBA standard so as to be fully compatible with application chips employing AMBA, and to change external peripheral devices. The present invention provides a controller and method for controlling an external chip and an error recoverable memory / peripheral device capable of storing the information, selecting a connection method according to the stored information, and supporting an error recovery function.

In order to achieve the above object, a control device of a memory / peripheral device capable of external connection and error recovery according to an embodiment of the present invention,

A system control unit for performing an external chip connection and error recovery, making an ASB a basic connection, and a user interface function making an APB connection; An AMBA ASB connector for manipulating signals input through an ASB to generate signals of the system controller, and converting the signals generated by the system controller into signals suitable for an ASB timing standard and outputting the signals to an ASB bus; An AMBA APB access unit configured to generate signals of the system control unit by manipulating signals input through an APB, and convert the signals generated by the system control unit into signals conforming to an APB timing standard and output them to the APB bus; If the data size of the system control unit and the data size of the outside of the system control unit is different from each other, the technical configuration is characterized by consisting of a dynamic data path logic unit for performing a dynamic data size reprocessing function.

In order to achieve the above object, a method of controlling an external chip and an error recoverable memory / peripheral device according to an embodiment of the present invention includes:

Setting an error recovery related register; Determining an error state when an error of the external device occurs and determining whether error recovery of the determined error is possible; If the error recovery is possible, recording an error status value and requesting an interrupt; If the error recovery is not possible, the technical configuration is characterized by performing a step of reporting a fatal error situation.

1 is a block diagram of a typical AMBA,

2 is a block diagram of a control device of a memory / peripheral device capable of external connection and error recovery according to the present invention;

FIG. 3 is a table illustrating functions of respective slices of the environmental information storage register in FIG. 2.

4 is a state transition diagram of the standby / stopped state generator in FIG.

5 is a table showing bit-by-bit allocation states of the error state storage register in FIG.

FIG. 6 is a timing diagram of executing multiple cycles when there is one standby state in FIG. 2.

7 is a flowchart illustrating a method of controlling an external chip and an error recovery memory / peripheral device according to the present invention.

Explanation of symbols on the main parts of the drawings

10: system control unit 11: standby / stop state generating unit

12: modified address generator 13: external device control signal generator

14: error state determination unit 15: state information storage unit

16: environmental information storage register 17; Error state storage register

20: AMBA ASB connection part 30: AMBA APB connection part

40: dynamic data path logic part

Hereinafter, an embodiment according to the technical concept of the apparatus and method for controlling a memory / peripheral device capable of external connection and error recovery of the present invention as described above will be described.

2 is a block diagram of a control device of a memory / peripheral device capable of external connection and error recovery according to the present invention.

As shown therein, the system controller 10 performs out-chip access and error recovery, makes the ASB the default connection, and the user interface function the APB connection; An AMBA ASB connection unit which generates signals of the system controller 10 by manipulating signals input through an ASB, and converts the signals generated by the system controller 10 into signals conforming to an ASB timing standard and outputs them to an ASB bus. 20; AMBA APB access unit for generating signals of the system control unit 10 by manipulating signals input through the APB, and converting the signals generated by the system control unit 10 to signals suitable for the APB timing standard and outputting them to the APB bus. 30; If the data size of the system control unit 10 and the data size of the outside of the system control unit 10 are different from each other, the dynamic data path logic unit 40 performs a dynamic data size reprocessing function to adjust this.

In the above, the system control unit 10 receives the information signal from the state information storage unit 14, generates a standby / stop state, generates a 'standby state' for access to a specific external device, and the slower than a specific external device A standby / stop state generator 11 for generating a 'stop wait state' for access; A modified address generator 12 generating an address suitable for an external peripheral device according to data received from the AMBA ASB connector 20 and adding a multicycle counter value to the address when performing a multicycle mode; An external device control signal generator 13 for generating a control signal for the external device; An error state determination unit 14 for discriminating whether an external device can recover an error and determining an error state; Environment information storage register 16 to enable read / write access to ARM and to program information on the external memory area, and an error state to store the address, data and type of error when an error occurs And a state information storage unit 15 having a storage register 17.

In the above, the standby / stop state generating unit 11 is configured to include an initialization state in a reset state, an internal standby generation state in which a standby state counter value is smaller than the number of standby states recorded in the environmental information storage register 16, and The transfer complete state, which has completed the waiting state, the stop state where the stop wait counter value is smaller than the stop wait number recorded in the register, the basic wait state ready for synchronization of the external wait occurrence, and the external wait request. The standby / stop state is generated including the external standby occurrence state in which the signal is '1' and the highest speed state in which there is no standby state.

In the above, the error state determination unit 14 includes an excess of addresses generated when the requested address exceeds the maximum bank size of the corresponding device, and a partial write protection memory for allowing the external memory to process sub-memory width writes. And a peripheral access error that informs the controller what type of access is being accepted by the connected external device, and an external wait request signal activated after exceeding the maximum number of stop waits (2 ⁴ ). An error condition is determined by exceeding the maximum number of stop waits.

7 is a flowchart illustrating a method of controlling an external chip and an error recovery memory / peripheral device according to the present invention.

As shown therein, setting an error recovery-related register (ST11); Determining an error state when an error of the external device occurs and determining whether error recovery of the determined error is possible (ST12 to ST14); If the error recovery is possible, recording an error state value and requesting an interrupt (ST15) (ST16); If the error recovery is not possible, the step ST17 of reporting a fatal error situation is performed.

Referring to the accompanying drawings, the operation of a control device and a method of a memory / peripheral device capable of external connection and error recovery according to the present invention configured as described above will be described in detail as follows.

First, in the present invention, the ASB connection is based on the characteristics of the module, but in order to realize a low power structure, the user interface functional blocks select the APB connection method.

Thus, the AMBA ASB / APB connection unit 20 and 30 manipulate internal signals input through the ASB / APB to generate internal signals, and change the internally generated signals into signals that conform to the ASB / APB timing standard. Outputs to the APB bus. The function of the AMBA ASB / APB connection 20, 30 can ensure AMBA compatibility.

The standby / stopped state generator 11 is configured to be programmable. Thus, the standby / stop state generator 11 can generate a programmable 'standby state' for accessing a specific external device, and generates a 'stop wait state' for access to a slower device. To this end, it has a state machine that receives the information signal from the state information storage unit 14 that manages the characteristic information of the external memory area and generates a standby / stop state. The state transition diagram of the standby / stop state generator 11 is as shown in FIG. 4, and the definition of each state is as follows.

* State Definition

; Reset Status-Reset Status

; Internal Standby Occurrence State-The state of the standby state counter is smaller than the number of standby states recorded in the environmental information storage register 16.

; Transmission completed status-completed waiting status set

; Stop Status-The Stop Wait Counter value is less than the Stop Wait number recorded in the register.

; Default standby state-ready state for synchronous external standby occurrence

; External standby state-External standby request signal '1'

; Full Speed State-Full Speed State with No Standby (Single Cycle Access)

In addition, the modified address generator 12 has a multicycle mode support function. Thus, the modified address generator 12 generates an address for an external peripheral device according to the data of the 32-bit address bus received from the ASB through the AMBA ASB connector 20. When performing the multiple cycle mode, add the multiple cycle counter value to the address.

In addition, the external device control signal generator 13 generates a control signal for the external device.

In addition, the error state determination unit 14 is composed of a register that distinguishes whether or not the error recovery is possible and the error state determination logic. The function definition for each slice of the register that distinguishes whether the error recovery is possible is shown in FIG. 5. Each bit assigned to FIG. 5 is matched one-to-one to each of the error state types (lowest order by bit). That is, the bit corresponding to the address exceeding error corresponds to the register [0], and if it is set to '1', it means that the recovery is possible. This register is read / writeable by ARM, enabling various error recovery routine designs.

The error state determination logic receives all the information signals related to the external interface of the chip to determine the type of error that occurs, and if the error is a recoverable error, sets the determined information in the error state information bit of the external device information register and then interrupts. It is in charge of requesting. However, if an unrecoverable error (fatal error) is reported, the fatal error is reported to the system controller without immediately requesting an interrupt, thereby eliminating unnecessary processes for dealing with an unrecoverable error.

7 shows the processing flow of the error state determining unit 14.

The following shows the values assigned according to the error occurrence state.

1) Address over: '0'

; This error occurs when the requested address exceeds the device's maximum bank size.

2) Write error to partial write inhibit memory: '1'

; As with the function of the partial write [3] bit of the state information storage unit 15, it means that the external memory can process the sub-memory width write. sub-memory width write indicates write access when the operand is less than the word width in memory. If this bit is cleared and an address is detected to write data less than the data size [1: 0], then 'Data Abort' Occurs.

3) Peripheral device access error: '2'

; This error tells the controller what type of access is being accepted by the connected external device. Peripherals can be used for operand packing (dynamic data paths, such as packing two 16-bit data into 32-bit data to handle if the memory data width and internal operand data width are different) or sub memory width access (one address data in memory). For the area where the M (Memory) / P (Peripheral) bit is '0', so that if the operand size is not equal to the memory size, Abort 'occurs.

4) Maximum number of stop waits exceeded: '3'

; Occurs when the external wait request signal is activated even after the maximum number of stop waits (2 ⁴ ) is exceeded.

In addition to these defined errors, the user can define up to 32 errors and determine whether they can be recovered or programmed.

On the other hand, the state information storage unit 15 has eight 32-bit registers to program information about eight external memory areas, and is designed to enable read / write access to the ARM. In addition, to support the error recovery function, 16 address storage / data storage registers that can store the address, data and type of error when an error occurs are built in. The standby / stopped state generator 11 is operated in accordance with each bit slice information (Fig. 3) of the environment information storage register 16 in the state information storage 15.

The function definition for each slice of the environment information storage register 16 is as follows.

The data size [1: 0] bits tell the internal state machine the size of the external data bus connected to the external device. ('00'-byte, '01'-hardword, '1x'-word)

The M / P [2] bit tells the controller what type of access is being accepted by the connected external device. Peripherals can be used for operand packing (dynamic data paths, such as packing two 16-bit data into 32-bit data to handle if the memory data width and internal operand data width are different) or sub memory width access (one address data in memory). For the area where the M (Memory) / P (Peripheral) bit is '0', so that if the operand size is not equal to the memory size, Abort 'occurs.

* If the Partial Write [3] bit is set, it indicates that the external memory can handle sub-memory width writes. sub-memory width write indicates write access when the operand is less than the word width in memory. When this bit is cleared and an address for writing data smaller than the data size [1: 0] is detected, 'Data Abort' occurs.

* If the read only [4] bit is set, it indicates that only read access can be performed for the connected external device. If the bus attempts to write to this external device, it generates a 'data abort'.

* If the auto wait [5] bit is set, it means that the access currently being performed has a wait state controlled by the internal wait / stop state generator 11. If this bit is cleared, it means that the wait state is controlled by an external wait request signal.

The error status [20:23] bits indicate the status of an error occurring in access to the device, and this value permits only read operations by the ARM, and the error status determination section 14 executes the write operation.

Meanwhile, when the data size inside the chip and the data size outside the chip are different from each other, the dynamic data pass logic unit 40 performs a dynamic data size reprocessing function to adjust the data size.

The operation of the dynamic data path logic unit 40 may be divided into two cases according to the relationship between the internal bus data size and the memory data size.

(1) Internal data size = <Memory data size

; In this case, normal normal data transfer is performed.

(2) Internal data size> Memory data size

; In this case, multiple cycles are performed. To this end, the modified address generator 12 generates a separate address according to the multiple cycle counter value.

6 shows a timing diagram for the execution of multiple cycles of the dynamic data path logic unit 40.

As such, the present invention strictly complies with the AMBA standard so as to be fully compatible with application chips employing AMBA, and stores the information when changing external peripheral devices, selects an access method according to the stored information, and provides an error recovery function. It will be supported.

Although the preferred embodiment of the present invention has been described above, the present invention may use various changes, modifications, and equivalents. It is clear that the present invention can be applied in the same manner by appropriately modifying the above embodiments. Accordingly, the above description does not limit the scope of the invention as defined by the limitations of the following claims.

As described above, the control device and method of the memory / peripheral device capable of external connection and error recovery according to the present invention strictly comply with the AMBA standard so as to be fully compatible with application chips employing the AMBA, and the external interface. Designed to develop AMBA-enabled chips by ensuring the low power of the module, ensuring user programmability that can be applied to changes in device characteristics of external peripheral devices, and supporting programmable error recovery functions Intellectual Property (IP) It can be used as an effect. Through this, even if the memory and other peripherals outside the chip is changed, by programming the information there is an effect that can contribute to improved performance and compatibility of the developed chip.

Claims (5)

A system control unit for performing an external chip connection and error recovery, making an ASB a basic connection, and a user interface function making an APB connection; An AMBA ASB connection unit for generating signals of the system controller by manipulating signals input through an ASB, and converting the signals generated by the system controller into signals conforming to an ASB timing standard and outputting the signals to an ASB bus; An AMBA APB access unit configured to generate signals of the system control unit by manipulating signals input through an APB, and convert the signals generated by the system control unit into signals conforming to an APB timing standard and output them to the APB bus; When the data size of the system control unit and the data size outside the system control unit are different from each other, a dynamic data path logic unit configured to perform a dynamic data size reprocessing function for adjusting the external chip and error recoverable memory / periphery Control of the device. The method of claim 1, wherein the system control unit, Receives an information signal from the status information storage unit and generates a standby / stop state, creating a 'standby state' for accessing a specific external device, and a standby for generating a 'stop wait state' for accessing a device slower than a specific external device. / Stop state generating section; A modified address generator for generating an address suitable for an external peripheral device according to data received from the AMBA ASB connection unit, and adding a multicycle counter value to an address when performing a multicycle mode; An external device control signal generator for generating a control signal for the external device; An error state determination unit for discriminating whether an external device can recover an error and determining an error state; To enable read / write access to ARM and to program information about the external memory area, an environment information storage register and an error state storage register that can store the address, data and type of error when an error occurs An apparatus for controlling an external chip and an error recoverable memory / peripheral device comprising a state information storage unit provided. The method of claim 2, wherein the standby / stop state generating unit, Initialization status in reset status, internal standby occurrence status in which the standby status counter value is smaller than the number of waiting statuses recorded in the environmental information storage register, transfer completion status in which the set standby status is completed, and stop standby counter value A stop state that is less than the stop wait number recorded in this register, a basic wait state that is ready for synchronization of an external wait occurrence, an external wait occurrence state in which an external wait request signal is '1', and a standby state An external chip and error-recoverable control device for memory / peripheral devices, characterized by generating a standby / stop state including a maximum speed state which is a maximum speed state. The method of claim 2, wherein the error state determination unit, Address overruns generated when the requested address exceeds the maximum bank size of the device, write errors to partially write-protected memory allowing the external memory to handle sub-memory width writes, and are accepted by the connected external device. The error status is determined by a peripheral access error that informs the controller what type of access is being made, and by exceeding the maximum number of stop waits generated when the external wait request signal is activated after exceeding the maximum number of stop waits. A memory / peripheral control device capable of external connection and error recovery. Setting an error recovery related register; Determining an error state when an error of the external device occurs and determining whether error recovery of the determined error is possible; If the error recovery is possible, recording an error status value and requesting an interrupt; And if the error recovery is not possible, reporting a fatal error condition, and performing an external chip access and error recovery memory / peripheral device.