KR100344952B1 - Correct method of frequency synthesizer noise of PLL module - Google Patents

Abstract

The present invention provides an oscillator for generating a constant frequency signal in a specific frequency band, a voltage controlled oscillator for generating a frequency corresponding to an input voltage, and a frequency generated from the voltage controlled oscillator and a frequency generated from the oscillator. A phase locked loop module having a PLL for receiving a signal and varying a magnitude of a voltage applied to the voltage controlled oscillator. In particular, the output stage of the reference frequency signal output from the voltage controlled oscillator is dualized and dualized. One output stage is provided with an inlet signal blocking means at one output stage and the other output end is provided with an inlet signal blocking means at a first stage and at the output stage having the inlet signal blocking means at the first stage. Second step of transmitting the reference frequency signal to the transmitting and receiving means side And a third step of transmitting the reference frequency signal output from the output stage not provided with the inverse signal blocking means in the first step to the PLL side. Since the reference frequency generated by the conventional voltage controlled oscillator is output through the output pad, the signal applied to the PLL side adversely affects the harmonic characteristics by the passive element constituting the output pad, and also is inversely introduced from the antenna side to the PLL side. The problem of interference caused by noise can be solved.

Description

Correction method of frequency-synchronized noise of phase-locked module {Correct method of frequency synthesizer noise of PLL module}

The present invention provides a PLL integrating a PLL and a loop filter with a voltage controlled oscillator used as a local oscillator signal source when down converting a signal received through an antenna or up converting a transmission signal in a wireless transceiver. The present invention relates to a method of improving frequency mixed noise of a phase synchronization module to obtain stable call quality of a mobile phone and to improve noise quality.

In general, wireless communication devices modulate transmission data to be transmitted and received on a carrier frequency signal for transmission and reception of wireless data, and when receiving, limit a carrier frequency in a received scan signal and demodulate it.

At this time, the frequency generating means used to generate or remove the carrier frequency or channel frequency during transmission and reception is a PLL module, which is a device for generating a frequency signal commonly referred to as a reference frequency.

As described above, the PLL module is configured as shown in FIG. 1, and in FIG. 2, the reference frequency oscillator 31 and the amplification unit are configured as an internal configuration of the voltage controlled oscillator 300 of FIG. 1. 32, a negative feedback resistor 33, and an output pad 34. As shown in FIG.

Among the components, the reference frequency oscillator 31 has a first coil L1 having one end connected to an input terminal In and receiving a control voltage generated from a PLL connected to the input terminal In, and the first coil. The cathode terminal is connected to the other end of L1 and the anode terminal is connected to the ground terminal, and the second diode is connected to the varactor diode VD and the two capacitors are connected in series. And a second coil L2 having one end connected to a connection point of the third capacitor C2 and C3, the second capacitor C2 and the third capacitor C3, and the other end connected to the ground terminal, and the second coil. The fourth capacitor C4 has one end connected to the connection point of the capacitor C2 and the third capacitor C3.

In addition, the amplifying unit 32 includes a transistor Q1 receiving an arbitrary positive voltage Vcc through the third coil L3 and the positive voltage Vcc applied to the third coil L3. A fifth capacitor (C5) charged by the second capacitor), a first resistor (R1) having a voltage applied to the third coil (L3) at one end and the other end connected to a base terminal of the transistor (Q1), A sixth capacitor C6 charged by the voltage applied to the first resistor R1, a seventh capacitor C7 charged by the voltage applied to the emitter terminal of the transistor Q1, and the transistor Q1. The second transistor (Q2) connected to the emitter terminal of the emitter terminal), the second resistor (R2) and the second transistor connecting the base terminal of the first transistor (Q1) and the second transistor (Q2) And a third resistor R3 connected between the base terminal of Q2 and the ground terminal.

In addition, the negative feedback resistor unit 33 is connected to the base terminal and the emitter terminal of the second transistor Q2 and is charged with the voltage output through the second resistor R2. And a ninth capacitor C9 charged by the voltage across the emitter terminal of the second transistor Q2, and a fourth resistor connected between the emitter terminal of the second transistor Q2 and the ground terminal. R4).

Finally, the output pads 34 are connected in series and are connected to the collector terminal and the ground terminal of the first transistor Q1 as a whole, and the tenth and eleventh capacitors C10 and C11, and the tenth and eleven capacitors. And a twelfth capacitor C12, one end of which is connected to the connection points of the C10 and C11.

Looking at the operation of the voltage controlled oscillator during the operation of the PLL module having a voltage controlled oscillator configured as described above, the control voltage output from the PLL 200 flowing through the input terminal (In) is the voltage of the varistor diode (VD) LC resonance is performed by the third capacitor C3 and the second coil L2 only when the threshold voltage is higher than or equal to the threshold voltage, and corresponds to the intrinsic value of the third capacitor C2 and the second coil L2 and the magnitude of the applied voltage. Specific frequency is generated.

Accordingly, the resonant frequencies of the third capacitor C3 and the second coil L2, which are components of the reference frequency oscillator 31, are caught by the base terminal of the second transistor Q2 constituting the amplifier 31. The second transistor Q2 is turned on / off according to the voltage state of the resonance frequency applied to the base terminal.

Only when the second transistor Q2 is turned on, the current conduction path of the first transistor Q1 is formed, thereby outputting the amplified reference frequency through the output pad 34.

In this case, the reference frequency generated by the voltage controlled oscillator 300 is transmitted to the RF transmitter / receiver and down-converts a signal received through an antenna, or as a local oscillator signal source when up-converting a transmitted signal. To be used. In addition, it is fed back to the PLL 200 side and used as a detection signal for adjusting the magnitude of the voltage applied to the voltage controlled oscillator 300 from the PLL 200 side.

At this time, since the reference frequency generated by the voltage controlled oscillator 300 is output through the output pad 34 provided to prevent the reverse feedback, the signal applied to the PLL 200 is applied to the passive element constituting the output pad. This adversely affects the harmonic characteristics, and the PLL 200 has a problem in that it is not possible to accurately adjust the magnitude of the voltage required to control the voltage controlled oscillator 300 by the noise flowing back from the antenna side.

An object of the present invention for solving the above problems is a voltage control used as a local oscillator signal source when down converting a signal received through an antenna or up converting a transmission signal in a wireless transmitting / receiving device The present invention provides a method for improving frequency mixing noise of a phase synchronization module to obtain excellent call quality of a mobile phone by improving stable frequency oscillation control and noise characteristics of a PLL module integrating an oscillator, a PLL, and a loop filter.

1 is a block diagram illustrating a conventional phase locked loop module;

2 is an exemplary circuit configuration of the voltage controlled oscillator shown in FIG.

3 is an exemplary block diagram of a phase locked loop module according to the present invention;

FIG. 4 is an exemplary circuit configuration of the voltage controlled oscillator shown in FIG. 3, FIG. 5 is an illustration of a 2nd harmonic frequency according to the prior art, FIG. 6 is an illustration of a 2nd harmonic frequency according to the present invention, and FIG. Fig. 8 is a PN characteristic diagram according to the present invention, Fig. 8 is a PN characteristic diagram according to the present invention, and Fig. 9 is a data table illustrating the characteristic improvement of the present invention corresponding to the prior art.

Features of the present invention for achieving the above object, the oscillator for generating a constant frequency signal of a specific frequency band, a voltage controlled oscillator for generating a frequency of a magnitude corresponding to the input voltage, and generated in the voltage controlled oscillator A phase locked loop module having a PLL for receiving a frequency and a frequency signal generated by the oscillator to change a magnitude of a voltage applied to the voltage controlled oscillator, comprising: an output terminal of a reference frequency signal output from the voltage controlled oscillator; One of the two output binarized and dualized output stages is provided with a reverse inlet signal blocking means, and the other output stage has no first inlet signal blocking means, and the first stage has a reverse inlet signal blocking means. The reference frequency signal output from the output terminal The second step of transmitting to the side, and the reference frequency signal output from the output stage that is not provided with the inverse signal blocking means in the first step comprises a third step of transmitting to the PLL side.

The above object and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

The technical idea of the present invention is that the same reference frequency output terminal is divided into two conventionally, one reference frequency output terminal is connected to the transmitting and receiving means side, and the other reference frequency output terminal is connected to the PLL side, thereby affecting noise or reference affected by the received signal. This is to prevent the harmonic character deterioration caused by the output pad provided in the signal output terminal.

The PLL module to which the technical idea of the present invention is applied as described above is configured as shown in FIG. 3, and in FIG. 4, the reference frequency is defined as an internal configuration of the voltage controlled oscillator 300 of FIG. 3. The oscillation part 31, the amplifier 32, and the negative feedback resistor 33 are comprised.

Among the components, the reference frequency oscillator 31 has a first coil L1 having one end connected to an input terminal In and receiving a control voltage generated from a PLL connected to the input terminal In, and the first coil. The cathode terminal is connected to the other end of L1 and the anode terminal is connected to the ground terminal, and the second diode is connected to the varactor diode VD and the two capacitors are connected in series. And a second coil L2 having one end connected to a connection point of the third capacitor C2 and C3, the second capacitor C2 and the third capacitor C3, and the other end connected to the ground terminal, and the second coil. The fourth capacitor C4 has one end connected to the connection point of the capacitor C2 and the third capacitor C3.

In addition, the amplifying unit 32 includes a transistor Q1 that receives an arbitrary positive voltage Vcc through the third coil L3 and the positive voltage Vcc applied to the third coil L3. A fifth capacitor (C5) charged by the second capacitor), a first resistor (R1) having a voltage applied to the third coil (L3) at one end and the other end connected to a base terminal of the transistor (Q1), A sixth capacitor C6 charged by the voltage applied to the first resistor R1, a seventh capacitor C7 charged by the voltage applied to the emitter terminal of the transistor Q1, and the transistor Q1. The second transistor (Q2) connected to the emitter terminal of the emitter terminal), the second resistor (R2) and the second transistor connecting the base terminal of the first transistor (Q1) and the second transistor (Q2) And a third resistor R3 connected between the base terminal of Q2 and the ground terminal.

In addition, the negative feedback resistor unit 33 is connected to the base terminal and the emitter terminal of the second transistor Q2 and is charged with the voltage output through the second resistor R2. And a ninth capacitor C9 charged by the voltage across the emitter terminal of the second transistor Q2, and a fourth resistor connected between the emitter terminal of the second transistor Q2 and the ground terminal. R4).

At this time, the configuration as described above is not different from the conventional configuration shown in FIG. 2, except that the output terminal of the reference frequency signal generated by the conventional voltage controlled oscillator is binarized and the output terminal has a capacitor for blocking the inflow signal ( C10), and the other output terminal is not provided with a capacitor for blocking the inflow signal.

In addition, the transmission and reception terminal that requires a reference frequency signal transmits a reference frequency signal through the inverse signal blocking capacitor (C10), and to the PLL side through an output terminal that is not connected to any passive elements.

Looking at the operation of the voltage controlled oscillator during the operation of the PLL module having a voltage controlled oscillator configured as described above, the control voltage output from the PLL 200 flowing through the input terminal (In) is the voltage of the varistor diode (VD) LC resonance is performed by the third capacitor C3 and the second coil L2 only when the threshold voltage is higher than or equal to the threshold voltage, and corresponds to the intrinsic value of the third capacitor C2 and the second coil L2 and the magnitude of the applied voltage. Specific frequency is generated.

Accordingly, the resonant frequencies of the third capacitor C3 and the second coil L2, which are components of the reference frequency oscillator 31, are caught by the base terminal of the second transistor Q2 constituting the amplifier 31. The second transistor Q2 is turned on / off according to the voltage state of the resonance frequency applied to the base terminal.

Only when the second transistor Q2 is turned on, the current conduction path of the first transistor Q1 is formed, thereby changing the voltage applied to the collector terminal of the second transistor Q2, that is, the frequency signal. The signal is transmitted to the RF transmitter / receiver side through the tenth capacitor C10 and accordingly is used as a local oscillator signal source when down converting a signal received through an antenna or up converting a transmission signal.

In addition, the reference frequency fed back to the PLL 200 side is directly transmitted with a change in voltage applied to the collector terminal of the second transistor Q2 directly. FIG. 5 is a diagram illustrating a 2nd harmonic frequency according to the related art. FIG. 6 is an exemplary diagram of a 2nd harmonic frequency according to the present invention corresponding to the frequency characteristics in the prior art shown in FIG. 5. In addition, FIG. 7 is a PN according to the prior art. Noise characteristic diagram, and FIG. 8 is a PN characteristic diagram according to the present invention corresponding to the frequency characteristic in the prior art shown in FIG. 7. FIG. The graphs are as shown in FIG. 9. At this time, when looking at the graphs of FIGS. 5 to 8, the meaning of delta MKR = -19.33 dB in the 2nd hamonic comparison graph is the largest p on the left side of the graph. The difference between eak (marked with a triangle mark: magnetic frequency) and the second largest peak (marked with diamonds: 2nd hamonic), the larger the difference, the better the frequency characteristic.In addition, the spot freq is 30khz on the PN characteristic graph. Also known as offset freq, it means the frequency 30khz away from the magnetic frequency, where -112.67dbc means that the noise at 30kHz away from the magnetic frequency is -112.67dbc. It shows the noise of 30 kHz away from the frequency (in this case 966 MHz), and the horizontal axis shows 100 Hz to 1 MHz, which is the log scale of the noise value from 100 Hz away from the magnetic frequency (966M) to 1 MHz away. In other words, the lower the noise value, the better the noise characteristics. It is to be understood that there are a number of improvements over the prior art. Although the invention has been shown and described in connection with specific embodiments, it is within the scope and spirit of the invention as indicated by the claims. It will be readily apparent to those of ordinary skill in the art that various modifications and variations are possible.

The problem caused in the prior art by providing a method of improving the frequency mixing noise of the phase synchronization module according to the present invention operating as described above, that is, the reference frequency generated in the voltage controlled oscillator is provided with an output pad provided to prevent inverse feedback. Since it is output through the PLL side, the passive element constituting the output pad adversely affects the harmonic characteristics, and on the PLL side, the amount of voltage required to control the voltage controlled oscillator is controlled by the noise flowing back from the antenna side. It can solve the problem of not being able to adjust correctly.

Claims (1)

An oscillator for generating a constant frequency signal of a specific frequency band, a voltage controlled oscillator for generating a frequency corresponding to an input voltage, and a frequency generated from the voltage controlled oscillator and a frequency signal generated from the oscillator A phase locked loop module having a PLL that receives and varies a magnitude of a voltage applied to the voltage controlled oscillator: A first step of dualizing an output terminal of the reference frequency signal output from the voltage controlled oscillator and having an inflow signal blocking means at one output terminal of the dualized output terminal, and having no inflow signal blocking means at the other output terminal; ; A second step of transmitting the reference frequency signal output from the output terminal including the inverse signal blocking means in the first step to the transmitting and receiving means; And And a third step of transmitting the reference frequency signal output from the output stage not provided with the inverse signal blocking means in the first step to the PLL side.