KR100342732B1 - Word Line Driver Circuits and Methods - Google Patents

Abstract

A driver circuit for use in a semiconductor memory array is disclosed. The memory array includes a plurality of driver circuits, each of which is used to drive a word line of the memory array. The driver circuit of the present invention includes a pull-up part and an active pull-down part. The pull-up part includes a pair of subordinate transistors arranged to pull up an output node coupled to a word line. The active pulldown section includes a pair of subordinate transistors arranged to pull down the running node coupled to the wordline. The control feedback path is coupled between the output node and the active pulldown of the driver circuit. The feedback path controls the activation of the pulldown portion of the driver circuit.

Description

Wordline Driver Circuits and Methods

Background of the Invention

Field of invention

FIELD OF THE INVENTION The present invention relates to semiconductor memories, particularly high speed, low power wordline driver circuits.

Description of the Prior Art

In a semiconductor memory array having 2 ⁿ word lines, an n-bit address input is required to select one line of word lines. Each word line of the array includes a decoder circuit and a driver circuit. All decoder circuits receive and decode n bit address inputs and in response, one word line of the array is selected. The driver circuit of the selected word line drives the selected word line, thus allowing memory cells or a plurality of memory cells of the selected word line to be accessed. At this time, all other word lines in the array are deselected.

For some applications, such as cache memory on microprocessor chips, fast memory cycle times and low power consumption are required. Memory cycles are time between successive operations, ie read or write. The rise time, recovery time and power consumption of the driver circuits are all critical to the overall performance of the memory.

Conventional wordline driver circuits are described in a paper entitled "An Experimental Soft-Error Immune 64-Kb 3ns Bipolar Ram" by Kunihiko Yamaguchi et al., 1988, IEEE Bipolar Circuits and Techno1ogy Meeting. FIG. 3 illustrates a two-stage dependent transistor driver circuit that pulls up a selected word line in response to a word line selection signal. The first discharge circuit is coupled to the intermediate node between the two stage dependent transistors. The second discharge circuit is coupled to the output node for driving the word line. Each discharge circuit includes a pair of dependent transistors, a capacitor, and a pair of resistors. The driver circuit has several disadvantages. First, the two discharge circuits each include a constant current source that consumes power regardless of whether a word line is selected or not. Thus, the size of the memory array is limited for a given power. Second, the discharge circuit is active when a row is selected, thus slowly slowing down the pull-up time of the driver. Third, the capacitor and resistor of each discharge circuit generate an RC constant that determines the time period during which the discharge circuit is ON. The RC time constant may vary between wafers due to process deviations. Therefore, the discharge circuit is very sensitive to processing and it is very difficult to make the timing of the discharge circuit coincide with the timing of the memory cycle.

Another conventional driver circuit is 1988, IEEE Journal of Solid-State Circuits, Vol. It is described in a paper entitled "A 4-ns 4Kx1-bit Two-Port BiCMOS SRAM" by Yang et al. FIG. 8 of the above paper describes a two-stage Darlington driver circuit for each word line. A common pulldown current source is coupled to the output of each driver circuit through a resistor. Shared current sources reduce power consumption, but slow down the circuit's operation. In the case where all word lines are unselected, the constant current source is equally shared among all driver circuits. If one word line is selected, the selected driver circuit induces more current than the inactive driver. When the driver drives the word line, the rise time of the selected word line is slow because the driver must supply more current to the resistor, so less current is practically available to drive the word line.

The recovery time of the selected wordline is very slow because the pulldown resistor and wordline capacitance cause RC delay during the pulldown. Moreover, if there is overlap between the selected wordline and other unselected wordlines, a common phenomenon in SRAM, the newly selected wordline driver is used to pull down the newly unselected wordline. The recovery time of an unselected word line is further increased because it steals a large amount of current.

Another driver circuit is 1991, IEEE, C.T. It is described in a paper titled "High Speed Low-Power Charge-Buffered Active Pull Down ECL Circuit" by Chuang et al. Figure 1b of the paper describes a driver with an active pulldown circuit. The driver is coupled between the word line and the NOR side of the ECL differential pair decoder. The active pulldown circuit includes a capacitor and a pulldown transistor coupled to the OR side of the ECL differential pair decoder. During wordline recovery, the capacitor is discharged through the pulldown transistor when the current is switched through the OR side of the differential pair. As a result, the pulldown transistor is turned on, providing an active pulldown path between the word line and ground. At this time, the charging of the capacitor is discharged and the pull-down transistor is turned off. The active pulldown circuit also has some disadvantages. Since the gain β of the pull-down transistor can vary from one wafer to another during manufacturing, it is difficult to determine the exact size of the capacitor. If the gain of the pull-down transistor does not match the size of the capacitor, the pull-down transistor may not be turned on sufficiently reliably or may turn off very slowly and consumes power unnecessarily. Capacitors are also intended to be very large and occupy useful space in semiconductor dies.

Summary of the Invention

The present invention discloses a word line driver for a memory array. Driver circuits include many new features that provide the best speed performance and reduced power consumption that are not possible with conventional driver circuits. In a preferred embodiment of the present invention, a plurality of driver circuits are used in the memory array, each of which is used to drive a word line. All driver circuits in the memory array share a single common pulldown current source.

The driver circuit of the present invention includes a pull up portion and an active pull down portion. The pullup section includes a pair of slave transistors arranged to pull up an output node coupled to a wordline. The active pulldown section includes a pair of dependent transistors arranged to pull down an output node coupled to a wordline. The control feedback path is coupled between the output node and the active pull down portion of the driver circuit and is used to control the activation of the pull down portion of the driver circuit.

The driver circuit of the present invention has three states of operation, an inactive state, a driving state, and a recovery state. In the inactive state, the pull-up portion of the driver circuit is inactive and the corresponding word line is deselected. Since all driver circuits are identical, the shared current source is equally distributed among all driver circuits of the memory array. In the driving state, the pull up portion of the selected driver circuit is activated and the corresponding selected word line is pulled up. The control feedback path prevents activation of the active pulldown portion of the selected driver circuit. In the recovery state, the wordline decoder deactivates the pullup portion of the selected driver circuit after the appropriate access time. After that, the control feedback path activates the pull down portion of the driver circuit.

As a result, the transistor of the active pulldown part is turned on and the output node is pulled down. After the output node is pulled down, the active pulldown section automatically terminates, and the selected driver circuit returns to the expected inactive state of the next memory cycle.

The driver circuit of the present invention provides many advantages. The rise time of the driver circuit is very fast because the active pulldown circuit is OFF during the pullup of the word line. The recovery time of the driver circuit is also very fast because the pullup is inactive while the active pulldown pulls down the wordline. The driver circuit consumes very little power because a single pull-down current source is shared among all drivers in the memory array. Finally, the driver circuit is highly manufacturable because the pull up portion and the active pull down portion match. The only requirement for proper realization and operation of the driver circuit of the present invention is the standard ECL matching between the same devices. In contrast, conventional driver circuits with RC constants are much more processing-sensitive and therefore less manufacturable because of timing issues coupled to the active pulldown portion of the circuit.

Description of the Preferred Embodiments

Referring to FIG. 1, a logic block diagram of an embedded access tree (EAT) memory array 10 is shown. The purpose of the above figure is to disclose a logical relationship between the various components of the EAT memory array 10 blinded with respect to the present invention, and is not necessarily intended to show the actual layout of the components on the semiconductor die.

Of particular relevance to the present invention are global wordline (GWL) decoders 20 _(1-g ), GWL drivers 22 _(1-g ), GWL 24 _(1-g ), bitlines 26 _{(1). m)} ), the global sense amplifiers 28 _(1-m ) and a single common pulldown current source I29. GWL decoder 20 _(1-g) and GWL driver 22 _(1-g ) are each associated with subarray 12 _(1-g) . Each subarray 12 includes a local word line (not shown). The total number of rows ^{2n in} the EAT memory is equal to the product of the number of local rows per subarray and the number of subarrays 12 ( ²ⁿ = g × l). Bit lines 28 _(1-m) respectively couple memory cells of m rows to global sense amplifiers 28 _(1-m) .

In order to explain the operation of the optimal mode of the present invention, the GWL driver 22 of the present invention is a built-in sense amplifier (ESA) of EAT memory disclosed in detail in the above-mentioned parent application entitled "Random Access Memory Design" as disclosed herein. It is used to drive. The EAT memory is an 8K byte SRAM array for use as a first level cache on a semiconductor die containing a microprocessor device. The EAT array includes 256 (m = 256) columns and 256 (2 ⁿ = 256) rows of memory cells. In the particular embodiment described in the parent application, the rows are grouped in 16 subarrays (g = 16). Each subarray contains 16 local rows (l = 16) of memory cells. The common pulldown current source I29 is approximately 24.6 mA in the EAT memory array described above.

Various components of the EAT memory array 10 of the present invention may be laid out on a semiconductor die in multiple arrangements. For example, the actual layout of the EAT memory 100 may be as shown and described in FIGS. 3 and 5 of the parent application described above. In particular, several subarrays can be laid out on the die so that they can be multiplexed together and the global bits can be shared.

Global Wordline Decoder and Driver Circuit

Referring to FIG. 2, a schematic of the GWL decoder 20 and the GWL driver 22 is shown. These two circuits are described in detail below.

Global Wordline Decoder

GWL decoder 20 includes transistors Q30, Q32, and Q34 arranged in emitter coupled logic (ECL) differential configuration, transistor Q36 and resistor R38 forming a constant differential current source I35 for the differential configuration. ), A standard 0R decoder logic 40, and a pullup resistor R42. The base of Q30 is coupled to the output of OR decoder logic 40, the collector is coupled to node A, and the emitter is coupled to node B. The base of Q32 is coupled to the " write " disable input, the collector is coupled to node A, and the emitter is coupled to node B. The base of Q34 is coupled to reference voltage Vb3, the collector is coupled to node C, and the emitter is coupled to node B. The base of Q36 is coupled to the reference voltage Vcs, the collector is coupled to node B, and the emitter is coupled to ground through resistor R38. The 0R decoder logic 40 is coupled to receive address inputs A ₁ -A _n from an address register (not shown) of the EAT memory 10. Node A is coupled to Vcc via pullup resistor R42.

Global Wordline Driver

The GWL driver 22 includes a pull up unit 50 and an active pull down unit 70. The GWL driver 22 is coupled to and drives one of the plurality of GWLs 24 _(i) .

The pull-up unit 50 includes transistors Q52, Q54 and Q56, a diode D58, and a resistor R60. The base of Q52 is coupled to node A, the collector is coupled to Vcc, and the emitter is coupled to node D. The base of Q54 is coupled to node D, the collector is coupled to Vcc, and the emitter is coupled to output node E. The base of Q56 is coupled to Vcs, the collector is coupled to node (D), and the emitter is coupled to Vee via R60.

GWL 24 _(i ) is coupled to the output node E.

The active pulldown portion 70 of the GWL driver 22 includes transistors Q72 and Q74, diodes D76, resistors R78 and R80, and a shared pulldown current source I29. The base of Q72 is coupled to node C, the collector is coupled to output node E, and the emitter is connected to node F. The base of Q74 is coupled to node F, the collector is coupled to output node E, and the emitter is coupled to constant current source I29. Diode D76 and resistor R80 are coupled in series between node F and constant current source I29. Resistor R78 is coupled between node C and output node E. The coupling of resistor R78 between output node E and node C provides a control feedback path 79 that controls the activation of pull-down section 70 depending on the state of driver circuit 22. The pulldown current source I29 is shared between the active pulldown sections 70 of all subarrays 12 _(1-g ) of the EAT memory 100.

The comparative magnitudes of the transistor, diode and resistance values of the GWL driver circuit 22, according to describing the optimal mode of the present invention, are described in the table below.

action

The GWL decoder 20 and the GWL driver 22 have three states of operation, an inactive state, a driving state, and a recovery state. The GWL decoder 20 and the GWL driver 22 operate in a new way in each state that greatly improves the speed and power supply performance of the EAT memory 10.

In the deactivation state, GWL 24 _(i) is deselected because one or more of the address inputs A ₁ -A _n applied to the input of the OR gate decoder logic 40 _(i) is high. do. As a result, the output of the OR decoder logic circuit 40 _(i) is high and the transistor Q30 is 0N. Therefore, the differential current I35 is adjusted through Q30 in the differential configuration, so that node A is pulled down. Since node A is low, Q52 and Q54 of pull-up section 50 are not driven and output node E is low and GWL 24 _(i ) is unselected. Furthermore, node C remains low because it is coupled to node E through resistor R78 of control feedback path 79. As a result, transistors Q72 and Q74 are not activated.

In the inactive state, the GWL driver 22 consumes minimal power. For each driver circuit 22, Q52 and Q54 of the pull-up section 50 and Q72 and Q74 of the active pull-down section 70 show that all GWL drivers 22 _(1-g ) are approximations of the current source I29. Is enough to consume the same share.

In the driving state, the address inputs A ₁ -A _n for a particular GWL 24 _(i) are all low and the output of the 0R decoder logic 40 _(i) is converted to low. As a result, Q30 is 0FF and the differential current (I35) is adjusted through Q34 in differential configuration. Node C is thus pulled down and node A is pulled up by resistor R42. In the pull-up section 50 of the GWL driver circuit 22, Q52 and Q54 are surely turned on, and pull up the node D and the output node E, respectively. GWL 24 _(i) is pulled up and thus selected. The majority of the current used to drive the selected row 24 _(i) is derived from V _CC .

In the driven state, the control feedback path 79 keeps the active pull down 70 inactive. This is due to the current flow from the differential current source I35 through Q34, node C, R78 and finally the output node E, which implies the resistance R78 between the output node E and the node C. It is performed by the voltage drop. Thus, the potential at node C is in a low state, and pull-down transistors Q72 and Q74 are inactive.

In a preferred embodiment, resistor R78 is large enough to keep the potential at node C below the turn-on thresholds of Q72 and Q74. Otherwise, node C will be pulled up, and Q72 and Q74 will be 0N to reverse the pullup effect of node E by pullup section 50.

In the recovery state, the activating 0R decoder logic 40 _(i) transitions to a high state after an appropriate read time has elapsed. Accordingly, differential current I35 is adjusted via Q30, node A is pulled down, and Q52 and Q54 of pullup section 50 are deactivated. However, the output node E remains high until its potential is discharged. As a result, the node C quickly rises to the potential of the node E because the differential current I35 no longer flows through the resistor R78 after Q34 is switched off. Thus, the potential at node C of the new inactive GWL driver 22 _(i) is higher than that of all other inactive GWL drivers 22. This very surely zeroes the transistors Q72 and Q74 of the inactive GWL driver 22 _(i) , with most of the current from the shared current source I29 flowing through these two transistors. Accordingly, the output node E is quickly pulled down, reducing the recovery time of the GWL driver 22 _(i) .

The GWL decoder 22 _(i) automatically returns to the inactive state when the potential at the output node E is discharged through the active pull-down path 79. In the recovery state, the node C following the potential of the node E is also discharged. This consequently turns off Q72 and Q74 so that the active pulldown section 70 automatically terminates and the GWL driver 22 _(i) returns to the inactive state.

GWL driver 22 _(i) is deactivated by the write disable signal coupled to the base of Q32 in differential configuration. During the write operation, the write disable signal is driven high, turning Q32 on. As a result, node A is pulled down and GWL driver 22 _(i ) is deactivated.

Diode D58 reduces ringing in pull-up section 50 when GWL driver 22 _(i) is activated. Diode D76 and resistor R80 reduce ringing in active pull-down portion 70 after GWL driver 22 _(i) is in a recovery state. This effect is described in some of the above-mentioned continuing applications entitled "Word Line Decoder / Driver Circuit and Method".

According to the simplified embodiment of the present invention, a number of components of the pull-up section 50 and the active pull-down section 70 can be removed. For example, transistors Q52 and Q56, diode D58, and resistor R60 are removed from pull-up 50, and the base of Q54 is coupled directly to node A. Similarly, in active pull down 70, transistor Q72, diode D76 and resistor R80 are also removed, and node C is coupled to the base of Q74. The operation of this embodiment is essentially the same as described above, but provides the effect of fewer components and less die space.

Although the present invention has been described in connection with the embodiments described in the accompanying description, many other alternatives, embodiments, and modifications will be apparent to those skilled in the art. For example, decoder 20 and driver circuit 22 may be used in any application where one of several items needs to be selected and driven. The specification is merely exemplary, and the true scope and spirit of the invention is indicated by the following claims.

1 is a logic block diagram of an embedded access tree (EAT) memory array of the present invention,

2 is a circuit schematic diagram of a wordline driver circuit according to the present invention.

Claims (20)

An output node coupled to the word line; A pull-up unit driving an output node and a word line; An active pull-down unit which pulls down the output node and the word line; And It includes a feedback control element coupled between the output node and the active pulldown section that controls the activation of the active pulldown section of the wordline driver circuit, and share a single common pulldown current source with all other wordline driver circuits in the semiconductor memory. A word line driver circuit. 2. The circuit of claim 1, wherein the feedback control element consists of a voltage drop element between the output node and the active pull down portion. 3. The circuit of claim 2 wherein the voltage drop element is comprised of a resistor. The circuit according to claim 1, wherein the pull-up portion is composed of a pull-up transistor. The method of claim 1. And the pull-up part comprises slave transistors. The circuit of claim 1, wherein the active pull-down portion is composed of a pull-down transistor. 12. The circuit of claim 1 wherein the active pulldown section is comprised of slave transistors. 2. The circuit of claim 1, wherein the feedback control element controls the active pulldown in response to the state of the driver circuit. 10. The circuit of claim 8, wherein the feedback control element deactivates the active pull down portion when the driver is in an inactive state. 9. The circuit of claim 8, wherein the feedback control element deactivates the active pull-down when the driver is in an active state. 9. The circuit of claim 8, wherein the feedback control element activates an active pull down portion when the driver is in a recovery state. 12. The circuit of claim 11, wherein the feedback control element terminates the activation of the pull-down section after the recovery state. 2. The circuit of claim 1 wherein the pull up portion and the active pull down portion match. A method of operating a wordline driver circuit operable in an inactive state, a driven state, and an active pull-down state, the method comprising: Coupling word lines to output nodes: Providing a pull-up circuit coupled to the output node; Providing a pull-down circuit coupled to the output node; Providing a control feedback path from an output node to a pull-down circuit; And Controlling activation of the pull-down circuit via the control feedback path based on the state of the driver circuit. 15. The method of claim 14, wherein the controlling step is further characterized by inactivating the pull-down circuit while the driver circuit is in a driving state. 15. The method of claim 14, wherein providing the control feedback path is further configured to increase the potential difference between the output node and the pull-down circuit that is applied to the control feedback path in a driven state such that the pull-down circuit is not activated. Way. 5. The method of claim 1 4, further comprising activating a pull-down circuit after the drive state. 18. The method of claim 17, wherein activating the pull down circuit further comprises pulling up a potential in the pull down circuit via a control feedback path. 19. The method of claim 18, wherein the pulldown circuit is automatically terminated after being activated. A plurality of word lines; A plurality of driver circuits each coupled with a plurality of word lines; And A single common current source shared between the plurality of drive ratio circuits, Each driver circuit An output node coupled to its respective word line; A pull-up unit driving an output node and a word line; An active pull-down unit which pulls down the output node and the word line; And And a feedback control element coupled between the output node and the active pull-down section for controlling the activation of the active pull-down section of the wordline driver circuit.