KR100342434B1 - A fast convolution approximation scheme for estimating end-to-end delay - Google Patents

Abstract

The present invention relates to a fast convergence approximation system and a method thereof for short-to-one-stage delay prediction, a method for obtaining a delay distribution at each node in a distributed manner and obtaining a short- .

A probability distribution storage device # 1 storing a delay distribution of traffic passing through the output port, a probability distribution storage device # 2 receiving delay information from an upstream or downstream node, and a probability distribution storing a result of the fast convolution in the controller A minimum value calculation block for calculating the greatest common divisor of DELTA ₂ stored in the DELTA 2 and DELTA 2 blocks calculated in the DELTA 1 calculation block and a minimum value calculation block for calculating the compressed delay distribution P _X2 (i), P _Y2 (i) And a probability distribution storage device # 3 that receives the convolution result and Δ 'of the convolution calculator and restores the convolution result to the original scale according to equations (4) and (5) and stores the convolution result.

The present invention has the effect of enabling estimation of a short-to-end delay in a short time by convoluting a delay distribution across several nodes at high speed.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a fast convolution approximation system for short-to-

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a fast convolution approximation method for end-to-end delay prediction, and more particularly, to a fast convolution approximation method for end-to- To a fast convolution approximation system and method for enabling estimation and compressing and delivering a delay distribution.

QoS requirements of users in ATM networks include cell loss rate, cell delay, and cell delay variation. ATM networks must accommodate both real-time traffic and non-real-time traffic. In real-time traffic, cell delay (CTD) and cell delay variation (CDV) are important quality factors. The network shall be able to know whether the cell delay variation required in the call admission control process during the call establishment is satisfied or not. Therefore, the network needs to estimate acceptable end-to-end delay variation using cell delay and delay variation information at each switch or node. End-to-end QoS prediction can be used for QoS and routing of QoS to select the best path to the destination as well as signal and call admission control.

The conventional method of estimating the end-to-end delay is proposed in the following five methods.

The first method estimates the end-to-end CDV as the sum of the CDVs at each node from the source to the destination.

The second method assumes that the CDV at each node is a constant multiple of the standard deviation of the CTD and that the constant is the same for all nodes. Under this assumption, the end-to-end CDV becomes equal to the sum of the squares of the CDVs at each node plus SQUARE ROOT.

The third method is to use the mean and variance of delay at each node and to use CDV. Regardless of the distribution of individual random variables, we use the central limit theorem that the sum of the random variables becomes closer to the normal distribution as the number of random variables increases.

The fourth method uses the CHERNOFF BOUND, assuming that the queuing delay on each switch follows the GAMMA distribution.

Fifth, the network is a method of using an operation maintenance (OAM) cell. Using the OAM cell, it is possible to obtain the end-to-end delay distribution without having to obtain the delay distribution at each node.

However, the above-described conventional methods cause the following problems.

The CDV obtained by the first method may not be the UPPER BOUND for the actual short-to-short CDV.

In the second method, the constants multiplied by the standard deviation at each node may not be the same.

In the case of the third method, there is a burden of calculating CDV at each node. In order to calculate the (1-α) - QUANTILE of the cell delay time distribution when the value of α is very small, This means that the calculation time is lengthened.

The fourth method is known to have a broadband dependency in the case of compressed video traffic and the GAMMA distribution assumption generally does not hold because broadband dependent traffic has a queue length distribution of HYPERBOLIC TAIL.

In the fifth method, a short-to-short delay distribution can be obtained without obtaining a delay distribution at each node. However, since there is a limitation on the frequency with which OAM cells are generated, it is very long OAM cells are generated on a connection-by-connection basis. Since the number of connections established in the ATM network is very large, OAM cells cause signal traffic to increase and load on the network can be increased.

In order to solve the above problems, the present invention has an object to obtain a delay distribution at each node in a dispersed manner and obtain a short-to-end delay using the information.

According to another aspect of the present invention, there is provided a control system for receiving a delay distribution from a neighboring node to perform a fast convolution and transmitting the result to another node to calculate a short-to- The routing information is recorded to determine to which delay distribution processor the delay distribution is sent from the upstream node and to which upstream node the calculation result of the delay distribution processor is sent when the delay distribution comes from the downstream node, A routing information manager for receiving a delay distribution for each output port from the switch and sending the delay distribution to the corresponding delay distribution processor; a delay distribution for receiving a delay distribution in a directly connected switch and receiving a delay distribution in a neighboring node and performing convolution at a high speed And a delay distribution from the upstream node to the corresponding delay distribution processor Jugeona, the calculation result of the delay distribution information processor delays the switching block to forward to the upstream node; characterized by being a.

The present invention also provides a delay distribution processor for performing a fast convolution approximation function on two delay distributions, comprising: storing a delay distribution of a cell passing through a corresponding output port in a probability distribution storage device # 1; Receiving the delay information from the upstream node or the downstream node in the distribution storage device # 2; and the probability distribution compressor # 2, when receiving delay information from the downstream node, connecting to the upstream node, or receiving the delay information from the upstream node, A step of transmitting the delay distribution data compression rate at the neighbor node in the probability distribution storage device # 2 to the delta 2 block; and a step of transmitting the compressed delay distribution calculated by the following Equations 2 and 6 Calculating a data compression rate in a delta 1 calculation block using the delay distribution input to the probability distribution storage # 1; Generating and storing a compressed delay distribution at a compression rate computed in the delta 1 block in the compressor # 1; calculating a compression ratio calculated in the delta 1 block and a maximum common divisor of the compression ratio stored in the delta 2 block in the minimum value calculation block A convolution calculator for convolution of the compressed delay distribution in the convolutional calculator, and a probability distribution storage unit # 3 for restoring the original scale according to the result of the convolution calculator and the following equations 4 and 5: Calculating a data compression ratio for a delay distribution obtained as a result of convolution in a delta 3 block to transfer the convolution result back to another neighbor node; 2, compressing the delay distribution using Equation (2) and Equation (6) using the data compression rate received from the delta 3 in step It characterized in that it comprises a; transferring the compressed cumulative delay distribution to the next adjacent node.

The present invention also provides a delay distribution processor for performing a function of transferring a delay distribution of a node itself and a delay distribution of neighboring nodes, wherein a cell delay distribution occurring at a corresponding output port of a directly connected switch is stored in a probability distribution storage device # 1 ; And

Calculating a data compression rate in a delta calculation block for a delay distribution stored in a probability distribution storage device # 1; Storing a delay distribution and a data compression rate obtained by compressing the delay distribution stored in the probability distribution storage # 1 in the distribution compressor # 1 to the data compression ratio calculated in the delta calculation block using Equations 2 and 6 and the data compression ratio in the scheduler block; Determining a transmission order of the branch delay distribution, and transmitting the delay distribution according to the determined transmission order.

The present invention also provides a delay distribution processor for performing a fast convolution approximation function by receiving a delay distribution at all nodes, wherein a delay distribution occurring at a corresponding output port of a directly connected switch is stored in a probability distribution storage device # 1 ; A step of determining a data compression rate in a delta 1 calculation block; and a step of compressing the delay delays stored in the probability distribution storage # 1 in the probability distribution compressor # 1 at a rate of delta and sending the compressed delay distribution and the compression rate to the selector A step of selecting a result of the probability distribution compressor # 1 in the selector; a step of storing a delay distribution generated in the final node in the probability distribution storage device # 2; , The compression rate for the delay distribution is stored in the delta 2 block, the probability distribution storage device # 3 Storing a data compression ratio for the distribution in a delta 3 block; selecting a minimum of two data compression ratios for two delay distributions fast-convoluted in a minimum value calculation block; And transmitting the result of the convolution operation to the probability distribution storage device # 4; and a step of performing a convolution operation on the delay distribution at the node closest to the delay distribution at the last node in the probability distribution storage # Storing the result and a minimum value of the data compression ratio; feeding back the result to a selector; and after the feed-back step, the convolution is finished from the second time in the selector Selecting a probability distribution storage device # 4 until a predetermined time has elapsed, storing accumulated convolution results in a probability distribution storage device # 2, The delay distribution for the free node is transmitted from the probability distribution queue to the probability distribution storage device # 3 and stored; and the delay distribution accumulated for the probability distribution storage device # 2 and the next node stored in the probability distribution storage # And the final result is stored in the probability distribution storage # 4.

1 is a block diagram showing the concept of an ATM node of the present invention.

2 is a control block for calculating a convolution for transmitting and receiving delay information to and from a neighboring node.

3 is an explanatory diagram of the principle of an approximate algorithm of fast convolution.

4 is a flowchart showing an algorithm for calculating a data compression ratio required for approximate calculation of a fast convolution.

5 is a block diagram of a delay distribution processor that performs a fast convolution approximation function for two delay distributions.

6 is a block diagram of a delay distribution processor that performs the function of transferring a delay distribution of its own node and a delay distribution of its neighboring nodes.

7 is a block diagram of a delay distribution processor that performs a fast convolution approximation function by receiving a delay distribution at all nodes.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram showing the concept of an ATM node of the present invention. As shown, a plurality of switch nodes are connected, and one node is a control block 102 for exchanging information about delay between a switch 101 exchanging data traffic and a neighboring node, and calculating an accumulated delay consist of.

Assuming that data flows from left to right, node A on the left in FIG. 1 becomes an UPSTREAM node, and nodes B and C on the right side become a DOWNSTREAM node. Data traffic between neighboring nodes is communicated through the data link 104, which represents a conceptual connection, may be physically included in the data link, or may be separate and separate from the data link. In the case of being physically included in the data link, the control message link 105 can be logically formed by dividing the data cell and the control cell into only the control cell and sending it to the control block 102.

As a first step to obtain the short-to-short delay distribution, the delay distribution should be obtained at each node. There are two methods for obtaining the delay distribution at each node.

The first method is to generate a test cell and pass the switch to measure the total time taken. The delay at one node can be known by writing the input time to the test cell's time stamp immediately before or after inputting the test cell to the switch or by subtracting the input time written in the time stamp at the moment of leaving the switch .

The second method is to observe the buffer in a way that can be applied to a shared buffered switch that separates and manages the output buffered switch or the output port. Let N 'be the number of cells in the buffer observed at the time of arrival of each cell, and N', N be the number of cells in the buffer observed at any given time. Let W be the time The following equation (1) holds.

Where K is the maximum number of cells that may be present in the buffer.

Using Equation (1), it is possible to observe the buffer at the moment when each cell arrives or observe the buffer at every cell time, thereby knowing the distribution of the time of waiting until the cell receives the service in the buffer. If the service time is constant If the link rate is constant, the distribution of the time that the cell stays in the switching system can be obtained by horizontally moving W by the service time.

The distribution of the delay can be obtained at the switch 101 of each node by the above-described method. To accumulate the delay information for each node to obtain the short-to-short delay distribution, each node simply sends the delay information generated at its own node and the delay information received from the neighbor node to the upstream or downstream node, There may be a method of collecting a node or a destination node and calculating the result including delay information at its own node instead of just passing the delay information at another node in another way ② There can be.

In case (1), when the controller 102 of the intermediate node receives the delay distribution from the directly connected switch 101, the delay information is compressed and sent to the call originating node or the destination. When the delay information is received from the upstream node or the downstream node It simply acts in the opposite direction. In the last node where all delay information is gathered, it is necessary to calculate the end-to-end delay using the delay information and the delay information received from the own node.

The control block 102 of each node receives the delay information from the directly connected switch and receives the cumulative delay distribution from the call originating node to the upstream node or from the destination to the downstream node from the control block of the upstream node or the downstream node, And transmits the delay distribution accumulated up to itself in the opposite direction in which the delay information is received.

If the number of nodes from the originating node to the destination node is Z, the number of times of transmitting the delay information per node is proportional to the square of Z, In the case of (2), since each node performs high-speed convolution, the number of operations required is slightly larger, but the number of times of transmitting the delay information per node is proportional to Z. Therefore, although the time required to obtain the short-to-end delayed prediction value may be shorter than that in the prior art, the information is continuously compressed after performing the fast convolution at each node, More accurate end-to-end delay prediction may be possible.

When call admission control is performed, it is necessary to judge whether or not a connection is established by determining a network situation at a node corresponding to a gateway which enters a network before sending a traffic from the call originating node to the network. Therefore, End-to-end delay information in a node having an admission control function. In this case, in this case, each node transmits both the delay information generated at its own node and the delay information received from the downstream node to the upstream node, or adds the delay information to the upstream node after receiving accumulated delay information from the downstream node, (2) is preferable.

2 shows a control block for calculating a convolution for transmitting and receiving delay information to and from a neighboring node. The function of the control block 102 is shown in more detail as shown.

In the case of a node at the edge of the network, the call admission control block 204 performs the call admission control function. The routing information manager 203 manages routing information for all connections going through its own node. In the call setup process, when the call admission control block 204 permits the call connection, the routing information for the new connection is added to the routing information manager 203. The function of the delay distribution processor 205 depends on the method of accumulating the delay information at each node.

In the case of using the above method (1), the delay distribution processor 205 allocates one to each output port and receives and stores the delay distribution of the cell passing through the corresponding output port. The delay information for each output port received from the switch 201 is transmitted to the delay distribution processor 205 via the routing information manager 203. [ When the delay information is collected at the call origination node, the delay distribution processor also stores the delay information from the downstream node to determine which delay information, which is received from the directly connected switch and the delay information received from the downstream node, In order, upstream of the delay information switching block 206. In this case, the port number at which each delay information exits is determined by the routing information manager 203.

When the delay information is collected at the destination node, the delay information from the upstream is transmitted to the delay distribution processor 205 in the direction of the corresponding downstream node through the delay information switching block 206. The delay distribution processor 205 determines which one of the delay information received from the directly connected switch and the delay information received from the upstream node is to be transmitted first, and immediately transmits the delay information to the downstream node.

In the case of using the delay information accumulation method in the above (2), the delay distribution processor 205 allocates one for each output port, stores the delay distribution of the cell passing through the corresponding output port, and receives the delay of another node to calculate a fast convolution approximation do.

When the delay distribution processor 205 receives the accumulated delay distribution at the downstream node and performs the fast convolution, the routing information manager 203 stores the calculation result, and the routing information manager 203 searches for the corresponding upstream node, The calculation result is transferred to the upstream node via the delay information switching block 206. [ When the delay distribution processor 205 receives the accumulated delay distribution at the upstream node and performs fast convolution, the delay distribution from the upstream node is transmitted to the corresponding delay distribution processor 205 through the delay information switching block 206, The delay distribution processor 205 receives the delay distribution at its own node and the delay distribution at the upstream node, and then performs fast convolution and sends the result to the downstream node.

Figure 3 shows the principle of an approximation algorithm for fast convolution. X is delay in the self-node, Y is Speaking of delay in the neighbor nodes, the random variable X ₂ and Y ₂ of the probability mass function (pmf) (303,304) is the probability mass of the random variables X and Y, as illustrated (2) and (3) from the functions (301, 302).

FIG. 3 deals with cases where the values of? And? ₂ are both 2.

In FIG. 3, it can be easily predicted that, when the pmf (303,304) of X ₂ and Y ₂ is convoluted, the resulting distribution function will be zero. When Δ and Δ ₂ are equal to each other, as shown in the following equations (4) and (5), if the case where 0 is exited is subtracted from the multiplication calculation, the number of times of multiplication can be reduced and the speed can be increased.

In the above, P_ {X_2 ^ '} (i) and P_ {Y_2 ^'} (i) are defined as follows.

This result implies that the convolution of pmf of X ₂ and pmf of Y ₂ can be calculated by convolving P_ {X_2 ^ '} (i) and P_ {Y_2 ^'} (i) do. Let X X and Y Y be the maximum values of D _X and D _Y , respectively. The number of probability values constituting pmf P_ {X_2 ^ '} (i) is about 1 / Δ smaller than P _X (i). Therefore, when the pmf of X2 and Y2 is convoluted instead of X and Y, the number of times of multiplication is (D _X +1) × (D _Y +1) And the upper limit of the COMPLEMENTARY CUMULATIVE DISTRIBUTION FUNCTION is obtained. When Δ and Δ ₂ are different, let Δ 'denote the greatest common divisor of Δ and Δ ₂ , and multiply the number of multiplications . However, even if Δ and Δ ₂ are large values, the data compression ratio Δ is always taken as a power of 2 because there is no gain in terms of the convolution speed.

As described above, by introducing the data compression ratios Δ and Δ ₂ , it is possible to reduce the number of times of multiplication compared with the case where the conventional convolution is used. In addition, using the data compression rate can reduce the amount of data to be transferred between adjacent nodes to estimate the short-to-one delay. In this case, if Y is the delay to the neighboring node, and D Y is the maximum value of _Y , if the data compression rate for pmf of Y is Δ _2, the probability distribution The number of .

If Δ _{2 is set} to a constant value, the number of probability values transmitted between neighboring nodes increases as the maximum delay increases. This is not preferable because it means that the short-to-end delay calculation is influenced by the degree of delay occurring at each node.

In order to solve the above problem, FIG. 4 proposes an algorithm for determining the data compression rate based on the delay at each node. 4 is a flowchart showing an algorithm for calculating a data compression ratio required for approximate calculation of a fast convolution. As shown, it is assumed that the number of probability values transmitted between nodes is m, and m is also a power of 2. (401) allocates and initializes a memory in an array a [i] storing all the variables and delay distributions used in the algorithm. The delay distribution is stored in the array a [i] (402). Where i represents the delay in cell time units, and a [i] represents the probability that the delay is i cell time. Given the delay distribution, the next step is to find the maximum delay and store the value in D _max (403). Since the data compression rate? Is always taken as a power of 2 (404,405), < / RTI > (406). When the data is compressed by the algorithms of Equations (2) and (6), the number of probability values to be transmitted to neighboring nodes does not exceed m.

Figure 5 is a block diagram of a delay distribution processor that performs a fast convolution approximation function for two delay distributions. As shown in the figure, the detailed structure of the delay distribution processor 205 for performing the fast convolution approximation calculation when the delay accumulation method (2) is used is shown.

The probability distribution storage # 1 (502) stores the delay distribution of the cell passing through the corresponding output port. At this time, the delay is measured in cell time units, and the occurrence rate is stored for each delay value.

The probability distribution storage device # 2 (503) receives delay information from the upstream node or the downstream node. The result of the fast convolution in the controller is stored in the probability distribution compressor # 2 (511). When the probability distribution storage device # 2 503 receives the delay information from the upstream node, the probability distribution compressor # 2 511 is connected to the downstream node, and when the probability distribution storage device # 2 503 receives the delay information from the downstream node The probability distribution compressor # 2 (511) is connected to the upstream node.

The probability distribution storage device # 2 503 first receives the delay distribution data compression rate? ₂ at the neighbor node and delivers it to the delta2 block 505 and then calculates the compressed delay distribution P_ {Y_2 ^ '} (i).

The probability distribution storage # 1 (502) accepts the distribution of the delay experienced by the cell going to the corresponding output port of its switch. The DELTA 1 calculation block 504 calculates the data compression rate Δ using the algorithm of FIG. 4 using the delay distribution received by the probability distribution storage device # 1 (502). If Δ increases, there is a disadvantage that the speed is faster but the accuracy is lowered. In the case where the weight is given to the accuracy, the DELTA 1 calculation block 504 may always output Δ by fixing the Δ in place of the algorithm of FIG.

The probability distribution compressor # 1 generates and stores a compressed delay distribution P_ {X_2 ^ '} (i) using the expressions 2 and 6 together with the Δ calculated in the DELTA 1 calculation block 504.

The minimum value calculation block 507 calculates the greatest common divisor of DELTA ₂ stored in DELTA 2 and DELTA 2 block 505 calculated in DELTA 1 calculation block 504. If both Δ and Δ ₂ are powers of two, since the greatest common divisor of the two numbers is the same as the smallest of the two numbers, the minimum value calculation block 507 functions to select the minimum value Δ 'between Δ and Δ ₂ .

Convolution calculator 508 convolves the compressed delay distribution P_ {X_2 ^ '} (i), P_ {Y_2 ^'} (i). The probability distribution storage unit # 3 509 receives the convolution result and Δ 'of the convolution calculator 508, restores the original scale according to Equations 4 and 5, and stores the convolution result. For fast-to-short delay computation, the convolution result must be passed back to another neighbor node. In order to reduce the amount of data to be delivered before delivering the result distribution, the DELTA 3 calculation block 510 calculates the data compression rate Δ ₃ for the delay distribution obtained as a result of the convolution.

The probability distribution compressor # 2 511 compresses the delay distribution using the data compression rate? ₃ received from the DELTA 3 calculation block 510 using the algorithms of Equations 2 and 6, and then compresses the data compression rate and the compressed cumulative delay distribution to another neighboring node (514).

6 illustrates a delay distribution processor 205 that performs a function of transmitting a delay distribution of its own node and a delay distribution of neighboring nodes in nodes other than the end node where all the delay distributions are collected when the delay accumulation method of (1) . 5, the cell delay distribution generated at the corresponding output port of the directly connected switch is stored in the probability distribution storage # 1 602 and the delay information received from the upstream node or the downstream node Is stored in the probability distribution storage # 2 (604). In the delay distribution processor 501 of FIG. 2, the data compression rate among the delay information received from the upstream node or the downstream node is separated and stored in the DELTA 2 block 505. However, in the case of the delay distribution processor 601, The data compression ratio is stored in the probability distribution storage # 2 (604) together with the probability values of the delay distribution without separating the data compression rate. The DELTA calculation block 603 calculates the data compression ratio Δ according to the algorithm of FIG. 4 for the delay distribution stored in the probability distribution storage device # 1 602, and the probability distribution compressor # 1 605 calculates the probability distribution storage # The delay distribution stored in the delay storage 602 is compressed according to the algorithm of Equations (2) and (6) at a rate of? To store the compressed delay distribution and?.

2) -type delay distribution processor 501 receives two delay distributions, performs a fast convolution, compresses and transmits the result, and thus the calculation result is transmitted only once. However, the delay distribution processor 601 of the (1) Since we distribute the distributions separately, it is necessary to determine the sequence of the distribution of the two delay distributions first. The scheduler block 606 performs such a role. As the scheduling algorithm, it is possible to use a FIFO (FIRST-IN FIRST-OUT) scheme in which an early arrival delay distribution is transmitted first. When two delay distributions arrive at the same time, the amount of information transmitted from the neighboring nodes is generally larger than the delay information generated by the directly connected node. Therefore, the probability distribution storage device # 2 604 is given a high priority By using the method of transferring the data with the rank, it is possible to minimize the amount of buffer required for the probability distribution storage # 2 (604). On the other hand, if it is desired to reduce the time required to start the high-speed convolution before the delay distribution of each node arrives at the final node where all the delay information is gathered, It is preferable to give the distributed compressor # 1 605 a high priority and delay information at a node close to the node performing the convolution.

The intermediate node simply transfers the delay distribution from its own node and the delay distribution received from the neighbor node to the originating node or destination node. However, in the delay distribution processor of the last node, The structure is more complicated than the intermediate node because it has to be looped.

FIG. 7 is a block diagram of a delay distribution processor 205 that performs a fast convolution approximation function by receiving a delay distribution at all nodes in an end node where delay distribution is collected when the delay accumulation method of (1) is used.

The delay distribution occurring at the corresponding output port of the directly connected switch is stored in the probability distribution storage # 1 of the delay distribution processor 701. The DELTA 1 calculation block 703 determines the data compression rate Δ according to the algorithm of FIG. 4, and the probability distribution compressor # 1 705 compresses the delay distribution stored in the probability distribution storage # 1 702 at a rate of Δ The compressed delay distribution and the compression ratio [Delta] are sent to a selector 706.

Since the selector selects the result of the probability distribution compressor # 1 at the beginning of the fast convolution calculation, the probability distribution store # 2 stores the delay distribution generated at the last node, and the data compression rate for the delay distribution is stored in the DELTA 2 block 708 < / RTI > The probability distribution storage device # 3 (709) receives the delay distribution generated at the node closest to the final node for the first time, and stores the data compression rate for the distribution in the DELTA 3 block (710). The minimum value calculation block 711 then selects the smallest of the two data compression ratios for the two delay distributions that are fast convoluted and the convolution calculator block 712 performs a convolution operation on the two compressed delay distributions, To the probability distribution storage # 4 (713). Accordingly, the probability distribution storage device # 4 713 stores the result of the fast convolution of the delay distribution at the node closest to the delay distribution at the last node and the minimum value of the data compression rate. When the result is fed back to the selector 706, the selector selects the probability distribution storage # 4 (713) from the second to the end of the convolution. Thus, the accumulated convolution result is stored in the probability distribution storage # 4 707 and the delay distribution for the next closest node is transferred from the probability distribution queue- (QUEUE) 704 to the probability distribution storage # 3 and stored . By repeating the process of performing the fast convolution on the cumulative delay distribution stored in the probability distribution storage device # 2 707 and the delay distribution of the next closest node stored in the probability distribution storage device # 3 709, - The near-end delay is approximately calculated. This result is finally stored in the probability distribution storage # 4 (713).

The present invention has the effect of enabling estimation of a short-to-end delay in a short time by convoluting a delay distribution across several nodes at high speed.

In addition, it is possible to reduce the load caused by the control information by compressing and transmitting the delay distribution instead of transmitting all of the delay distribution, and shortening the estimation time of the short-to-end delay.

Further, the present invention can improve call admission control by knowing the current network situation by using the estimation information of the short-to-end delay, and can provide useful information even in the case of QoS routing.

Claims (14)

A system for obtaining a short-to-end delay using delay information at each unit node in an ATM network, Wherein each unit node comprises a switch for exchanging data traffic, And a control block connected to the switch for exchanging information on delay between neighboring nodes and for calculating an accumulated delay. The method according to claim 1, Wherein each of the unit nodes is divided into an end node where delay information is collected and an intermediate node other than the end node, A data link for communicating data traffic between neighboring nodes, Further comprising a control message link that conveys a control message to the fast convergence approximation system. The method of claim 2, Wherein the control message link can be included in the data link and can be independently configured separate from the data link. ≪ Desc / Clms Page number 19 > The method of claim 3, Wherein when the control message link is included in the data link, only the control cell is transmitted to the control block by distinguishing between the data cell and the control cell, and the fast convolution approximation system for the short-to-single-stage delay prediction. 1. A system having a plurality of unit nodes including a switch for exchanging data traffic in an ATM network and a control block connected to the switch for exchanging delay information between adjacent nodes, The control block includes a routing information manager for receiving and outputting a delay distribution for each output port in the directly connected switch, A plurality of delay distribution processors receiving a delay distribution in a switch directly connected through the routing information manager and performing convolution at a high speed in a neighboring node, And a delay information switching block for sending the delay distribution from the upstream node to the corresponding delay distribution processor or for transferring the calculation result of the delay distribution processor to the corresponding upstream node and for calculating the short- Wherein the neighboring node receives the delay distribution and performs fast convolution, and transmits the result to another node. The fast convergence approximation system for short-to-one-way delay prediction. 1. A system having a plurality of unit nodes including a switch for exchanging data traffic in an ATM network and a control block connected to the switch for exchanging delay information between adjacent nodes, The control block includes: A routing information manager for receiving and outputting a delay distribution for each output port in the directly connected switch, Receives the delay distribution from the switch directly connected through the routing information manager, receives the delay distribution from neighboring nodes, and delivers the delay distribution to the call originating node or the destination node, or performs high speed convolution at the call originating node or the destination node A plurality of delay distribution processors, And a delay information switching block for sending the delay distribution from the upstream node to the corresponding delay distribution processor or for transferring the calculation result of the delay distribution processor to the corresponding upstream node, As a result of this, it is necessary to carry out high-speed convolution in a call origination node or a destination node in which all delay information is gathered as the above element, and to perform fast convolution on all delay information received by itself, To-node delay of the fast convergence approximation system. The method according to claim 5 or 6, The routing information manager records the routing information when a call is established and determines to which delay distributor the delay distribution is sent from the upstream node and determines to which upstream node the delay distribution calculation result is sent from the downstream node Wherein the fast convergence approximation system for short-to-one-way delay prediction determines a fast convergence approximation system. The method of claim 5, Wherein the delay distribution processor comprises: a delay distribution compression ratio DELTA calculation block; A minimum value calculation block for calculating the greatest common divisor of data compression ratios for two delay distributions as a minimum value of two, A probability distribution compressor # 1 for compressing a delay distribution in a directly connected switch according to an algorithm of the following equation, A convolution calculator for convoluting the two delay distributions compressed by equations (2) and (6) A probability distribution storage # 3 for restoring and storing the convolution calculation result distribution back to the original scale, And a convolution of two delay distributions independent of each other, which is composed of a probability distribution compressor # 2 which compresses again the convolution result with the algorithm of Equations (2) and (6) before transferring the convolution result to another node Speed convolution approximation system for short-to-one-delay prediction. The method of claim 8, Wherein the delay distribution processor determines a data compression rate such that the amount of compressed information is constant based on the maximum value of the delay in order to perform fast convolution computation or to reduce the amount of information conveyed between nodes. A Fast Convolution Approximation System for Delay Prediction. The method of claim 6, Wherein the delay distribution processor, when belonging to a node other than the last node where all delay information is gathered, A DELTA calculation block, Probability distribution compressor # 1, When the delay information at the own node and the delay information at the neighboring node arrive, the first arriving information is transmitted with higher priority, the delay information at the own node is given with higher priority, or the neighboring nodes And a scheduler for delivering priority information to the delay information, The delay information generated at the corresponding output port of the directly connected switch is temporarily compressed and the delay information generated at the own node and the delay information received from the neighboring node are transmitted to the call originating node or the destination node according to the arrival order A fast convolution approximation system for short - to - delay prediction. The method of claim 6, Wherein the delay distribution processor, when belonging to an end node where all delay information is gathered, A DELTA calculation block, A probability distribution QUEUE between the call origination node and the destination node storing the delay distribution of all the nodes except for the call origination node in order from the delay distribution of the near node, A selector for selecting one of a delay distribution and an accumulated delay distribution at its own node; A minimum value calculation block for selecting a minimum value among the data compression rate of the accumulated delay distribution and the data compression rate of the delay distribution at the nearest node among the nodes not included in the accumulation, A convolution calculator, Wherein the fast convergence is calculated from the delay distribution of the nearest node in order from the delay distribution at all the nodes going through the call from the call origination node to the destination node. A delay distribution processor for performing a fast convolution approximation function on two delay distributions, Storing a delay distribution of a cell passing through a corresponding output port in probability distribution storage # 1; Receiving delay information from the upstream node or the downstream node in the probability distribution storage device # 2; The probability distribution compressor # 2 is connected to the upstream node when it receives the delay information from the downstream node, or to the downstream node when receiving the delay information from the upstream node. Receiving a delay distribution data compression ratio at a neighboring node in a probability distribution storage device # 2 and transmitting the delay distribution data compression ratio to a delta 2 block; Storing a compressed delay distribution calculated by the following equations (2) and (6); and Calculating a data compression ratio in the delta 1 calculation block using the delay distribution input to the probability distribution storage # 1; Generating and storing a compressed delay distribution at a compression rate calculated in the delta 1 block in the first probability distribution compressor; Calculating a maximum common divisor of the compression ratio computed in the delta 1 block and the compression ratio computed in the delta 2 block in the minimum value calculation block; Convoluting the compressed delay distribution in the convolution calculator; Storing the convolution result in the probability distribution storage unit # 3 by restoring the result of the convolution calculator to the original scale according to the following equations (4) and (5) Calculating a data compression rate of the delay distribution obtained as a result of the convolution in the delta 3 block to transfer the convolution result to another neighbor node again; Compressing the delay distribution using Equation (2) and Equation (6) using the data compression rate received from the delta 3 in the second probability distribution compressor; And transmitting the data compression rate and the compressed cumulative delay distribution to a next neighbor node. ≪ Desc / Clms Page number 19 > A delay distribution processor for performing a function of transmitting a delay distribution of a node itself and a delay distribution of a neighboring node, A cell delay distribution occurring at a corresponding output port of a directly connected switch is stored in probability distribution storage # 1; The delay information transmitted from the upstream node or the downstream node is stored in the probability distribution storage # 2; Calculating a data compression ratio in the delta calculation block using the delay distribution stored in the probability distribution storage # 1; Storing a delay distribution and a data compression rate obtained by compressing the delay distribution stored in the probability distribution storage # 1 in the probability distribution compressor # 1 by the data compression ratio using Equations 2 and 6; Determining a transmission order of two delay distributions in a scheduler block; And transmitting the delay distribution according to the determined transmission order. The fast convergence approximation method for short-to-high-speed delay prediction according to claim 1, A delay distribution processor for performing a fast convolution approximation function by receiving a delay distribution at all nodes, The delay distribution occurring at the corresponding output port of the directly connected switch is stored in the probability distribution storage # 1; determining a data compression rate in a delta 1 calculation block; Compressing the delay division stored in the probability distribution storage # 1 in the probability distribution compressor # 1 at a rate of delta, sending the compressed delay distribution and the compression rate to the selector, Wherein the high speed convolution calculation is started; Selecting a result of the probability distribution compressor # 1 in the selector; Storing the delay distribution generated in the final node in the probability distribution storage device # 2; A compression rate for the delay distribution is stored in a delta 2 block; Receiving a delay distribution generated at a node closest to the last node in the probability distribution storage device # 3 and storing a data compression rate for the distribution in a delta 3 block; Selecting a minimum value of two data compression ratios for two delay distributions fast-convoluted in a minimum value calculation block; Performing a convolution operation on two delay distributions compressed in the convolution calculator block and transmitting the result to the probability distribution storage # 4; Speed convolution of the delay distribution at the node closest to the delay distribution at the last node in the probability distribution storage device # 4 and storing the result and the minimum value of the data compression rate; Feeding back the results to a selector; Selecting the probability distribution storage device # 4 from the second to the end of the convolution after the feed-back step, Storing the accumulated convolution result in the probability distribution storage # 2; The delay distribution for the nearest node is transmitted from the probability distribution queue to the probability distribution storage # 3 and stored; Repeating the delay distribution accumulated in the probability distribution storage device # 2 and the delay distribution of the next closest node stored in the probability distribution storage device # 3; And storing the final result in the probability distribution storage # 4. The fast convergence approximation method for end-to-end delay prediction,