KR100337036B1 - Semiconductor device of multi-layer interconnection having an improved interlayer insulating film, and process for forming the same - Google Patents

Abstract

In a semiconductor device having a multi-layer interconnection structure having an interlayer insulating HSQ (hydrogen silsesquioxane) film having a low dielectric constant, the surface layer below the HSQ film and in direct contact with the HSQ film is formed of a hydrophobic surface layer. Therefore, when the HSQ film is fired, the low dielectric constant of the HSQ film never rises as a result of no moisture being discharged from the lower surface layer.

Description

TECHNICAL FIELD OF THE INVENTION A semiconductor device having a multi-layered wiring structure having an improved interlayer insulating film and a method for manufacturing the same.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a multilayer wiring structure, and more particularly, to a semiconductor device having a multilayer wiring structure having an improved interlayer insulating film and a manufacturing method thereof.

The operating speed of the semiconductor device decreases as the product of the parasitic capacitance C between the wiring resistance R and the adjacent wiring increases. Here the parasitic capacitance between the wires will be called 'inter-metal capacitance'. As the spacing between adjacent wirings becomes narrower, the intermetallic capacitance C increases in inverse proportion to the spacing between adjacent wirings. Therefore, it is important to reduce the intermetallic capacitance C in order to improve the operating speed of the semiconductor device. From the above point of view, it is widely used to form an interlayer insulating film (low-k material) having a relatively low dielectric constant between adjacent fine wirings. The HSQ (hydrogen silsesquioxane) film can be cited as an example of an interlayer insulating film having a relatively low dielectric constant. Examples of using the HSQ film as a low dielectric constant interlayer insulating film include EP-A2-0790645, EP-A2-0810648, JP-A-10-335458, and June 1, 1998, assigned to the same assignee as the assignee of the present application. The corresponding U.S. patent application Ser. No. 09 / 088,048, filed on May, is incorporated herein by reference.

Hereinafter, a process of forming an interlayer insulating film having a low dielectric constant between adjacent wirings according to the conventional art will be described with reference to FIGS. 3A to 3C.

In Fig. 3A, reference numeral 301 denotes a plasma SiO ₂ film formed as an interlayer insulating film on a semiconductor substrate on which various circuit elements including transistors are formed. A metal film is formed on the plasma SiO 2 film 301 and then patterned by a lithoplast process to form a plurality of metal wires 302 adjacent to each other.

As shown in FIG. 3B, a plasma-enhanced tetraethyloxysilane (PETOS) film is formed on the entire surface as a liner film 303 with a thickness of about 100 nm. Thereafter, as shown in FIG. 3C, an HSQ film 304 is formed on the entire surface with a thickness of about 400 nm to fill the gap between the metal wires 302.

However, in the above-described process, TEOS is represented by Si (CH ₂ H ₅ O) ₄ and the PETEOS film 303 contains moisture therein. Therefore, when the HSQ film 304 is fired, moisture is discharged from the PETEOS film, and as a result, the fired HSQ film becomes a high dielectric film having a dielectric constant of 4 or less.

Accordingly, an object of the present invention is to form a hydrogen silsesquioxane film without increasing the dielectric constant of the hydrogen silsesquioxane film in the step of forming an interlayer insulating film of low dielectric constant between adjacent wirings.

It is still another object of the present invention to provide a semiconductor device having a multi-layered wiring structure including a hydrogen silsesquioxane film for improved interlayer insulation that maintains a low dielectric constant and a method of manufacturing the same.

The above objects are achieved according to the present invention by a semiconductor device of a multi-layered wiring structure having an interlayer insulating film comprising at least a hydrogen silsesquioxane film, wherein the insulating film under the hydrogen silsesquioxane film of the interlayer insulating film is hydrogen silses. It has a hydrophobic surface in direct contact with the quoxane membrane.

In particular, in one embodiment of the semiconductor device according to the present invention, the plasma SiO ₂ film 301 is formed on the semiconductor substrate as an interlayer insulating film, and a plurality of metal wirings are formed on the plasma SiO ₂ film. The hydrophobic liner film is formed to cover the gold wiring and the plasma SiO ₂ film, and the hydrogen silsesquioxane film is laminated on the hydrophobic liner film to fill the gap between the metal wirings. And more preferably is converted into a film with the liner film is formed in a plasma SiO ₂ film is a hydrophobic treatment executed for the plasma SiO ₂ film the plasma SiO ₂ film Si-H bond or Si-CH ₃ bond group of the prime number.

In another preferred embodiment, the plasma SiO ₂ film is formed on the semiconductor substrate as an interlayer insulating film, and a plurality of metallizations are formed on the plasma SiO ₂ film. The hydrophobization treatment is performed to convert the exposed surface of the plasma SiO ₂ film, which is not covered with metallization, to a hydrophobic surface. The hydrogen silsesquioxane film is laminated on the plasma SiO ₂ film to fill the gaps between the metal wires. Similar to the first embodiment described above, the hydrophobic surface of the plasma SiO ₂ film is converted into a surface layer having hydrophobic groups of Si—H bonds or Si—CH ₃ bonds.

In the above-described feature, the hydrophobization treatment is performed on the liner film or the lower insulating film, so that no moisture is generated from the liner film or the lower insulating film when the hydrogen silsesquioxane film is fired, so that the dielectric constant of the hydrogen silsesquioxane film does not increase and thus The intermetal correction capacitance is reduced as compared with the interlayer insulating film formed of the oxide film.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor having a multi-layered wiring structure having an interlayer insulating layer, the method of performing a hydrophobization treatment on at least a portion of the lower insulating film formed on the semiconductor substrate And forming a hydrogen silsesquioxane film as at least a portion of the lower insulating film as an interlayer insulating film.

In particular, the process according to the present invention comprises the steps of forming a plurality of metal wirings on the interlayer insulating film formed on the semiconductor substrate, and forming an insulating liner film on the interlayer insulating film to cover the plurality of metal wirings; Performing a hydrophobization treatment on the insulating liner film so as to convert the insulating liner film into a hydrophobic insulating liner, and forming a hydrogen silsesquioxane film on the hydrophobic insulating liner film to fill gaps between the plurality of metal wirings. It is included.

Further, the process according to the present invention is a process of forming a plurality of metal wirings on an interlayer insulating film formed on the semiconductor substrate, and not covered with a plurality of metal wirings to form a hydrophobic surface layer on the exposed surface of the interlayer insulating film. And performing a hydrophobization treatment on the exposed surface of the interlayer insulating film, and forming a hydrogen silsesquioxane film on the hydrophobic insulating film so as to fill between the plurality of metal wirings.

The above objects, features and advantages of the present invention will become apparent from the following preferred embodiments of the present invention with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a partial sectional view of a semiconductor device showing a manufacturing process of a first embodiment according to the present invention for producing a semiconductor device having a multilayer wiring structure having an improved hydrogen silsesquioxane film for interlayer insulation.

Fig. 2 is a partial sectional view of a semiconductor device showing the manufacturing process of the first embodiment according to the present invention for producing a semiconductor device having a multi-layered wiring structure having an improved hydrogen silsesquioxane film for interlayer insulation.

3 is a partial cross-sectional view of a semiconductor device, showing an example of manufacturing a semiconductor device having a multilayer wiring structure according to the prior art.

4 is a partial cross-sectional view of a semiconductor device having a multilayer wiring structure according to the prior art.

<Brief description of the major symbols in the drawings>

Before explaining a method for manufacturing a semiconductor device having a multilayer wiring structure according to the present invention, a description will be given of a semiconductor device having a multilayer wiring structure to which the present invention can be applied.

Fig. 4 is a partial sectional view of a semiconductor device having a multilayer wiring structure according to the prior art, which is disclosed as the prior art in the aforementioned JP-A-10-335458 and corresponding US patent application Ser. No. 09 / 088,048. The semiconductor device having the multilayer wiring structure shown includes a semiconductor substrate 1 having a field oxide film (element isolation region) 2 formed on the main surface of the semiconductor substrate 1. In one element formation region of the semiconductor substrate 1 partitioned by the field oxide film 2, a diffusion layer 3 is formed and one MOS transistor is formed in the diffusion layer 3.

A gate oxide film 22 is formed on the surface of the diffusion layer 3 and a gate electrode 23 is formed on the gate oxide film 22. A sidewall oxide film 24 is formed on each sidewall of the gate electrode 23. A pair of source / drain regions 21 are formed in the surface region of the diffusion film 3 on the opposite side of the gate electrode 23.

The interlayer insulating film of the zero level is formed so as to cover the gate electrode 23, the main surface of the substrate 1 and the field oxide film 2. A pair of contact holes 5 are formed through the interlayer insulating film 4 so as to reach the source / drain regions 21, respectively. The inner surface of each of the contact holes 5 is filled with a barrier metal 6, and each of the contact holes 5 is filled with a tungsten plug 7, for example.

The metal wiring 8 of the first level, for example made of aluminum, is placed on the interlayer insulating film 4 such that the pair of first levels of wiring 8 are positioned on the tungsten plug 7 filled in the contact hole 5. Is formed. The first oxide film 9 is stacked on the entire surface to form a thin liner film covering the wiring 8 of the first level. The HSQ film 10 is laminated on the front surface to fill the gap between the metal wirings 8 and to cover the metal wirings 8. In addition, the second oxide film 11 is laminated on the HSQ film. Thus, a first level interlayer insulating film is formed to have a flattened top surface.

The via hole 12 has a first level interlayer insulating film (second oxide film 11 and HSQ film) so as to reach one of a pair of first level wirings 8 respectively connected to the source / drain regions 21. 10)) through. The inner surface of via hole 12 is filled with barrier metal 13, and via hole 12 is filled with tungsten plug 14, for example.

Further, for example, the second level metal wiring 15 made of aluminum alloy is interlayer insulating film of the first level so that one of the second level wiring 15 is located on the tungsten plug 14 filled in the via hole 12. (Second oxide film 11). A second level interlayer insulating film 16 is stacked on the entire surface to fill the gaps between the metal wires 15 and to cover the metal wires 15.

Hereinafter, a first embodiment of the process according to the present invention for manufacturing a semiconductor device having a multilayer wiring structure having an improved hydrogen silsesquioxane film for interlayer insulation will be described with reference to FIG.

FIG. 1A is a semiconductor substrate in which various circuit elements (not shown in A of FIG. 1) including a transistor are formed and a plurality of metal wires 102 are formed on the plasma SiO ₂ film 101 (FIG. A condition is shown in which the plasma SiO ₂ film 101 is formed of an interlayer insulating film on (not shown in A of 1). The metal wire 102 may be formed by, for example, forming a metal film on the plasma SiO ₂ film 101 and then patterning the metal film by a lithography process.

Here, the plasma SiO ₂ film 101 is a zero level interlayer insulating film 4 (i.e., the lowest level interlayer insulating film SiO ₂ film) on the main surface of the semiconductor substrate 1 shown in FIG. It may be considered that it corresponds to the first level interlayer insulating film 10 + 11 shown in Fig. 4 or the second or more high level interlayer insulating film. Accordingly, the metal wiring 102 is formed of the metal wiring 8 of the first level formed on the interlayer insulating film 4 of the 0th level shown in FIG. 4, or the interlayer insulating film 10 of the first level shown in FIG. It can be considered that it corresponds to the second level interlayer insulating film 15 formed on +11) or the higher level metal wiring formed on the second or more high level interlayer insulating film.

Thereafter, as shown in FIG. 1B, as the liner film 103, a plasma enhanced tetraethyloxysilane (PETOS) film is formed to a thickness of about 100 nm. Here, the thickness of the liner film 103 is sufficiently shorter than the height of the metal wiring 102.

Here, as shown in Fig. 1C, hydrogen plasma processing is performed on the PETEOS film 103 by a parallel plate type plasma apparatus using a high frequency voltage of 13.56 MHz. In addition to the above process, not only a hydrophobic group of Si—H bond is formed on the surface of the PETEOS film 103, but also the moisture contained in the PETEOS film 103 is considerably reduced. As a result, the hydrophobic liner film 104 is formed to absorb almost no moisture.

Thereafter, as shown in FIG. 1D, an HSQ film 105 is formed on the entire surface with a thickness of about 400 nm to fill the gap between the metal wires 102 and to cover the metal wires 102. In addition, the stacked HSQ films 105 are fired. Thus, an interlayer insulator is formed.

In the above-described process, since the liner film 104 formed of the PETEOS film is hydrophobic, the liner film 104 hardly absorbs moisture. In addition, the moisture contained in the liner film 104 is quite low. Therefore, when the HSQ film 105 is fired, moisture is not discharged from the liner film 104 so that moisture is not absorbed by the HSQ film 105. As a result, the dielectric constant of the HSQ film 105 is kept low by about three.

In the above embodiment, the plasma gas used for the hydrophobization treatment contains hydrogen as well as an inert gas such as argon and ammonia may be added to stabilize the plasma discharge. In addition, a parallel plate plasma apparatus is used. However, it is possible to shorten the processing time by using a high density plasma apparatus such as an electron cycrotron resonance (ECR) plasma apparatus, an inductively-coupled plasma (ICP) apparatus, and a helicon plasma source apparatus.

Hereinafter, a second embodiment according to the present invention for manufacturing a semiconductor device having a multi-layered wiring structure having an improved hydrogen silsesquioxane film for interlayer insulation will be described with reference to FIGS. 2A-2C. The second embodiment differs in that the liner film 103 is not formed and the HMDS (hexamethyl disilazane) process is used as the hydrophobization treatment.

FIG. 2A is a view similar to A of FIG. 1. That is, A of FIG. 2 shows a semiconductor substrate (not shown) including transistors and a plurality of metal wires 202 are formed on a semiconductor substrate (not shown) formed on the plasma SiO ₂ film 201. The conditions in which the plasma SiO ₂ film 101 is formed of an interlayer insulating layer are shown.

Here, as shown in FIG. 2B, an HMDS process is performed. In addition to the above process, not only the hydrophobic groups of the Si—CH ₃ bonds are formed on the exposed portions of the plasma SiO ₂ film 201 which are not covered by the plurality of metal wires 202, but also the exposure of the plasma SiO ₂ film 201. The moisture contained in the parts is significantly reduced. As a result, hydrophobic surface layer 203 having a thickness of about 50 nm and containing only a reduced amount of moisture is formed on the exposed surface of plasma SiO ₂ film 201. The hydrophobic surface layer 203 absorbs little moisture.

The HMDS process is performed by exposing the exposed portion (hydrophobic portion) of the plasma SiO ₂ film 201 to the vapor of hexamethyl disilazane (HMDS), represented by (CH ₃ ) ₃ Si-NH-Si (CH ₃ ) ₃ . . As a result, at least the surface layer of the exposed portion of the plasma SiO ₂ film 201 becomes hydrophobic.

Here, the following chemical reaction occurs in the surface layer of the exposed portion of the plasma SiO ₂ film 201.

2Si-OH + (CH ₃ ) ₃ Si-NH-Si (CH ₃ ) ₃ → 2Si-O-Si- (CH ₃ ) ₃ + NH ₃

Thereafter, as shown in FIG. 2C, an HSQ film 204 is formed on the entire surface with a thickness of about 400 nm to fill the gap between the metal wires 202 and to cover the metal wires 202. In addition, the formed HSQ film 204 is fired. After that, an interlayer insulator is formed.

In the process described above, the exposed surface of the plasma SiO ₂ film is formed on the hydrophobic surface layer 203 so that it absorbs almost no moisture and contains only a very low degree of moisture. Therefore, when the HSQ film 204 is fired, moisture is not discharged from the exposed surface of the plasma SiO ₂ film so that the moisture is not absorbed by the HSQ film 204. As a result, the dielectric constant of the HSQ film 204 is kept low by about three.

Here, those skilled in the present field may, in the first embodiment, perform the HMDS process on the liner film 103 instead of the hydrogen plasma process, and in the second embodiment, the hydrogen plasma process instead of the HMDS process may expose the plasma SiO ₂ film. It will of course be appreciated that this may be done for a given surface.

As seen from above, according to the present invention, the surface layer located under the HSQ film and in direct contact with the HSQ film is formed of a hydrophobic surface layer. Therefore, when the HSQ film is fired, moisture is not discharged from the lower surface layer, and as a result, the low dielectric constant of the HSQ film never rises.

As mentioned above, although this invention was demonstrated according to the most suitable Example, this invention is not limited only to the structure of the said Example, A various correction and change from the structure of the said Example are also included in the scope of the present invention.

Claims (14)

A semiconductor device having a multilayer wiring structure comprising an interlayer insulating film including at least a hydrogen silsesquioxane film, And an insulating film under the hydrogen silsesquioxane film of the interlayer insulating film is provided with a hydrophobic surface layer directly connected to the hydrogen silsesquioxane film. The method of claim 1, And a plasma SiO ₂ film formed on the semiconductor substrate and a plurality of metal interconnections formed on the plasma SiO ₂ film, The insulating film under the hydrogen silsesquioxane film is formed of a hydrophobic liner film formed to cover the metal wiring and the plasma SiO ₂ film, And the hydrogen silsesquioxane film is laminated on the hydrophobic liner film so as to fill the gap between the metal wirings. The method of claim 2, And the hydrophobic liner film is formed of a plasma SiO ₂ liner film having a hydrophobic group of a Si—H bond or a Si—CH ₃ bond. The method of claim 1, And a plasma SiO ₂ film formed on the semiconductor substrate and a plurality of metal interconnections formed on the plasma SiO ₂ film, The insulating film under the hydrogen silsesquioxane film is formed of an exposed portion of the plasma SiO ₂ film not covered with the plurality of metal wires, The exposed portion of the plasma SiO ₂ film has a hydrophobic surface layer, And the hydrogen silsesquioxane film is laminated on the hydrophobic surface layer of the plasma SiO ₂ film to fill the gap between the metal wirings. The method of claim 4, wherein And the hydrophobic surface layer is formed of the surface layer of the exposed portion of the plasma SiO ₂ film and has a hydrophobic group of Si—H bond or Si—CH ₃ bond. A method of manufacturing a semiconductor device having a multilayer wiring structure having an interlayer insulating film, Performing a hydrophobization treatment on at least a portion of the lower insulating film formed on the semiconductor substrate, And forming hydrogen silsesquioxane as an interlayer insulating film on said at least part of said lower insulating film. The method of claim 6, The at least part of the lower insulating film is formed of a plasma SiO ₂ film, and the hydrophobization treatment is performed by exposing the plasma SiO ₂ film to hydrogen plasma to convert the plasma SiO ₂ film into a film having a hydrophobic group of Si—H bond. A method for manufacturing a semiconductor device. The method of claim 6, Said at least a portion of the lower insulating film is formed of a plasma SiO ₂ film, and the hydrophobic treatment is executed to stop the plasma SiO ₂ sikimeuroseo exposed to a vapor of hexamethyldisilazane (hexamethyl disilazane) the plasma SiO ₂ film Si-CH ₃ A method for manufacturing a semiconductor device, characterized by converting to a film having a hydrophobic group of bonds. The method of claim 6, Forming a plurality of metal wirings on the interlayer insulating film formed on the semiconductor substrate; Forming a plasma SiO ₂ liner film on the interlayer insulating film to cover the plurality of metal wires; And performing the hydrophobization treatment on the plasma SiO ₂ liner film to convert the plasma SiO ₂ liner film into a hydrophobic insulating liner film, And the hydrogen silesquioxane film is formed on the hydrophobic insulating liner film so as to fill a gap between the plurality of metal wirings. The method of claim 9, And wherein said hydrophobization treatment is performed by exposing said plasma SiO ₂ liner film to hydrogen plasma so that at least one surface of said plasma SiO ₂ liner film is converted to a film having a hydrophobic group of Si—H bond. The method of claim 9, The hydrophobic treatment is to be converted into a film having been run sikimeuro exposed film the plasma SiO ₂ liner in steam of hexamethyldisilazane (hexamethyl disilazane) The plasma SiO ₂ liner film at least one surface is an small number of Si-CH ₃ bond A method for manufacturing a semiconductor device. The method of claim 6, Forming a plurality of metal wires on the plasma SiO ₂ film formed on the semiconductor substrate; Further comprising the step of performing the hydrophobization treatment on the exposed portion of the plasma SiO ₂ film not covered with the metal wiring, As a result, at least one surface layer of the exposed portion of the plasma SiO ₂ film is converted into a hydrophobic surface layer, And the hydrogen silsesquioxane is formed on the plasma SiO ₂ film to fill the gap between the metal wirings. The method of claim 12, The hydrophobization treatment is performed by exposing the exposed portion of the plasma SiO ₂ film to hydrogen plasma so that the surface layer of the exposed portion of the plasma SiO ₂ film is converted to a film having a hydrophobic group of Si—H bond. Way. The method of claim 12, The hydrophobic treatment is a film having a small number of the plasma the exposed parts of hexamethyldisilazane is executed sikimeuroseo exposed to the vapor above the surface layer wherein the plasma SiO ₂ film the exposed portion of the (hexamethyl disilazane) of SiO ₂ is Si-CH ₃ bond Method for manufacturing a semiconductor device, characterized in that the switching.