KR100335129B1 - Method for forming contact of semiconductor device - Google Patents
Method for forming contact of semiconductor device Download PDFInfo
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- KR100335129B1 KR100335129B1 KR1019990061268A KR19990061268A KR100335129B1 KR 100335129 B1 KR100335129 B1 KR 100335129B1 KR 1019990061268 A KR1019990061268 A KR 1019990061268A KR 19990061268 A KR19990061268 A KR 19990061268A KR 100335129 B1 KR100335129 B1 KR 100335129B1
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- film
- titanium
- semiconductor substrate
- forming
- contact
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 49
- 238000000034 method Methods 0.000 title claims abstract description 24
- 239000010936 titanium Substances 0.000 claims abstract description 39
- 239000000758 substrate Substances 0.000 claims abstract description 38
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 35
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 16
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 12
- 239000010937 tungsten Substances 0.000 claims abstract description 12
- 229910021341 titanium silicide Inorganic materials 0.000 claims abstract description 11
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 6
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 5
- 238000005121 nitriding Methods 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 abstract description 2
- 239000002184 metal Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 9
- 229920002120 photoresistant polymer Polymers 0.000 description 9
- 229910010421 TiNx Inorganic materials 0.000 description 6
- 230000004888 barrier function Effects 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000002776 aggregation Effects 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 229910021332 silicide Inorganic materials 0.000 description 2
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 2
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- 229910008484 TiSi Inorganic materials 0.000 description 1
- 239000012790 adhesive layer Substances 0.000 description 1
- 238000005054 agglomeration Methods 0.000 description 1
- 238000004220 aggregation Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76847—Barrier, adhesion or liner layers formed in openings in a dielectric the layer being positioned within the main fill metal
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 기판과 금속 콘택에 있어서 콘택 저항 및 접합 누설(Junction Leakage) 등의 전기적 특성을 개선하도록 한 반도체 소자의 콘택 형성방법에 관한 것으로서, 반도체 기판상에 콘택홀을 갖는 절연막을 형성하는 단계와, 상기 콘택홀을 포함한 반도체 기판의 전면에 600℃이하의 저온 PECVD법으로 티타늄막을 형성하는 단계와, 상기 티타늄막이 형성된 반도체 기판에 약 1000sccm의 유량으로 NH3가스를 주입하여 티타늄막을 질화시키는 단계와, 상기 질화된 티타늄막상에 약 680℃이상의 고온 CVD법으로 질화 티타늄막을 형성함과 동시에 질화된 티타늄막과 반도체 기판의 계면에 티타늄 실리사이드막을 형성하는 단계와, 상기 콘택홀을 포함한 반도체 기판의 전면에 텅스텐막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The present invention relates to a method for forming a contact of a semiconductor device to improve electrical characteristics such as contact resistance and junction leakage in a substrate and a metal contact, comprising the steps of: forming an insulating film having a contact hole on the semiconductor substrate; Forming a titanium film on the front surface of the semiconductor substrate including the contact hole by a low temperature PECVD method at 600 ° C. or below, and nitriding the titanium film by injecting NH 3 gas at a flow rate of about 1000 sccm into the semiconductor substrate on which the titanium film is formed; And forming a titanium nitride film on the nitrided titanium film by a high temperature CVD method of about 680 ° C. or more and simultaneously forming a titanium silicide film at an interface between the nitrided titanium film and the semiconductor substrate, and on the entire surface of the semiconductor substrate including the contact hole. And forming a tungsten film.
Description
본 발명은 반도체 소자의 제조공정에 관한 것으로, 특히 전기적 특성을 향상하는데 적당한 반도체 소자의 콘택 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a process for manufacturing a semiconductor device, and more particularly to a method for forming a contact for a semiconductor device suitable for improving electrical characteristics.
일반적으로 콘택 플러그를 형성할 때 사용하는 CVD 텅스텐막은 접착층(Adhesion Layer)없이 산화막 혹은 다른 절연막 위에 증착할 경우 접착이 좋지 않아 떨어진다.In general, a CVD tungsten film used to form a contact plug is degraded due to poor adhesion when deposited on an oxide film or another insulating film without an adhesion layer.
따라서 CVD 텅스텐막과 접착성이 좋은 티타늄(Ti)막을 접착층으로 사용한 경우 티타늄막은 CVD 텅스텐막에 대해 높은 접착율(High Sticking Coefficient)을 갖고 있을 뿐만 아니라 실리콘 콘택(Silicon Contact) 계면에서 고온처리시 티타늄 실리사이드가 형성되어 콘택 저항을 낮춘다.Therefore, when using a CVD tungsten film and a good adhesion (Ti) film as an adhesive layer, the titanium film not only has a high sticking coefficient for the CVD tungsten film but also has a high temperature at the silicon contact interface. Silicide is formed to lower the contact resistance.
그러나 티타늄막은 높은 반응성 재료이기 때문에 텅스텐막 증착시 사용하는 반응가스인 WF6과 반응하여 고저항 컴파운드(Compound)인 TiF3을 형성할 뿐만 아니라 불소(Fluorine)의 확산에 대한 베리어(Barrier)역할을 하지 못한다. 따라서 질화 티타늄(TiN)막을 콘택 확산 베리어막으로 사용하고 있다.However, since titanium film is a highly reactive material, it reacts with WF 6 , a reaction gas used to deposit tungsten film, to form TiF 3 , a high resistance compound, and also acts as a barrier to diffusion of fluorine. can not do. Therefore, a titanium nitride (TiN) film is used as the contact diffusion barrier film.
한편, 상기 티타늄막과 질화 티타늄막을 베리어층으로 사용할 때 상기 티타늄막 형성시 반도체 기판의 계면에 티타늄 실리사이드막이 형성되고, 스텝 커버레이지(Step Coverage)도 우수해 콘택 사이즈가 아주 작은 딥 콘택(Deep Contact)에서 이용하고 있다.Meanwhile, when the titanium film and the titanium nitride film are used as the barrier layer, a titanium silicide film is formed at the interface of the semiconductor substrate when the titanium film is formed, and the step contact is also excellent, so that a deep contact having a very small contact size (Deep Contact) I use it in).
이하, 첨부된 도면을 참고하여 종래의 반도체 소자의 콘택 형성방법을 설명하면 다음과 같다.Hereinafter, a method for forming a contact of a conventional semiconductor device will be described with reference to the accompanying drawings.
도 1a 내지 도 1c는 종래의 반도체 소자의 콘택 형성방법을 나타낸 공정단면이다.1A to 1C are cross-sectional views illustrating a method for forming a contact of a conventional semiconductor device.
도 1a에 도시한 바와 같이, 반도체 기판(11)상에 산화막(12)을 형성하고, 상기 산화막(12)상에 포토레지스트(13)를 도포한 후, 노광 및 현상공정을 포토레지스트(13)를 패터닝하여 콘택영역을 정의한다.As shown in FIG. 1A, an oxide film 12 is formed on a semiconductor substrate 11, a photoresist 13 is applied on the oxide film 12, and then an exposure and development process is performed on the photoresist 13. Pattern to define the contact area.
이어, 상기 패터닝된 포토레지스트(13)를 마스크로 이용하여 상기 반도체 기판(11)의 표면이 소정부분 노출되도록 산화막(12)을 선택적으로 제거하여 콘택홀(14)을 형성한다.Subsequently, the contact layer 14 is formed by selectively removing the oxide layer 12 so that the surface of the semiconductor substrate 11 is exposed by using the patterned photoresist 13 as a mask.
도 1b에 도시한 바와 같이, 상기 포토레지스트(13)를 제거하고, 상기 반도체 기판(11)의 전면에 세정 공정을 실시하여 상기 반도체 기판(11)의 표면에 형성된 자연 산화막(도시되지 않음)을 제거한다.As shown in FIG. 1B, the photoresist 13 is removed, and a natural oxide film (not shown) formed on the surface of the semiconductor substrate 11 is removed by performing a cleaning process on the entire surface of the semiconductor substrate 11. Remove
이어, 상기 콘택홀(14)을 포함한 반도체 기판(11)의 전면에 TiCl4를 소스(Source)로 한 PECVD(Plasma Enhanced Chemical Vapor Deposition)법으로 티타늄(Ti)막(15)을 고온증착(약 650℃)한다.Subsequently, the titanium film 15 is deposited at a high temperature on the entire surface of the semiconductor substrate 11 including the contact hole 14 by a plasma enhanced chemical vapor deposition (PECVD) method using TiCl 4 as a source. 650 ° C).
이때 상기 콘택홀(14) 저면의 반도체 기판(11) 표면에는 반도체 기판(11)의 실리콘(Si)과 티타늄막(15)의 티타늄(Ti)이 반응하여 티타늄 실리사이드(TiSi2)막(16)이 형성된다.At this time, the silicon (Si) of the semiconductor substrate 11 and the titanium (Ti) of the titanium film 15 react with the surface of the semiconductor substrate 11 at the bottom of the contact hole 14 to form a titanium silicide (TiSi 2 ) film 16. Is formed.
도 1c에 도시한 바와 같이, 상기 티타늄 실리사이드막(16)을 포함한 반도체 기판(11)의 전면에 TiCl4를 소스로 한 CVD법으로 질화 티타늄(TiN)막(17)을 형성하고, 상기 질화 티타늄막(17)상에 CVD법으로 텅스텐(W)막(18)을 형성한다.As shown in FIG. 1C, a titanium nitride (TiN) film 17 is formed on the entire surface of the semiconductor substrate 11 including the titanium silicide film 16 by a CVD method using TiCl 4 as the source, and the titanium nitride A tungsten (W) film 18 is formed on the film 17 by CVD.
이후 공정은 도시하지 않았지만, 상기 텅스텐막(18)과 질화 티타늄막(17) 및 티타늄막(15)의 전면에 에치백이나 CMP 공정을 통해 상기 콘택홀(14)내부에 콘택플러그를 형성한다.Although not shown, a contact plug is formed inside the contact hole 14 through an etch back or CMP process on the tungsten film 18, the titanium nitride film 17, and the titanium film 15.
그러나 상기와 같은 종래의 반도체 소자의 콘택 형성방법에 있어서 다음과 같은 문제점이 있었다.However, the above-described conventional method for forming a contact of a semiconductor device has the following problems.
즉, 티타늄막 형성시 기판의 표면에 형성되는 티타늄 실리사이드막의 응집작용(Agglomeration)의 제어가 어렵고 티타늄막 및 질화 티타늄막의 두께를 아주 얇게 형성하기가 어렵다.That is, it is difficult to control the agglomeration of the titanium silicide film formed on the surface of the substrate when the titanium film is formed, and to form a very thin thickness of the titanium film and the titanium nitride film.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출한 것으로 기판과 금속 콘택에 있어서 콘택 저항 및 접합 누설(Junction Leakage) 등의 전기적 특성을 개선하도록 한 반도체 소자의 콘택 형성방법을 제공하는데 그 목적이 있다.An object of the present invention is to provide a method for forming a contact of a semiconductor device to improve electrical characteristics such as contact resistance and junction leakage in substrate and metal contacts. .
도 1a 내지 도 1c는 종래의 반도체 소자의 콘택 형성방법을 나타낸 공정단면도1A to 1C are cross-sectional views illustrating a method for forming a contact of a conventional semiconductor device.
도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 콘택 형성방법을 나타낸 공정단면도2A to 2D are cross-sectional views illustrating a method of forming a contact for a semiconductor device according to the present invention.
도면의 주요 부분에 대한 부호의 설명Explanation of symbols for the main parts of the drawings
21 : 반도체 기판 22 : 산화막21 semiconductor substrate 22 oxide film
23 : 포토레지스트 24 : 콘택홀23: photoresist 24: contact hole
25 : 티타늄막 26 : TiNx막25 titanium film 26 TiNx film
27 : 질화 티타늄막 28 : 티타늄 실리사이드막27: titanium nitride film 28: titanium silicide film
29 : 텅스텐막29: tungsten film
상기와 같은 목적을 달성하기 위한 본 발명에 의한 반도체 소자의 콘택 형성방법은 반도체 기판상에 콘택홀을 갖는 절연막을 형성하는 단계와, 상기 콘택홀을 포함한 반도체 기판의 전면에 600℃이하의 저온 PECVD법으로 티타늄막을 형성하는 단계와, 상기 티타늄막이 형성된 반도체 기판에 약 1000sccm의 유량으로 NH3가스를 주입하여 티타늄막을 질화시키는 단계와, 상기 질화된 티타늄막상에 680℃이상의 고온 CVD법으로 질화 티타늄막을 형성함과 동시에 질화된 티타늄과 반도체 기판의 계면에 티타늄 실리사이드막을 형성하는 단계와, 상기 콘택홀을 포함한 반도체 기판의 전면에 텅스텐막을 형성하는 단계를 포함하여 이루어짐을 특징으로 한다.The contact forming method of the semiconductor device according to the present invention for achieving the above object comprises the steps of forming an insulating film having a contact hole on the semiconductor substrate, low temperature PECVD below 600 ℃ on the front surface of the semiconductor substrate including the contact hole Forming a titanium film, injecting NH 3 gas at a flow rate of about 1000 sccm into the semiconductor substrate on which the titanium film is formed, and nitriding the titanium film; and forming a titanium nitride film by a high temperature CVD method of 680 ° C. or higher on the nitrided titanium film And forming a titanium silicide film at the interface between the nitrided titanium and the semiconductor substrate and forming a tungsten film on the entire surface of the semiconductor substrate including the contact hole.
이하, 첨부된 도면을 참고하여 본 발명에 의한 반도체 소자의 콘택 형성방법을 상세히 설명하면 다음과 같다.Hereinafter, a method for forming a contact of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2d는 본 발명에 의한 반도체 소자의 콘택 형성방법을 나타낸 공정단면도이다.2A to 2D are cross-sectional views illustrating a method of forming a contact for a semiconductor device according to the present invention.
도 2a에 도시한 바와 같이, 반도체 기판(21)상에 산화막(22)을 형성하고, 상기 산화막(22)상에 포토레지스트(23)를 도포한 후, 노광 및 현상공정을 포토레지스트(23)를 패터닝하여 콘택영역을 정의한다.As shown in FIG. 2A, an oxide film 22 is formed on a semiconductor substrate 21, a photoresist 23 is applied on the oxide film 22, and then an exposure and development process is performed on the photoresist 23. Pattern to define the contact area.
이어, 상기 패터닝된 포토레지스트(23)를 마스크로 이용하여 상기 반도체 기판(21)의 표면이 소정부분 노출되도록 산화막(22)을 선택적으로 제거하여 콘택홀(24)을 형성한다.Next, the contact layer 24 is formed by selectively removing the oxide layer 22 so that the surface of the semiconductor substrate 21 is exposed by using the patterned photoresist 23 as a mask.
도 2b에 도시한 바와 같이, 상기 포토레지스트(23)를 제거하고, 상기 반도체 기판(21)의 전면에 세정 공정을 실시하여 상기 반도체 기판(21)의 표면에 형성된 자연 산화막(도시되지 않음)을 제거한다.As shown in FIG. 2B, the photoresist 23 is removed, and a natural oxide film (not shown) formed on the surface of the semiconductor substrate 21 is removed by performing a cleaning process on the entire surface of the semiconductor substrate 21. Remove
이어, 상기 콘택홀(24)을 포함한 반도체 기판(21)의 전면에 TiCl4를 소스로 이용한 저온(스테이지 히터 온도가 600℃ 이하) PECVD법으로 티타늄(Ti)막(25)을 형성한다.Next, a titanium (Ti) film 25 is formed on the entire surface of the semiconductor substrate 21 including the contact hole 24 by a low temperature (stage heater temperature of 600 ° C. or less) PECVD method using TiCl 4 as a source.
여기서 상기 티타늄막(25) 형성시 스테이지 히터 온도가 600℃ 이하이면 반도체 기판(21)의 온도는 530℃이하로 하기 때문에 상기 티타늄막(25)과 반도체 기판(21)의 계면에 티타늄 실리사이드가 형성되지 않는다.Here, if the stage heater temperature is 600 ° C. or less when the titanium film 25 is formed, the temperature of the semiconductor substrate 21 is 530 ° C. or less, so that titanium silicide is formed at the interface between the titanium film 25 and the semiconductor substrate 21. It doesn't work.
도 2c에 도시한 바와 같이, 상기 티타늄막(25)이 형성된 챔버 내부에 NH3가스를 1000sccm의 유량으로 주입하여 상기 티타늄막(25)을 질화시키어 TiNx막(26)을 형성한다.As shown in FIG. 2C, NH 3 gas is injected into the chamber in which the titanium film 25 is formed at a flow rate of 1000 sccm to nitride the titanium film 25 to form a TiNx film 26.
여기서 상기 NH3가스는 상기 티타늄막(25)을 형성한 동일 챔버내에 주입한다.The NH 3 gas is injected into the same chamber in which the titanium film 25 is formed.
도 2d에 도시한 바와 같이, 상기 콘택홀(24)을 포함한 반도체 기판(21)의 전면에 TiCl4를 소스로 이용한 고온(스테이지 히터 온도는 680℃ 이상) CVD법으로 질화 티타늄(TiN)막(27)을 형성한다.As shown in FIG. 2D, a titanium nitride (TiN) film (using a high temperature (stage heater temperature of 680 ° C. or more) using TiCl 4 as a source on the entire surface of the semiconductor substrate 21 including the contact hole 24 (CVD) ( 27).
여기서 상기 질화 티타늄막(27) 형성시 상기 TiNx막(26)과 반도체 기판(21)의 계면에서 TiNx막(26)의 티타늄(Ti)과 반도체 기판(21)의 실리콘(Si)이 반응하여 티타늄 실리사이드막(28)이 형성된다.Here, when the titanium nitride film 27 is formed, titanium (Ti) of the TiNx film 26 and silicon (Si) of the semiconductor substrate 21 react at the interface between the TiNx film 26 and the semiconductor substrate 21. The silicide film 28 is formed.
이어, 상기 질화 티타늄막(27)상에 CVD법으로 텅스텐막(29)을 형성한다.Next, a tungsten film 29 is formed on the titanium nitride film 27 by CVD.
이후 공정은 도시하지 않았지만, 상기 텅스텐막(29)과 질화 티타늄막(27) 및 TiNx막(27)의 전면에 에치백이나 CMP 공정을 통해 상기 콘택홀(24)내부에 콘택 플러그를 형성한다.Although not shown, a contact plug is formed inside the contact hole 24 through an etch back or CMP process on the tungsten layer 29, the titanium nitride layer 27, and the TiNx layer 27.
이상에서 설명한 바와 같이 본 발명에 의한 반도체 소자의 콘택 형성방법은 다음과 같은 효과가 있다.As described above, the method for forming a contact of a semiconductor device according to the present invention has the following effects.
첫째, 고온 CVD법에 의해 질화 티타늄막 형성시 TiNx의 티타늄과 실리콘과 반응하게 하여 티타늄 실리사이드막을 얇게 형성함으로서 티타늄 실리사이드막의응집작용을 방지할 수 있다.First, when the titanium nitride film is formed by the high temperature CVD method, the titanium silicide film is thinly formed by reacting with titanium and silicon of TiNx to prevent the aggregation of the titanium silicide film.
둘째, 티타늄막의 질화(Nitridation)를 통해 질화 티타늄막의 두께를 줄일 수 있기 때문에 이후 콘택 플러그 공정에 대한 확산 베리어를 형성하면서도 베리어 두께를 낮추어 콘택홀에서의 텅스텐 접착성이 우수함과 동시에 콘택에 있어서의 전기적 특성을 개선할 수 있다.Second, since the thickness of the titanium nitride film can be reduced through nitriding of the titanium film, the thickness of the barrier film is lowered while forming a diffusion barrier for the contact plug process. Properties can be improved.
Claims (5)
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