KR100332883B1 - Laminated chip parts - Google Patents
Laminated chip parts Download PDFInfo
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- KR100332883B1 KR100332883B1 KR1020000042669A KR20000042669A KR100332883B1 KR 100332883 B1 KR100332883 B1 KR 100332883B1 KR 1020000042669 A KR1020000042669 A KR 1020000042669A KR 20000042669 A KR20000042669 A KR 20000042669A KR 100332883 B1 KR100332883 B1 KR 100332883B1
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4007—Surface contacts, e.g. bumps
- H05K3/4015—Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
Abstract
본 발명은 적층칩 부품에 있어서, 적층상태의 칩부품 제조시 실제 제품상태에서 정확한 재료정수(유전율, 수축율)를 계산함으로써 이에따른 실제품의 오차 발생을 최소화 하고, 정확한 설계가 가능토록 되어 제품의 신뢰성을 향상시키도록 한 유전율 측정이 용이한 적층 칩부품에 관한 것으로서 그 기술적인 구성은, 측정전극패턴이 형성되는 상부시트와, 상기 전극패턴이 오버랩토록 접지패턴이 형성되면서 상기 접지패턴의 일측에 감지전극패턴이 연결되는 내측시트및, 상기 내측시트의 하측에 일정 형상의 특성패턴이 형성되는 동작시트와, 상기 동작시트의 하측에 접지패턴이 형성되는 하부시트를 포함하여 구성되는 것을 요지로 한다.In the present invention, in the manufacture of laminated chip parts, the accurate material constants (dielectric constant, shrinkage) are calculated in the actual product state to minimize the occurrence of errors in the actual product according to the actual product state, so that accurate design is possible and the reliability of the product The present invention relates to a multilayer chip component having an easy dielectric constant measurement for improving the dielectric constant. The technical configuration includes: an upper sheet on which a measuring electrode pattern is formed, and a ground pattern formed on the electrode pattern so as to overlap the sensing pattern on one side of the ground pattern An inner sheet to which an electrode pattern is connected, and an operating sheet having a predetermined characteristic pattern formed on the lower side of the inner sheet, and a lower sheet having a ground pattern formed on the lower side of the operating sheet are provided.
Description
본 발명은 고주파, 협대역에 사용되는 적층 칩에 있어서, 적층상태의 칩부품 제조시 실제 제품상태에서 정확한 재료정수(유전율, 수축율)를 계산함으로써 이에따른 실제품의 오차 발생을 최소화 하고, 정확한 설계가 가능토록 되어 제품의 신뢰성을 향상시키도록 한 적층 칩부품에 관한 것이다.In the present invention, in the laminated chip used in high frequency and narrow band, the accurate material constant (dielectric constant, shrinkage) is calculated in the actual product state when manufacturing the chip parts in the stacked state, thereby minimizing the occurrence of errors in the actual product, The present invention relates to a laminated chip component that is made possible to improve the reliability of the product.
최근 이동통신의 급속한 발달로 사용주파수대가 점차로 고주파, 협대역화 되어지며 이에따른 이동통신 부품의 개발역시 요구되는 고주파, 협대역화 추세로 가고 있고, 상기 이동통신 부품은 유전체로 이루어져 생산자가 제공하는 특성의 구조를 설계에 그대로 적용하거나 제품제작과는 별도로 수축율을 측정하는 실험과 유전율을 측정하기 의한 샙플을 제작하여 사용 하였다.Recently, due to the rapid development of mobile communication, the use frequency band is gradually becoming high frequency and narrow band, and accordingly, the development of mobile communication component is also going to the trend of high frequency and narrow band, which is required. The structure of the characteristic was applied to the design as it was, or it was used to manufacture the sample by measuring the dielectric constant and the sample by measuring the dielectric constant separately from the production of the product.
이와같은 기술과 관련된 종래의 적층칩의 재료정수 측정방법은 도1에 도시한 바와같이, 유전체 파우더(10)를 성형하여 일정형상의 시트(20)를 형성한후 소결하여 그 수축율 측정공정(40)을 수행하고, 상기 시트(20)의 상하측에 전극(30)을 형성하여 유전율을 측정하여 설계상태의 변수를 정하게 되는 것이다.In the conventional method of measuring the material constant of the laminated chip related to the above technique, as illustrated in FIG. 1, the dielectric powder 10 is formed to form a sheet 20 having a predetermined shape, followed by sintering to measure the shrinkage rate (40). ), And the electrode 30 is formed on the upper and lower sides of the sheet 20 to measure the dielectric constant to determine the parameters of the design state.
상기와 같은 재료정수 측정방법은, 소형의 칩 제품상태에서는 유전율을 측전하기가 힘들고, 수축율울 확인하기 위해서는 단면을 연마해 정확한 관찰을 수행하여야 하여 측정이 힘들게 되며, 이러한 방법도 측정상의 오류가 빈번하게 발생됨은 물론 설계치를 실제품에 적용시 소성등의 공정에 의해 유전율의 차이가 발생되어 제품의 신뢰성을 해치게 되는 단점이 있는 것이다.In the material constant measurement method as described above, it is difficult to measure the dielectric constant in the state of small chip products, and in order to check the shrinkage rate, it is difficult to measure the surface by grinding the cross section and performing accurate observation. Of course, when the design value is applied to the actual product, a difference in dielectric constant is generated by a process such as firing, which impairs the reliability of the product.
본 발명은 상기한 바와같은 종래의 여러 문제점들을 개선하기 위한 것으로서그 목적은, 적층상태의 칩부품 제조시 실제 제품상태에서 정확한 재료정수(유전율, 수축율)를 계산함으로써 이에따른 실제품의 오차 발생을 최소화 하고, 정확한 설계가 가능토록 되어 제품의 신뢰성을 향상시키며, 샘플과 실제품 사이의 특성치를 최소화 시키고, 설계오차를 실제 제품의 생산단계부터 줄여 공정상의 시간낭비를 줄일수 있도록 하는 적층 칩부품을 제공하는데 있다.The present invention is to solve the various problems as described above, the purpose of which is to calculate the exact material constant (dielectric constant, shrinkage) in the actual product state when manufacturing the chip parts in the laminated state to minimize the occurrence of errors in the actual product accordingly To improve the reliability of the product by minimizing the characteristics between the sample and the actual product, and to reduce the design errors from the production stage of the actual product, it is possible to provide a multilayer chip component that can reduce the time spent in the process. have.
도1은 종래의 적층칩 유전율 측정상태를 도시한 설명도1 is an explanatory diagram showing a conventional laminated chip dielectric constant measurement state
도2는 본 발명에 따른 유전율 측정이 용이한 적층칩을 도시한 개략도Figure 2 is a schematic diagram showing a laminated chip easy to measure the dielectric constant according to the present invention
도3은 본 발명에 따른 적층칩의 적층상태를 도시한 개략도Figure 3 is a schematic diagram showing the stacked state of the stacked chip according to the present invention
도4A,B는 본 발명의 다른 실시에 따른 적층칩의 적층상태를 도시한 개략도4A and 4B are schematic views showing the stacked state of a stacked chip according to another embodiment of the present invention.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
100...측정전극패턴 110...상부시트100.Measure electrode pattern 110.Top sheet
210...접지패턴 220...감지전극패턴210 ... earth pattern 220 ... electrode pattern
310...특성패턴 400...하부시트310 ... Characteristic pattern 400 ... Lower seat
410...접지패턴410 ... ground pattern
상기 목적을 달성하기 위한 기술적인 구성으로서 본 발명은, 상측에 측정전극패턴이 형성되는 상부시트와,The present invention as a technical configuration for achieving the above object, the upper sheet and the measuring electrode pattern is formed on the upper side,
상기 전극패턴이 오버랩토록 접지패턴이 형성되면서 상기 접지패턴의 일측에 감지전극패턴이 일체로 연결되는 내측시트및,An inner sheet in which a ground pattern is formed to overlap the electrode pattern, and a sensing electrode pattern is integrally connected to one side of the ground pattern;
상기 내측시트의 하측에 일정 형상의 특성패턴이 형성되는 동작시트와,An operation sheet for forming a characteristic pattern having a predetermined shape under the inner sheet;
상기 동작시트의 하측에 접지패턴이 형성되는 하부시트를 포함하여 구성되는 적층 칩부품을 마련함에 의한다.According to the present invention, a multilayer chip component including a lower sheet having a ground pattern formed under the operation sheet is provided.
이하, 첨부된 도면에 의거하여 본 발명의 실시예를 상세하게 설명하면 다음과 같다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도2는 본 발명에 따른 유전율 측정이 용이한 적층칩을 도시한 개략도이고, 도3은 본 발명에 따른 적층칩의 적층상태를 도시한 개략도이며, 도4A,B는 본 발명의 다른 실시에 따른 적층칩의 적층상태를 도시한 개략도로서 본 발명은, 상측에일정크기의 측정전극패턴(100)이 일체로 형성되는 유전체재질의 상부시트(110)가 설치되고, 상기 측정전극패턴(100)은, 상부시트(110)의 상측 표면에 형성되거나 상부시트(110)의 형성시 일체로 적층형성된다.Figure 2 is a schematic diagram showing a laminated chip easy to measure the dielectric constant according to the present invention, Figure 3 is a schematic diagram showing the stacked state of the stacked chip according to the present invention, Figures 4A, B is according to another embodiment of the present invention As a schematic diagram illustrating a stacked state of a stacked chip, the present invention includes an upper sheet 110 of a dielectric material having a predetermined sized measuring electrode pattern 100 integrally formed thereon, and the measuring electrode pattern 100 is It is formed on the upper surface of the top sheet 110 or integrally formed in the formation of the top sheet 110.
상기 상부시트(110)의 저부에 적층되는 내측시트(200)는, 상기 측정전극패턴(100)이 오버랩토록 접지패턴(210)이 형성되면서 상기 접지패턴(210)의 일측에 일체로 연결되는 감지전극패턴(220)이 일체로 설치된다.The inner sheet 200 stacked on the bottom of the upper sheet 110 may be sensed to be integrally connected to one side of the ground pattern 210 while the ground electrode 210 overlaps the measurement electrode pattern 100. The electrode pattern 220 is integrally installed.
상기 내측시트(200)의 하측에 저층되는 동작시트(300)는, 일정 형상을 갖도록 특성패턴(310)이 형성된다.A characteristic pattern 310 is formed in the operation sheet 300 to be stacked below the inner sheet 200 to have a predetermined shape.
상기 동작시트(300)의 하측에 적층되는 하부시트(400)는, 접지패턴(410)이 상측면에 적층형성된다.In the lower sheet 400 stacked below the operation sheet 300, the ground pattern 410 is stacked on the upper surface.
또한, 상기 상부시트(110)와 내측시트(200)및 동작시트(300)와 하부시트(400)에 각각 형성되는 전극패턴이 외부전극(450)에 연결토록 설치되는 구성으로 이루어 진다.In addition, the electrode patterns formed on the upper sheet 110 and the inner sheet 200 and the operation sheet 300 and the lower sheet 400 are formed so as to be connected to the external electrode 450.
이와같은 구성으로 이루어진 본 발명의 작용을 설명하면 다음과 같다.Referring to the operation of the present invention made of such a configuration as follows.
도2 내지 도4에 도시한 바와같이, 상부시트(110)와 내측시트(200)및 동작시트(300)와 하부시트(400)를 적층상태에서 외부단자(450)를 연결하여 실제적용되는 제품과 동일한 적층체를 형성하면 적층체의 상면에 형성되는 측정전극패턴(100)과 감지전극패턴(220)에 의해 실제 제품의 상태에서 유전율과 수축율의 확인이 가능하게 된다.2 to 4, the upper sheet 110, the inner sheet 200 and the operation sheet 300 and the lower sheet 400 by connecting the external terminal 450 in the laminated state is actually applied products When the same laminate is formed, the dielectric constant and shrinkage can be confirmed in the actual product state by the measuring electrode pattern 100 and the sensing electrode pattern 220 formed on the upper surface of the laminate.
또한, 칩 설계치를 도출하는데 중요한 요소인 수축율및 유전율을 용이하게 축정토록 된다.In addition, shrinkage and dielectric constant, which are important factors in deriving chip design values, can be easily calculated.
A=전극의 면적, C=측정된 캐패시턴스값, d=유전층두께A = area of electrode, C = measured capacitance value, d = dielectric layer thickness
그리고, 상기 수학식에 의하여 유전율을 측정하고자 할때는 상부시트(110)의 상하측에 형성되는 측정전극패턴(100)과 감지전극패턴(220)에 의해(실물 상태에서 A값과 d값이 용이하게 측정됨) 용이하게 측정토록 된다.When the dielectric constant is to be measured by the above equation, the measurement electrode pattern 100 and the sensing electrode pattern 220 formed on the upper and lower sides of the upper sheet 110 (the A value and the d value are easily in the real state). Measured) It is easy to measure.
또한, 동일재질로 형성되는 상부시트(110)의 상하측에 접촉토록 형성되는 측정전극패턴(100)과 접지패턴(210)은, 전극면적이 상이할때 발생되는 특성변화를 최소화 토록 측정전극패턴(100)이 수직선상에서 오버랩되면서 접지패턴(220)의 내측에 위치토록 형성된다.In addition, the measurement electrode pattern 100 and the ground pattern 210 which are formed to contact the upper and lower sides of the upper sheet 110 formed of the same material, the measurement electrode pattern to minimize the characteristic change generated when the electrode area is different As the 100 is overlapped on the vertical line, it is formed to be positioned inside the ground pattern 220.
한편, 도4에서와 같이 상이한 재질로 형성되는 상부시트(110)의 경우, 각각의 재질 상측에 측정전극패턴(100)을 형성하고, 상기 측정전극패턴(100)은 각각 수직성 방향에서 겹치도록 형성되어 그 일측에 감지전극패턴(220)이 일체로 연결되어 각각의 재질에 대한 수축율및 유전율을 측정하게 된다.Meanwhile, in the case of the upper sheet 110 formed of different materials as shown in FIG. 4, the measurement electrode patterns 100 are formed on the upper sides of the respective materials, and the measurement electrode patterns 100 overlap each other in the vertical direction. The sensing electrode pattern 220 is integrally connected to one side thereof to measure shrinkage and dielectric constant of each material.
그리고, 상기 상부시트(110)및 내측시트(200), 내측시트(200)의 하측에 적층되면서 특성패턴(310)이 형성되는 동작시트(300)와 그 하측에 적층되면서 접지패턴(410)이 형성되는 하부시트(400)가 일체로 적층된후 각각의 패턴에 절연되어 접지토록 외부단자(450)를 연결하면 기판에 실장이 가능토록 된다.Then, the upper sheet 110 and the inner sheet 200, the operation sheet 300 is laminated on the lower side of the inner sheet 200 and the characteristic pattern 310 is formed and the ground pattern 410 is laminated on the lower side After forming the lower sheet 400 is integrally stacked and is insulated in each pattern to connect the external terminal 450 to the ground to be mounted on the substrate.
상기 제품은 기판에 곧바로 실장할수 있도록 형성되는 실제부품의 수축율 및 유전율의 측정이 가능하여 적층상태의 칩제품을 설계할 경우 정확한 재료정수값을 실제의 칩 상태에서 측정함으로써 설계시의 변수발생을 최소화 할수 있게 되는 것이다.The product can measure the shrinkage and dielectric constant of the actual parts formed to be mounted directly on the board. When designing a chip product in a stacked state, the accurate material constant value is measured in the actual chip state to minimize the occurrence of design variables. You can do it.
이상과 같이 본 발명에 따른 적층 칩부품에 의하면, 적층상태의 칩제품을 설계할 경우 정확한 재료정수값을 실제의 칩 상태에서 측정함으로써 설계시의 변수발생을 최소화 할수 있고, 정확한 설계가 가능토록 되어 제품의 신뢰성을 향상시키며, 샘플과 실제품 사이의 특성치를 최소화 시키고, 설계오차를 실제 제품의 생산단계부터 줄여 공정상의 시간낭비를 줄일수 있도록 하는 등의 효과가 있다.As described above, according to the multilayer chip component according to the present invention, when designing a chip product in a stacked state, the accurate material constant value is measured in an actual chip state, thereby minimizing the generation of variables in the design and enabling accurate design. It improves the reliability of the product, minimizes the characteristic value between the sample and the actual product, and reduces the design time from the production stage of the actual product to reduce the time waste in the process.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000042669A KR100332883B1 (en) | 2000-07-25 | 2000-07-25 | Laminated chip parts |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000042669A KR100332883B1 (en) | 2000-07-25 | 2000-07-25 | Laminated chip parts |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20020009181A KR20020009181A (en) | 2002-02-01 |
| KR100332883B1 true KR100332883B1 (en) | 2002-04-15 |
Family
ID=19679750
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000042669A KR100332883B1 (en) | 2000-07-25 | 2000-07-25 | Laminated chip parts |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100332883B1 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100848193B1 (en) * | 2006-11-21 | 2008-07-24 | 주식회사 아모텍 | Chip device |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63217814A (en) * | 1987-03-06 | 1988-09-09 | Murata Mfg Co Ltd | Chip shaped electronic component |
| JPH04340796A (en) * | 1991-05-17 | 1992-11-27 | Mitsubishi Electric Corp | Printed circuit board |
| JPH06216540A (en) * | 1993-01-18 | 1994-08-05 | Nec Corp | Multilayered printed wiring board |
| JPH09121093A (en) * | 1995-10-25 | 1997-05-06 | Tdk Corp | Shield laminated electronic component |
| JPH11204314A (en) * | 1998-01-09 | 1999-07-30 | Murata Mfg Co Ltd | Laminated electronic component array |
| US5952901A (en) * | 1996-11-20 | 1999-09-14 | Alps Electric Co., Ltd. | Laminated electronic component with trimmable parallel electrodes |
-
2000
- 2000-07-25 KR KR1020000042669A patent/KR100332883B1/en not_active IP Right Cessation
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63217814A (en) * | 1987-03-06 | 1988-09-09 | Murata Mfg Co Ltd | Chip shaped electronic component |
| JPH04340796A (en) * | 1991-05-17 | 1992-11-27 | Mitsubishi Electric Corp | Printed circuit board |
| JPH06216540A (en) * | 1993-01-18 | 1994-08-05 | Nec Corp | Multilayered printed wiring board |
| JPH09121093A (en) * | 1995-10-25 | 1997-05-06 | Tdk Corp | Shield laminated electronic component |
| US5952901A (en) * | 1996-11-20 | 1999-09-14 | Alps Electric Co., Ltd. | Laminated electronic component with trimmable parallel electrodes |
| JPH11204314A (en) * | 1998-01-09 | 1999-07-30 | Murata Mfg Co Ltd | Laminated electronic component array |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20020009181A (en) | 2002-02-01 |
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