KR100332646B1 - Bootstrap circuit - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

The present invention relates to a bootstrap circuit.

2. The technical problem of the invention

The read speed is increased by applying a voltage to the gate of the cell within a range that does not stress the cell.

3. Summary of the Solution of the Invention

The present invention provides a first pumping means for pumping a power supply voltage according to a first control signal, voltage detection means for detecting whether the power supply voltage is lower than a reference value according to a second control signal, and the first control signal and the voltage detection. And a second pumping means for pumping the power supply voltage in accordance with the output signal of the means, and a switching means for outputting the voltage pumped in the second pumping means in accordance with a third control signal.

Description

Bootstrap circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bootstrap circuit, and in particular, after a pumping using a first pumping unit according to a read signal, a desired voltage is obtained by pumping using the second pumping unit only when the applied voltage is lower than the reference voltage of the detection circuit. The present invention relates to a bootstrap circuit capable of performing a fast read operation while reducing stress by applying to a gate of a cell.

In the low voltage device, a potential higher than the power supply voltage VCC must be applied to the gate of the cell in order to ensure stable operation and sufficient read margin when reading data of the cell. A bootstrap circuit is needed to generate this high potential.

In the low voltage device, as the potential is lowered, the potential to be applied to the gate of the cell is also lowered. As a result, it is difficult to secure the read speed and the read margin. Therefore, a read pump circuit must be used. . However, when used over a wide voltage range, pump circuits of the same performance always boost too high when the supply voltage is high, stressing the cell's gate. Therefore, conventionally, the pumping capacitor is separated from the bootstrap circuit, which is a read pump circuit, and detects an applied power supply voltage, and when the power supply voltage is low, the pumping efficiency is improved by pumping using all capacitors, and when the power supply voltage is high, the separation is performed. By using only one capacitor among the capacitors, the pumping efficiency is reduced to reduce the stress on the gate of the cell. However, in such a pump circuit, the time point at which pumping starts depends entirely on the time point when the power supply voltage is detected. Therefore, when the power supply voltage is detected late, the delayed pumping time is delayed by the late detected time, and thus the speed at which the boosting voltage is applied to the gate of the cell is reduced. In addition, since it takes time to stably detect the power supply voltage, it is necessary to wait for the detection time before pumping, and the sensing time is required for a certain time for the stable operation of the detection circuit. It is too late to detect, which makes it difficult to implement a fast operation speed.

Accordingly, an object of the present invention is to provide a bootstrap circuit capable of performing a stable and fast read operation.

The present invention for achieving the above object is a first pumping means for pumping a power supply voltage in accordance with a first control signal, voltage detection means for detecting whether the power supply voltage is lower than a reference value in accordance with a second control signal, and the first A second pumping means for pumping the power supply voltage in accordance with one control signal and an output signal of the voltage detecting means, and switching means for outputting a voltage pumped by the second pumping means in accordance with a third control signal. It is characterized by.

1 is a block diagram of a bootstrap circuit in accordance with the present invention.

2 is a detailed circuit diagram of a voltage detector of a bootstrap circuit according to the present invention;

3 is a detailed circuit diagram of a switching unit of the bootstrap circuit according to the present invention;

4 (a) and 4 (b) are output waveform diagrams in the case of the bootstrap circuit according to the present invention.

<Description of the symbols for the main parts of the drawings>

DESCRIPTION OF SYMBOLS 1 First pumping part 2 Voltage detection part

3: second pumping unit 4: switching unit

11 pulse generator 12 latch means

13: NOR gate 14: initialization means

15: voltage detection means

P1 to P3: first to third PMOS transistors

N1 to N10: first to tenth NMOS transistors

I1 to I5: first to fifth inverters

Q1 to Q6: first to sixth nodes

P11 to P13: first to third PMOS transistors

N11 to N14: first to fourth NMOS transistors

Q11 and Q12: first and second node

I11: Inverter

The present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a bootstrap circuit according to the present invention and is configured as follows. The first pumping unit 1 includes a capacitor and pumps the power supply voltage to a potential set according to the read signal ADT using the capacitor. The voltage detector 2 operates according to the inverted chip enable signal CEb, and detects the applied power supply voltage VCC to operate the second pump 3 when it is lower than the detection point. Outputs a signal for The second pumping unit 3 includes a capacitor and pumps the power supply voltage VCC according to the output signal EN and the read signal ADT of the voltage detector 2. The switching unit 4 outputs the voltage pumped by the second pumping unit 3 to the output terminal OUT, that is, the word line, in accordance with the switch enable signal SW_EN.

2 is a detailed circuit diagram of the voltage detection unit of the bootstrap circuit according to the present invention.

The initialization unit 14 including the first to fifth NMOS transistors N1 to N5 is connected between the first to fifth nodes Q1 to Q5 and the ground terminal VSS, and is inverted chip enable signal CEb. ), The potential of the first to fifth nodes Q1 to Q5 is dropped to the ground potential to initialize the circuit. The first PMOS transistor P1 is connected between the power supply terminal and the sixth node Q6 to supply the power supply voltage VCC according to the inverted chip enable signal CEb. The first resistor R1 connected between the sixth node Q6 and the second node Q2 and the ninth NMOS transistor N9 connected between the second node Q2 and the ground terminal VSS have a size thereof. The detection point is determined accordingly. In addition, the tenth NMOS transistor N10 connected between the sixth node Q6 and the third node Q3 and the second resistor R2 connected between the third node Q3 and the ground terminal VSS are also connected. The detection point is determined according to the size. The sixth NMOS transistor N6 operated according to the potential of the second node Q2 is connected between the fourth node Q4 and the eighth NMOS transistor N8, and the eighth NMOS transistor N8 is connected to the sixth and sixth NMOS transistors N8. It is connected between the seventh NMOS transistors N1 and N2 and the ground terminal VSS. The seventh NMOS transistor N7 operated according to the potential of the third node Q3 is connected between the first node Q3 and the eighth NMOS transistor N8. The second PMOS transistor P2 is connected between the first PMOS transistor P1 and the sixth NMOS transistor N6, and is connected between the third PMOS transistor P3 and the gate terminal to be a potential of the fourth node Q4. It is operated according to. The third PMOS transistor P3 is connected between the first PMOS transistor P1 and the seventh NMOS transistor N7, and is connected between the second PMOS transistor P2 and the gate terminal to be a potential of the fourth node Q4. It is operated according to. Up to this point, the voltage detecting means 15 is shown. The first and second inverters I1 and I2 delay the potential of the first node Q1 for a predetermined time. The output signal of the second inverter I2 is transmitted through the transfer gate M1, which is driven by a pulse output from the pulse generator 11. That is, the pulse generated by the pulse generator 11 in response to the inverted chip enable signal CEb is input to the gate side of the NMOS transistor of the transfer gate M1, and is inverted through the third inverter I3 to be a PMOS transistor. It is input to the gate side of and operated. On the other hand, the pulse generator 11 is for generating a pulse in the high state only for a predetermined period when the inverted chip enable signal CEb input from the high state to the low state. The signal transmitted through the transmission gate M1 is latched by the latch means 12 consisting of the fourth and fifth inverters I4 and I5 and then input to one input terminal of the NOR gate 13. The inverted chip enable signal CEb is input to another input terminal of the NOR gate 13. The signal EN combined and output by the NOR gate 13 is input to the second pumping means to determine the operation of the second pumping means.

The driving method of the voltage detector of the bootstrap circuit according to the present invention configured as described above is as follows.

When the inverted chip enable signal CEb is applied in a high state, the first to fifth NMOS transistors N1 to N5 connected to the first to fifth nodes Q1 to Q5 are turned on, and the first to fifth The potential of the five nodes Q1 to Q5 is dropped to the ground potential VSS. The potential of the first node Q1 maintaining the low state is delayed for a predetermined time through the first and second inverters I1 and I2. The low state signal is transmitted through the transfer gate M1 and latched by the latch means 12 formed of the fourth and fifth inverters I4 and I5 to output a high state signal. A high state signal and a high state inverted chip enable signal CEb are input to the NOR gate 13 to output a low state signal. Therefore, the second pumping part cannot be driven.

When the inverted chip enable signal CEb is applied in a low state, a description will be given of the case in which the power supply voltage VCC is applied in an initial state (0V), a state lower than a set value, and a state higher than a set value.

1) When the power supply voltage VCC is applied at 0V

The inverted chip enable signal CEb is applied in a low state to turn off the first to fifth NMOS transistors N1 to N5 connected to the first to fifth nodes Q1 to Q5, and the first PMOS transistor. Turn on (P1). Although the power supply voltage VCC of 0V is supplied through the turned-on first PMOS transistor P1, the voltage of 0V does not change the potential of the first node Q1 as when the circuit is initialized. Therefore, the first node Q1 maintains the potential of the low state. The potential of the first node Q1 maintaining the low state is delayed for a predetermined time through the first and second inverters I1 and I2. The signal in the low state is latched by the latch means 12 made up of the fourth and fifth inverters I4 and I5 through the transfer gate M1 turned on by the pulse generated by the pulse generator 11 to the high state. Output the signal. A high state signal and a low state inverted chip enable signal CEb are input to the NOR gate 13 to output a low state signal. Therefore, the second pumping part cannot be driven.

2) When the power supply voltage VCC is lower than the set value

The inverted chip enable signal CEb is applied in a low state to turn off the first to fifth NMOS transistors N1 to N5 connected to the first to fifth nodes Q1 to Q5, and the first PMOS transistor. Turn on (P1). The power supply voltage VCC is supplied through the turned-on first PMOS transistor P1 to make the potential of the second node Q2 high through the first resistor R1. The sixth, eighth, and ninth NMOS transistors N6, N8, and N9 are turned on by the potential of the second node Q2 in the high state. Accordingly, a path is formed through the sixth and eighth NMOS transistors N6 and N8 to the ground terminal VSS, so that the potential of the fourth node Q4 becomes low. The second and third PMOS transistors P2 and P3 are turned on by the potential of the fourth node Q4 in the low state to supply the power supply voltage VCC, but the sixth and eighth NMOS transistors N6 and N8 The fourth node Q4 remains low because it is passed through the ground terminal VSS. Meanwhile, since the power supply voltage supplied through the tenth NMOS transistor N10 is passed to the ground terminal through the second resistor R2, the potential of the third node Q3 does not turn on the seventh NMOS transistor N7. Therefore, the first node Q1 is kept high. Here, the first resistor R1 and the ninth NMOS transistor N9, and the tenth NMOS transistor N10 and the second resistor R2 may adjust the size of the resistor and the transistor to adjust the current flowing in the corresponding path. . The potential of the first node Q1 in the high state is applied to the transfer gate M1 after a predetermined time delay through the first and second inverters I1 and I2. On the other hand, the transfer gate M1 is driven by a pulse generated by the pulse generator 11 driven by the inverted chip enable signal CEb. That is, the high state signal generated by the pulse generator 11 is applied to the NMOS transistor side of the transfer gate M1, and the signal inverted to the low state through the third inverter I3 is the PMOS of the transfer gate M1. It is applied to the transistor side to drive the transfer gate M1. The signal of the high state applied through the transmission gate M1 is latched by the latch means 12 introduced into the fourth and fifth inverters I4 and I5 so that one input terminal of the NOR gate 13 is in the low state. The inverted chip enable signal CEb of the low state is input to another input terminal of the NOR gate 13 to output a high state signal. The second pumping part is driven by this high state signal.

3) When the power supply voltage VCC is higher than the set value

The inverted chip enable signal CEb is applied in a low state to turn off the first to fifth NMOS transistors N1 to N5 connected to the first to fifth nodes Q1 to Q5, and the first PMOS transistor. Turn on (P1). Since the voltage supplied through the first PMOS transistor P1 is higher than the set value, the voltage is passed to the ground terminal at a time earlier than the time detected by the voltage detecting means 15, and the first node Q1 is turned low. The potential of the first node Q1 maintaining the low state is delayed for a predetermined time through the first and second inverters I1 and I2. The signal in the low state is latched by the latch means 12 made up of the fourth and fifth inverters I4 and I5 through the transfer gate M1 turned on by the pulse generated by the pulse generator 11 to the high state. Output the signal. A high state signal and a low state inverted chip enable signal CEb are input to the NOR gate 13 to output a low state signal. Therefore, the second pumping part cannot be driven.

3 is a detailed circuit diagram of a switching unit of a bootstrap circuit according to the present invention.

The first PMOS transistor P11 is operated according to the potential of the first node Q11 and is connected between the second node Q12 and the output terminal OUT. The second PMOS transistor P12 is operated according to the potential of the second node Q12 and is connected between the first node Q11 and the output terminal OUT. The third and fourth NMOS transistors N13 and N14 maintain the turn-on state by inputting the power supply voltage VCC to the gate terminal, and are always at the potentials of the second and first nodes Q12 and Q11, that is, the first and the first. 2 The voltage supplied through the PMOS transistors P11 and P12 is passed. The first NMOS transistor N11 is operated according to the switch enable signal SW_EN and is connected between the third NMOS transistor N11 and the ground terminal VSS. The second NMOS transistor N12 is operated according to the switch enable signal SW_EN inverted through the inverter I11 and is connected between the fourth NMOS transistor N14 and the ground terminal VSS. The third PMOS transistor P13 is operated according to the potential of the second node Q12 and supplies a voltage (boost voltage) pumped by the second pumping part to the output terminal OUT, that is, the word line.

The driving method of the switch of the bootstrap circuit according to the present invention configured as described above is as follows.

First, when the switch enable signal SW_EN is applied in the low state while the power supply voltage VCC is applied to the gate terminal to always maintain the turn-on state, the third and fourth NMOS transistors N13 and N14 are applied to the first and second NMOS transistors N13 and N14. The NMOS transistor N11 is turned off and inverted to a high state through the inverter I11 to turn on the second NMOS transistor N12. A path is formed through the turned-on fourth and second NMOS transistors N14 and N12 to the ground terminal VSS so that the first node Q11 is turned low. The first PMOS transistor P11 is turned on by the potential of the first node Q11 in the low state to supply the potential of the output terminal OUT to the second node Q12. The potential of the output terminal OUT is a voltage pumped by the first pumping unit. Therefore, since the second node Q12 maintains a high state, the second node Q12 may turn off the third PMOS transistor P13 and thus may not output the voltage pumped by the second pumping unit.

The third and fourth NMOS transistors N13 and N14 are applied to the gate terminal when the switch enable signal SW_EN is applied in a high state while the power supply voltage VCC is applied to the gate terminal to maintain the turn-on state. The N11 is turned on and inverted to a low state through the inverter I11 to turn off the second NMOS transistor N12. A path is formed through the turned-on third and first NMOS transistors N13 and N11 to the ground terminal VSS so that the second node Q12 goes low. The second PMOS transistor P12 is turned on by the potential of the second node Q12 in the low state to supply the potential of the output terminal OUT, and the third PMOS transistor P13 is turned on to pimp the first pumping unit. The supplied voltage is supplied to the output terminal OUT to raise the potential of the output terminal OUT.

4 (a) and 4 (b) are output waveform diagrams of the bootstrap circuit according to the present invention. FIG. 4 (a) shows a case where the power supply voltage is lower than the set value, and FIG. 4 (b). Shows the case where the application is higher than the set value.

As shown in FIG. 4A, when the power supply voltage is lower than the set value, the voltage detector outputs a signal for driving the second pumping unit. According to this signal, the second pumping unit is driven and the voltage supplied to the word line is a voltage obtained by adding the voltage output from the second pumping unit to the voltage output from the first pumping unit.

On the other hand, when the power supply voltage is higher than the set value, as shown in FIG. 4 (b), a signal for driving the second pumping unit is not output from the voltage detector, and thus the voltage supplied to the word line is pumped from the first pumping unit. It becomes a voltage.

As described above, according to the present invention, since it takes relatively little time to select the capacitor used to detect and pump the power supply voltage, it is possible to implement a high read speed and improve the reliability of the device.

Claims (6)

First pumping means for pumping a power supply voltage to an output terminal according to the first control signal; Voltage detection means for receiving the power supply voltage and detecting whether the power supply voltage is lower than a reference voltage according to a second signal; Second pumping means for pumping the power supply voltage in accordance with the first control signal and an output signal of the voltage detection means; And And a switching means for outputting the voltage pumped by the second pumping means to the output terminal according to a third control signal. The method of claim 1, And said first pumping means comprises a capacitor. The method of claim 1, The voltage detection means includes an initialization unit for initializing a circuit according to the second control signal; A voltage detector configured to input a power supply voltage according to the second control signal, compare the power supply voltage with a pumping reference value, and output a result; Latch means for latching an output signal of the voltage detector; And And logic means for outputting a signal for driving the second pumping unit by logically combining the output signal of the latch means and the second control signal. The method of claim 1, The second pumping unit bootstrap circuit, characterized in that it comprises a capacitor. The method of claim 1, The switching means includes a first PMOS transistor connected between the output terminal and a first node; A second PMOS transistor connected between the output node and a second node; A first NMOS transistor connected between the first node and a ground terminal and driven according to the third control signal; A second NMOS transistor connected between the second node and the ground terminal and driven according to the inverted third control signal; And a third PMOS transistor which is driven according to the potential of the first node and supplies a voltage pumped by the second pumping means to the output terminal. The method of claim 5, And the first and second PMOS transistors are cross-connected.