KR100328842B1 - Semiconductor memory apparatus - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device. In the prior art, a sense amplifier is designed to receive a bit line equalizer signal, a precharge signal, and a bit line signal as a gate poly line, which has a large resistance component and a capacitance component. Since the signal transmission characteristic is poor, there is a problem that an error occurs when the sensing operation of the sense amplifier is performed. Accordingly, the present invention enables a cell array, which is a collection of cells that are the minimum units of a memory device, a sense amplifier array for sensing and amplifying a small voltage difference detected by the cell array, and enabling cell data sensing operation of the sense amplifier array unit. A semiconductor memory device having a sense amplifier driver for outputting a sense amplifier driver control signal, wherein a metal line is wired at a predetermined interval on an upper portion of a gate polyline which is a transmission path for the sense amplifier driver control signal of the sense amplifier array. In addition, the predetermined distance between the predetermined sense amplifiers of the sense amplifier array, and then contact the gate polyline and the metal line shunt (shunt) at the separation point to reduce the resistance value and capacitance due to the gate polyline of the sense amplifier It is effective to perform the accurate sensing operation.

Description

Semiconductor memory device {SEMICONDUCTOR MEMORY APPARATUS}

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device capable of improving signal transmission characteristics in a sense amplifier array.

In general, the memory devices of the DRAM are arranged and the sense amplifiers are arranged in accordance with the number of cell arrays for read and write operations of the memory devices. The signal is transmitted from the sense amplifier array to the gate polyline instead of the metal, which will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram illustrating a general semiconductor memory device. As shown in FIG. 1, the cell array 10, which is a collection of cells that are the minimum units of a memory device, and the small voltage difference detected by the cell array 10 are illustrated. A sense amplifier array 13 for sensing and amplifying, and a sense amplifier driver 11, 12 for outputting a sense amplifier drive control signal for enabling cell data sensing operation of the sense amplifier array unit 13; .

Fig. 2 is a detailed circuit diagram of the sense amplifier array 13, and as shown therein, a bit for interrupting connection of the bit lines BL0 and BLB0 with the upper cell array side by the sense amplifier drive control signal BSL. An equalizer section 2 connected between a line connecting section 1 and the bit line connecting section 1 and a sense amplifier 3 to be described later to precharge the bit lines BL0 and BLB0 to a predetermined level of voltage. And a sense amplifier 3 which amplifies and outputs a weak signal input through the bit lines BL0 and BLB0 to a predetermined level, and transmits or outputs an output signal of the sense amplifier 3 to the outside. An input / output line connection unit 4 for receiving a signal and a bit line connection unit 5 for intermittent bit line connection with the lower cell array side by a sense amplifier drive control signal (BSR), Describe the operation.

First, when the sense amplifier driver 11 supplies the sense amplifier driver control signal BSL to 'high', the nMOS transistors N1 and N2 of the bit line connection unit 1 are turned on to turn on the bit line ( The cell array 10 and the sense amplifier 3 are connected to each other via BL0) and BLB0.

The weak signal read from the cell array 10 is applied to the sense amplifier 3 through the NMOS transistors N1, N2 and bit lines BL0, BLB0 of the bit line connection unit 1. And amplified to a predetermined level.

For example, if the read data is 'high', it is pulled up to the level of the boosted voltage CSP, and if the read data is 'low', it is pulled down to the level of the falling voltage CSN.

At this time, when the selection signal of the input line connection unit 4 is supplied with 'high', the n-MOS transistors N8 and N9 are turned on thereby outputting the data sensed through the sense amplifier 3 to the outside. .

When the read data sensing operation of the cell array 10 is terminated through the series of processes as described above, the equalizer signal BLEQ is supplied to the equalizer unit 2 from the sense amplifier driver 11 to 'high' and the enmo transistor is applied. Since the bit lines N3 to N5 are turned on, the bit lines BL0 and BLB0 are precharged to the equalizer voltage VBLR.

Here, since the lower cell array different from the above is connected to the sense amplifier 3 through the bit line connection unit 5 and the bit lines BL1 and BLB1, the sense amplifier 3 may receive data input in the corresponding mode. Sensing and outputting the same as

3 is a diagram showing the layout of the bit line connection unit 1 and the equalizer unit 2, which are indicated by circles in FIG. 2, wherein the bit line connection unit 1 is a gate of active and e gates of a and b. The NMOS transistor N1 of N, and the NMOS transistor N2 of the active gates e and the gates of c and d are configured to operate as a MOS transistor switch of the sense amplifier driving signal BSL.

The equalizer 2 includes an n-MOS transistor NM4 consisting of an active b and a gate and a gate of a, an n-MOS transistor NM5 consisting of an active b and a gate and a gate of a and c, d It consists of an NMOS transistor NM3 consisting of a gate of active and a.

In this case, the gate polylines (A), (B), and (C) used as the gates of the NMOS transistors N1 to N5 have characteristics that are worse in signal transmission than metal lines due to their large resistance and capacitance. The sense amplifier drive control signals BSL, BSR, and BLEQ driving the sense amplifier 3 are applied to the plurality of sense amplifiers 3 with the same gate polylines A, B, and C. In addition, the gate polylines (A), (B), and (C) are designed to be used as gates of the NMOS transistor.

Accordingly, the sense amplifier array 13 transmits the sense amplifier drive control signals BSL, BSR, and BLEQ to the sense amplifiers 3, respectively, with gate signal lines A and B having poor signal characteristics. The time difference between the sense amplifier drive control signals BSL, BSR, and BLEQ arrives due to the fact that the signal is received as (C), and thus a time difference occurs during the sensing operation.

However, in the conventional apparatus operating as described above, the sense amplifier is designed to receive the bit line equalizer signal, the precharge signal, and the bit line signal to the gate polyline, and the gate polyline has a large value of the resistance component and the capacitance component. Therefore, there is a problem that an error occurs when performing a sensing operation of the sense amplifier due to poor signal transmission characteristics.

Accordingly, the present invention devised in view of the above problems divides the gate poly line, which is the sense amplifier drive control signal transmission line of the sense amplifier array, and shunts the gate poly line with the metal line, thereby resisting the capacitance and the capacitance. It is an object of the present invention to provide a semiconductor memory device capable of performing a precise sensing operation by reducing a value.

1 is a block diagram showing a configuration of a conventional semiconductor memory device.

2 is a detailed circuit diagram of a sense amplifier array in FIG.

FIG. 3 shows a layout of a bit line connection unit and an equalizer unit in FIG.

4 is a detailed circuit diagram of a sense amplifier array in the semiconductor memory device of the present invention.

Fig. 5 shows the layout of the bit line connection unit and the equalizer unit in Fig. 4;

FIG. 6 is a view showing a state in which a contact shunt is formed between two sense amplifiers at predetermined intervals in FIG. 4; FIG.

***** Description of the symbols for the main parts of the drawings *****

1, 5: Bit line connection 2: Equalizer

3: Sense amplifier 4: I / O line connection

The present invention for achieving the above object is a cell array which is a collection of cells that are the minimum unit of the memory device, a sense amplifier array for sensing and amplifying the small voltage difference detected by the cell array, the cell of the sense amplifier array unit A semiconductor memory device having a sense amplifier driver for outputting a sense amplifier driver control signal for enabling a data sensing operation, the semiconductor memory device comprising: a predetermined interval on an upper portion of a gate polyline which is a transmission path for the sense amplifier driver control signal of the sense amplifier array; The metal lines are wired, spaced apart between the predetermined sense amplifiers of the sense amplifier array at predetermined intervals, and then shunted by contacting the gate polyline and the metal lines at the separation points.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings, in which the operations and effects of the semiconductor memory device are attached.

The general structure of the semiconductor memory device of the present invention is the same as that of Fig. 1, except that the present invention is based on the sense amplifier drive control signals BSL, BSR, and Sense of the sense amplifier array 13. The metal lines A ', B', and C 'are wired at predetermined intervals on the gate polylines A, B, and C, which are transmission paths for BLEQ, and the sense A predetermined interval is spaced between the predetermined sense amplifiers 3 of the amplifier array 13, and the gate polylines (A), (B), (C) and the metal lines (A '), (B') at the separation points. Shunting by contacting (C ') is different from the conventional method.

Therefore, the general operation of the semiconductor memory device of the present invention is the same as before. 1 and 4, when the sense amplifier driver 11 supplies the sense amplifier drive control signal BSL to 'high', the n-MOS transistor N1 of the bit line connection unit 1 is thereby supplied. ), (N2) is turned on, and the cell array 10 and the sense amplifier 3 are connected through the bit lines BL0 and BLB0.

In this case, the sense amplifier driving control signal BSL is supplied through the metal line A ', thereby reducing the supply delay time.

The weak signal read from the cell array 10 is applied to the sense amplifier 3 through the NMOS transistors N1, N2 and bit lines BL0, BLB0 of the bit line connection unit 1. And amplified to a predetermined level.

For example, when the read data is 'high', it is pulled up to the level of the boosted voltage CSP, and when the read data is 'low', it is pulled down to the level of the falling voltage CSN.

At this time, when the selection signal of the input line connection unit 4 is supplied with 'high', the n-MOS transistors N8 and N9 are turned on thereby outputting the data sensed through the sense amplifier 3 to the outside. .

When the read data sensing operation of the cell array 10 is terminated through the series of processes as described above, the equalizer signal BLEQ is supplied to the equalizer unit 2 from the sense amplifier driver 11 to 'high' and the enmo transistor is applied. Since the bit lines N3 to N5 are turned on, the bit lines BL0 and BLB0 are precharged to the equalizer voltage VBLR.

In this case, the equalizer signal BLEQ is supplied through the metal line B 'to reduce the delay time.

Here, since the lower cell array different from the above is connected to the sense amplifier 3 through the bit line connection unit 5 and the bit lines BL1 and BLB1, the sense amplifier 3 receives data input in the corresponding mode. Sensing and outputting the same as

That is, as shown in FIG. 5, the present invention is a gate polyline (A), (B), (C) which are transmission paths for the sense amplifier drive control signals BSL, BSR, and BLEQ of the sense amplifier array 13. The metal lines A '(B') and (C ') are wired at predetermined intervals on the upper part of the circuit board, and spaced apart from each other between the two sense amplifiers 3 of the sense amplifier array 13 at predetermined intervals. Then, at the separation point, the gate polylines (A), (B), (C) and the metal lines (A ') (B') and (C ') are shunted to the metal lines (A'). By supplying the sense amplifier drive control signals BSL, BSR, and BLEQ through (B ') and (C'), the supply delay time according to the position of the sense amplifier 3 is reduced, so that accurate sensing operation is performed. Will be performed.

At this time, as shown in FIG. 6, the contact shunt is wired apart from two predetermined sense amplifiers 3, and above the storage elements of the cell array 10 of the column line corresponding to the contact shunt. Wire another metal line to use as a power mesh or claw signal line.

As described in detail above, the present invention performs an accurate sensing operation by reducing the resistance value and capacitance caused by the gate polyline of the sense amplifier by shunting from the metal line to the gate polyline in the middle of the sense amplifier array. It can work.

Claims (2)

A cell array, which is a collection of cells that are the minimum units of a memory element, a sense amplifier array that senses and amplifies a small voltage difference sensed by the cell array, and a sense amplifier drive control for enabling cell data sensing operation of the sense amplifier array unit. A semiconductor memory device having a sense amplifier driver for outputting a signal, comprising: wiring a metal line at a predetermined interval on an upper portion of a gate polyline, which is a transmission path for a sense amplifier drive control signal of the sense amplifier array; And a gate polyline and a metal line are contacted and shunted at a predetermined interval after spaced between two predetermined sense amplifiers of the array. 2. The semiconductor memory device according to claim 1, wherein a metal line is wired over the memory elements of the cell array of the column line corresponding to the contact shunt and used as a power mesh or clobal signal line.