KR100328828B1 - Column enable apparatus for column redundancy circuit - Google Patents

Abstract

The present invention relates to a column enable device of a column redundancy circuit. In the related art, it takes a long time because a process of comparing an address and outputting a result is sequentially performed during one clock, and thus, the column enable time. There was a problem with this delay. Accordingly, the present invention includes a pre-address comparison section for comparing a defective address with respect to an external address first inputted by an internal clock signal Yclk1; A post address comparison unit for increasing an address by one by a predetermined time delayed clock Yclk1D of the internal clock signal Yclk1, and comparing a defective address; A defect address storage section for storing an address of a defective memory cell; A comparison result output unit configured to output a comparison result of the sundresser comparison unit and the reardresser comparison unit; The decoder unit is configured to enable a column or a redundancy column designated by the result output from the comparison result output unit. The two types of clocks compare addresses for one clock and output the compared results for the other clock. This has the effect of reducing the enable time.

Description

COLUMN ENABLE APPARATUS FOR COLUMN REDUNDANCY CIRCUIT}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a column redundancy circuit. In particular, two types of clocks allow a defective address to be compared for one clock and a column enable signal to be outputted according to a comparison result for another clock, thereby reducing column enable time. And a column enable device of a column redundancy circuit.

A technique commonly used to remedy defective memory areas due to process or design problems is a redundancy technique, which is divided into row redundancy and column redundancy, and in the present invention, a column is doubled. The redundancy will be described as an example.

In general, the column redundancy circuit includes a fuse to test each memory cell after the manufacture of the memory is completed, and when there is an error, the column redundancy circuit is cut to convert the column selection signal to select the redundancy cell.

In this case, the memory cell is tested by applying row address RA and column address CA in synchronization with row address strobe RAS and column address strobe CAS, respectively. After writing, it is common practice to read the data recorded in the memory cell again and determine whether it matches the first recorded data.

Accordingly, if the data recorded in the memory cell and the data initially recorded match, it is determined that all the memory cells stored in the memory are intact.

FIG. 1 is a block diagram illustrating a column redundancy column enable device of a DRAM according to the prior art. As shown in FIG. 1, an internal clock signal (Yclk1, Yclk2) is incremented by one at an externally input address as shown in FIG. A column address counter section 1; A defect address storage section 2 which stores an address of a defective memory cell; An address comparison section (3) which compares and outputs whether the address output from the column address counter section (1) and the address of the defective address storage section (2) are the same; A column pre-decoder section (4) for outputting a control signal for enabling or disabling the column of addresses output from the address comparison section (3); It consists of a column decoder unit 5 for enabling the column or redundancy column designated by the control signal output from the column pre-decoder unit 4, with reference to the waveform diagram of FIG. The explanation is as follows.

First, the defective address storage section 2 stores the addresses of the defective cells by testing the memory cells, and the column address counter section 1 stores one by one according to the internal clock signals Yclk1 and Yclk2 from externally specified addresses. The address is sequentially increased and output.

Here, the internal clock signals Yclk1 and Yclk2 as shown in Figs. 2B and 2C are output in synchronization with the rising edge of the external clock signal in Fig. 2A, and the external signal designated by the clock signal Yclk1 is externally designated. The address is compared and the result is output. After that, the address is incremented by 1 by the clock signal Yclk2 and compared.

Next, the address comparison section 3 compares the defective address stored in the defective address storage section 2 with the address output from the column address counter section 1, and the result (for example, if the same is the case). If '0' is different, '1' is output.)

Accordingly, the column pre-decoder section 4 disables the designated column because the designated column has a defect in the case of '0' according to the result output from the address comparison section 3, and redundancy is performed. A control signal for enabling the (redundancy) column is output to the column decoder unit 5. FIG.

On the other hand, when the output result is '1', since the designated column is normal, the redundancy column is disabled, and a control signal for enabling the original designated column is output.

Accordingly, the column decoder unit 5 enables the column or the redundancy column designated by the control signal output from the column pre-decoder unit 4.

However, in the related art, it takes a long time because the comparison of the addresses and the output of the results are sequentially performed during one clock, and thus, the column enable time is delayed.

Accordingly, the present invention has been made to solve the above-mentioned conventional problems, and the column enable time is shortened by comparing the addresses for one clock by the two types of clocks and outputting the compared result during the other clocks. It is an object of the present invention to provide a column enable device of a column redundancy circuit.

1 is a block diagram showing the configuration of a column enable device of a column redundancy method of the DRAM according to the prior art.

2 is a waveform diagram of a clock for performing a comparison operation in FIG.

Figure 3 is a block diagram showing the configuration of the column enable device of the column redundancy method according to the present invention.

4 is a waveform diagram of a clock for performing a comparison operation in FIG.

*** Description of the symbols for the main parts of the drawings ***

10: sun address comparison section 10a: column address counter section

10b, 30b: address comparison unit 20: defective address storage unit

30: address comparison section 30a: pre-column address counter section

40: comparison result output section 40a, 40b: transmission gate section

50: decoder section 50a: column free decoder section

50b: column decoder

The present invention for achieving the above object comprises a pre-address comparison unit for comparing whether or not a defective address with respect to the external address first input by the internal clock signal (Yclk1); A post address comparison unit for increasing an address by one by a predetermined time delayed clock Yclk1D of the internal clock signal Yclk1, and comparing a defective address; A defect address storage section for storing an address of a defective memory cell; A comparison result output unit configured to output a comparison result of the sundresser comparison unit and the reardresser comparison unit; And a decoder configured to enable the column or the redundancy column designated by the result output from the comparison result output unit.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 3 is a block diagram showing the configuration of a column redundancy column enable apparatus according to the present invention. As shown in FIG. 3, a comparison is made between a defective address and an external address first inputted by an internal clock signal Yclk1. A pre-address comparison unit 10; An address comparison unit (30) for increasing the address by one by a predetermined time delayed clock (Yclk1D) of the internal clock signal (Yclk1) and comparing whether the address is a defective address; A defect address storage section 20 which stores an address of a defective memory cell; A comparison result output unit 40 for outputting a comparison result between the sundresser comparator 10 and the afterdresser comparator 30; And a decoder unit 50 for enabling the designated column or the redundancy column by the result output from the comparison result output unit 40.

Here, the sun address comparator 10 outputs an address first externally inputted by the internal clock signal Yclk1 through the column address counter 10a to the address comparator 10b as before, and compares the addresses. The unit 10b compares this with the address of the defect address storage unit 20 to compare whether there is a defect.

On the other hand, after the internal clock signal (Yclk1, Yclk2) is generated, the after-address comparison unit 30 is increased by one than the address set in the column address counter (10a) by the clock (Yclk1D, Yclk2D) generated after a predetermined time. A pre-column address counter section 30a which counts by incrementing by one from the address; The address comparator 30b compares the address output from the pre-column address counter 30a with the address of the defective address storage 20 to determine whether there is a defect. The conventional internal clock Yclk1, The defect is compared one clock ahead of the comparison operation by Yclk2).

On the other hand, the comparison result output section 40 is a transmission gate section 40a that is turned on / off by an internal clock (Yclk1) and outputs a comparison result of the line address comparator 10; It consists of a transfer gate portion 40b that is turned on / off by the internal clock Yclk2 and outputs a comparison result of the rear-address comparator 30.

That is, when the external address input first is '000', the column address counter unit 10a outputs '000' to the address comparison unit 10b by the internal clock Yclk1 as shown in FIG. As a result of the comparison, the result of the comparison is output to the decoder unit 50 through the transmission gate 40a of the output unit 40.

In the conventional case, the address is increased by one by the internal clock Yclk2. However, in the present invention, the address 001, which is increased by one than the address set by the column address counter 10a, is set in the pre-column address counter. Then, the internal clock Yclk1D generated after a predetermined time after the generation of the internal clock Yclk1 compares the defects, and the address is incremented by one by the internal clock Yclk2D.

Next, the result of the comparison between the first address comparison unit 10 and the second address comparison unit 20 as described above is output through the comparison result output unit 40, the result of the first external address is the internal clock (Yclk1) Is output through the transfer gate portion 40a which is turned on / off by the < Desc / Clms Page number 6 >

In other words, the comparison result of the first external address is compared by the internal clock (Yclk1) and outputs the results sequentially, as in the prior art, but then the addresses are increased and compared by the internal clocks (Yclk1D, Yclk2D). The result is output by the internal clock (Yclk2). In other words, since the conventional clocks (Yclk1 and Yclk2) both output the result of comparing the defect status and the result thereof, a considerable time is delayed in the column enable. In the present invention, the column enable processing speed is increased by comparing the internal clocks Yclk1D and Yclk2D with the other internal clocks Yclk1 and Yclk2. will be.

Of course, the decoder 50 receiving the comparison result disables the designated column when the designated column has a defect as in the related art, and instead enables the redundant column, and when there is no defect in the designated column, the redundant column. Disables and enables the specified original column so that the result is intact.

As described above, the column enable apparatus of the column redundancy circuit of the present invention can shorten the column enable time by comparing addresses for one clock by two types of clocks and outputting the compared result during the other clock. It is effective.

Claims (3)

1. A column redundancy circuit for repairing a defective memory cell, comprising: a pre-address comparison section for comparing whether an external address first input by an internal clock signal Yclk1 is a defective address; An address comparison unit which compares whether the address is a defective address by increasing the address by one by the clocks Yclk1D and Yclk2D delayed by a predetermined time from the internal clock signals Yclk1 and Yclk2; A comparison result output unit configured to output a comparison result of the sundresser comparison unit and the reardresser comparison unit; And a decoder unit for enabling a column or a redundancy column designated by a result output from the comparison result output unit. 2. The address of claim 1, wherein the backward address comparator is 1 from an address increased by one more than an address set in the column address counter by the clocks Yclk1D and Yclk2D generated after a predetermined time after the internal clock signals Yclk1 and Yclk2 are generated. A pre-column address counter unit for counting by increments; And an address comparing unit which compares an address output from the pre-column address counter unit with a defective address to determine whether there is a defect. 2. The apparatus of claim 1, wherein the comparison result output unit comprises: a transmission gate unit which is turned on / off by an internal clock (Yclk1) and outputs a comparison result of the sun address comparator; A column enable device of a column redundancy circuit, comprising: a transmission gate section which is turned on / off by an internal clock (Yclk2) and outputs a comparison result of a rear-address comparison section.