KR100328595B1 - semiconductor memory device - Google Patents

Abstract

The present invention discloses a word line structure of a highly integrated semiconductor memory device. According to this, the memory cell array is divided evenly into a plurality of sub-memory cell arrays, and the low resistance conductive lines are respectively paralleled to the high resistance word lines by interconnect plugs in the contact holes to reduce the resistance of the high resistance word lines. Low resistance conductive lines are electrically connected to the word lines in an arbitrary sub-memory cell array by interconnecting plugs to properly distribute the resistance of the word lines. Interconnect plugs are alternately arranged on both the left and right sides of an arbitrary sub-memory cell array.

Accordingly, the present invention can reduce the occurrence of defects in the product by suppressing the short circuit of neighboring low resistance lines at the points of the interconnection plugs while using the existing manufacturing process as it is, and achieve high integration of the semiconductor memory device.

Description

Semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having high integration by preventing short circuits of low resistance conductive lines connected to each of them in order to reduce resistance of word lines.

In general, one of the word lines of the word lines of the semiconductor memory device is selected by enabling the corresponding word line driver by an address signal applied from the outside. Therefore, the enable operation of the word line is closely related to the performance of the semiconductor memory device. Wordlines have been made of polysilicon because they act as gate electrodes of transistors in memory cells, which have significant electrical resistance. The resistance of the word line can be reduced by mixing polysilicon with metal silicides such as tungsten silicide.

However, the resulting mixture, usually termed polycide, still has a much greater resistance than the resistance of metals such as aluminum. In addition, the number of memory cells connected to one word line increases with increasing integration and capacity of semiconductor memory devices. Due to the relatively high resistance of the word line and the large number of memory cells on each word line, the word line exhibits significant resistive (R) and capacitive (C) loads, and the accompanying RC signal propagation delay slows the operation of the memory device. .

In view of such a problem, a new word line structure semiconductor memory device has been proposed in which a low resistance metal conductive line is connected in parallel to a high resistance word line to reduce the resistance of the word line. That is, as shown in FIG. 1, the memory cell array 10 in which memory cells (not shown) are arranged is equally divided into two sub memory cell arrays 11 and 13. The word lines 111 of the odd-numbered row and the word lines 112 of the even-numbered row are alternately arranged in parallel with each other while running the sub memory cell arrays 11 and 13, and the word lines 111, All of the word line drivers 20 driving 112 are disposed on the left side of the memory cell array 10. The low resistance conductive lines 113 are connected in parallel to the corresponding word lines 111 to reduce the resistance of the word lines 111, respectively, and the low resistance conductive lines 114 are also respectively connected to the word lines 112. It is connected in parallel to the corresponding word lines 112 to reduce the resistance. Conductive interconnect plugs 31 in contact holes (not shown) located at the left and right ends of the sub-memory cell array 11 so that the conductive lines 113 properly distribute the resistance of the word lines 111, respectively. 33 is electrically connected in parallel to the word lines 111. The conductive lines 114 are likewise electrically connected in parallel to the word lines 112 by interconnecting plugs 32, 34.

Meanwhile, as the word lines 111 and 112 and the conductive lines 113 and 114 are connected by a plurality of interconnecting plugs, the resistance of the word lines 111 and 112 may be reduced. Since the length of the word line is extended due to the increase in the number of contact holes to be filled with a plurality of interconnect plugs, in consideration of the size of the semiconductor memory device, they are usually connected by interconnect plugs at one or two points of the word line.

The conductive lines 113, 114 and the interconnect plugs 31, 32, 33, 34 comprise tungsten and the word lines 111, 112 are high resistance polycrystalline silicon. Or materials such as polysides. The term 'high resistance' is used in reference to the resistance of a low resistance line, and in an absolute sense does not mean that the high resistance line has a high resistance.

Although not illustrated in the drawings for convenience of description, it is obvious to those skilled in the art that bit lines are arranged side by side in a direction perpendicular to word lines, and that each memory cell is disposed at an intersection of the word line and the bit line. It is true.

In the semiconductor memory device having such a word line structure, the word lines 111 and the conductive lines 113 are connected in parallel by interconnection plugs 31 and 33, and the word lines 112 and the conductive lines are electrically connected. Since the lines 114 are connected in parallel by the interconnect plugs 32 and 34, the resistance of the word lines 112 is reduced and further the RC transfer delay of the semiconductor memory device is improved.

However, as illustrated in FIG. 2, the conductive lines 113 and 114 are parallel to the same line of the first and second word lines 111 and 112 with an interlayer insulating film (not shown) interposed therebetween. Are wired. The widths of the conductive lines 113 and 114 are located between the sub memory cell arrays 11 and 13 to provide a mask alignment margin in the fabrication process for highly integrated semiconductor memory devices. Locally widen at the point of interconnecting plugs 33, 34 in a contact hole (not shown) and thus adjacent conductive lines 113, 114 at the point of interconnecting plugs 33, 34. The gap G1 is smaller than the gap G between adjacent conductive lines 113 and 114 at most other points. As the semiconductor memory device is highly integrated, the contact holes to which the interconnect plugs 33 and 34 are filled are relatively large, even though the width and the gap G of the conductive lines 113 and 114 are reduced. It is because it is limited and the space | interval G1 is relatively limited.

Furthermore, since the interconnect plugs 33, 34 are all arranged in line, the gap G1 of the conductive lines 113, 114 at the point of the interconnect plugs 33, 34 is reduced. At most other points, it is much narrower than the gap G of the conductive lines 113, 114, which results in a shortage of the gap of the conductive lines 113, 114. As a result, a short circuit between adjacent conductive lines 113 and 114 is likely to occur during the manufacturing process of the highly integrated semiconductor memory device, and furthermore, a high defect rate of the product has a high level of integration of the semiconductor memory device.

In order to improve this, a semiconductor memory device having a modified word line structure has been proposed. That is, as shown in FIG. 3, the interconnecting plugs 33 and 34 are arranged in a zigzag proximity to each other, unlike the arrangement in FIG. 1, and the interconnecting plugs 31 and 32 are also in contact with each other. Are placed in zigzag proximity

In the semiconductor memory device having the word line structure as described above, similarly to the semiconductor memory device of FIG. 1, the resistances of the word lines 111 and 112 are reduced, and the RC transfer delay of the semiconductor memory device is improved.

In addition, the conductive lines 113 and 114 are disposed on the same line of the word lines 111 and 112 with an interlayer insulating film (not shown) interposed therebetween, as shown in FIG. 4, and contact holes. Interconnect plugs 33, 34 in the field (not shown) are zigzag in proximity. Thus, in the case of highly integrated semiconductor memory devices, the widths of the conductive lines 113, 114 are locally wide at the points of the interconnect plugs 33, 34 and the interconnect plugs 33, 34. The distance G2 between the neighboring conductive lines 113 and 114 at the point of is smaller than the distance G between the neighboring conductive lines 113 and 114 at most other points. However, the gap G2 becomes considerably wider than the gap G1 of FIG. 1.

However, even though the interconnecting plugs 33, 34 are arranged in a zigzag arrangement, they are closely spaced so that the distance between the adjacent conductive lines 113, 114 at the point of the interconnecting plugs 33, 34 is reduced. G3) is narrow, which still results in lack of spacing of the conductive lines 113, 114. As a result, short circuits of the conductive lines 113 and 114 are likely to occur during the fabrication process of the highly integrated semiconductor memory device, and further, the defect rate of the product is high, thereby limiting the high integration of the semiconductor memory device.

In order to solve this problem, the gap G3 must be sufficiently secured, which requires the expansion of the gap between the contact holes to be filled with the interconnect plugs 33 and 34 and further, the length of the word line. As a result, the resistance of the word line increases, the RC propagation delay increases, and it is difficult to reduce the size of the highly integrated semiconductor memory device.

At present, there is an urgent need for a word line structure of a highly integrated semiconductor memory device capable of preventing short circuits of parallel connected low-resistance conductive lines and improving good yields in order to reduce the resistance of the word lines.

Accordingly, an object of the present invention is to provide a semiconductor memory device capable of preventing short circuits of low resistance lines connected in parallel in order to reduce resistance of word lines.

Another object of the present invention is to provide a semiconductor memory device capable of achieving high integration of the semiconductor memory device.

1 is a schematic diagram showing a word line of a conventional semiconductor memory device.

2 is a layout diagram illustrating a word line of FIG. 1.

3 is a schematic diagram showing a modified word line of a semiconductor memory device according to the prior art;

4 is a layout diagram illustrating a word line of FIG. 3.

5 is a schematic diagram showing a word line of a semiconductor memory device according to the present invention.

6 is a layout diagram illustrating a word line of FIG. 5.

The semiconductor memory device according to the present invention for achieving the above object is

A memory cell array having sub memory cell arrays in which memory cells are arrayed;

First and second word lines arranged side by side alternately with each other in the sub memory cell arrays;

First and second conductive lines each having a resistance lower than that of the first and second word lines and reducing the resistance of the first and second word lines, respectively; And

And first and second interconnection plugs connecting the first and second word lines and the first and second conductive lines in parallel, respectively.

First and second interconnection plugs connected to one end of the first and second conductive lines may be alternately disposed at left and right sides of a desired sub memory cell array among the sub memory cell arrays.

Preferably, the first and second interconnection plugs disposed on the left and right sides of the sub memory cell array are arranged in a line, respectively.

Accordingly, the present invention can reduce the occurrence rate of defects of the product by reducing the occurrence of short circuits of the adjacent first and second conductive lines at the points of the interconnection plugs while using the existing manufacturing process as it is, and achieve high integration of the semiconductor memory device. .

Hereinafter, a semiconductor memory device according to the present invention will be described in detail with reference to the accompanying drawings. The same code | symbol is attached | subjected to the part of the same structure and the same operation as the conventional part.

5 is a schematic diagram showing a word line of a semiconductor memory device according to the present invention.

As shown in FIG. 5, the memory cell array 50 in which memory cells (not shown) are arrayed includes sub memory cell arrays 51a, 51b, 51c, 51d, 51e, It is equally divided into 51f and 51g. The first word lines 511 of the odd-numbered row and the second word lines 512 of the even-numbered row are divided into the sub memory cell arrays 51a, 51b, 51c, 51d, and 51e. All of the word line drivers 20 driving the first, second word lines 511 and 512 are arranged side by side alternately with each other. Is placed on the left side of the. Low resistance first and second conductive lines 513 are respectively connected in parallel to the first word lines 511 to reduce the resistance of the corresponding first word lines 511. The second conductive lines 514 are also respectively connected in parallel to the second word lines 512 to reduce the resistance of the corresponding second word lines 512. In order to properly distribute the resistances of the first word lines 511, the first conductive lines 513 may have contact holes at the left end of the sub memory cell array 51 a and the right end of the sub memory cell array 51 f. (Not shown) electrically connected in parallel to the first word lines 511 by first interconnect plugs 31, 33. Second conductive lines 514 at the left end of the sub-memory cell array 51a and at the left end of the sub-memory cell array 51f to properly distribute the resistance of the second word lines 512, respectively. The connection plugs 32 and 34 are electrically connected in parallel to the second word lines 512.

Here, the conductive lines 513 and 514 and the interconnecting plugs 31, 32, 33 and 34 include tungsten, and the word lines 511 and 512 are high. Materials such as resistive polycrystalline silicon or polysides. Of course, the conductive lines 513 and 514 may be made of a metal layer such as aluminum. The term 'high resistance' is used in connection with the resistance of the conductive line, and in an absolute sense does not mean that the high resistance line has a high resistance.

Although not illustrated in the drawings for convenience of description, it is obvious to those skilled in the art that bit lines are arranged side by side in a direction perpendicular to word lines, and that each memory cell is disposed at an intersection of the word line and the bit line. It is true.

In the semiconductor memory device having the word line structure as described above, the resistance of the first and second word lines 511 and 512 is reduced, and the RC transfer delay of the semiconductor memory device is improved.

A layout diagram of area A of FIG. 5 is shown in FIG. 6. That is, the first and second conductive lines 513 and 514 are disposed on the same line of the first and second word lines 511 and 512 with an interlayer insulating film (not shown) therebetween. All of the first interconnect plugs 33 in the contact holes (not shown) are disposed on the right side of the sub memory cell array 51f, and the second interconnect plugs 34 are all sub memory cell array 51f. Is placed on the left side of the. That is, the first and second interconnection plugs 33 and 34 are disposed in a zigzag fashion with the sub memory cell array 51f interposed therebetween.

Also, the width of the first and second conductive lines 513, 514 is locally wide at the point of the interconnect plugs 33, 34 and at the point of the interconnect plugs 33, 34. The gap G4 of the neighboring conductive lines 513 and 514 is smaller than the gap G between the neighboring conductive lines 513 and 514 at most other points.

Therefore, in the case of the highly integrated semiconductor memory device of the present invention, the interconnection plugs 33 and 34 are not required to be considered at all while maintaining the interval G4 equal to the interval G2 of FIG. 4. The shortage of the gap between the conductive lines 513 and 514 due to the narrow gap between the adjacent conductive lines 513 and 514 at the point of) can be eliminated and furthermore, high integration can be achieved.

As described above, according to the present invention, a memory cell array is divided into a plurality of sub-memory cell arrays, and low-resistance conductive lines are respectively connected to interconnecting plugs in contact holes to reduce resistance of high-resistance word lines. Connected in parallel to the high resistance word lines, and the low resistance conductive lines are electrically connected to the word lines in an arbitrary sub-memory cell array by interconnect plugs in order to properly distribute the resistance of the word lines. Interconnect plugs are alternately arranged on both the left and right sides of an arbitrary sub-memory cell array.

Accordingly, the present invention can reduce the occurrence of defects in the product by suppressing the short circuit of neighboring low resistance lines at the points of the interconnection plugs while using the existing manufacturing process as it is, and achieve high integration of the semiconductor memory device.

On the other hand, the present invention is described based on the preferred example shown in the drawings, but not limited to this and various modifications and improvements are possible by those skilled in the art to which the present invention belongs without departing from the spirit of the invention. Of course.

Claims (2)

A memory cell array having sub memory cell arrays in which memory cells are arrayed; First and second word lines arranged side by side alternately with each other in the sub memory cell arrays; First and second conductive lines having a resistance lower than that of the first and second word lines and disposed in a different layer from the first and second word lines, for reducing the resistance of the first and second word lines, respectively; And First and second interconnection plugs respectively connected in parallel to the first and second word lines and the first and second conductive lines through a contact hole, First and second interconnection plugs connected to one end of the first and second conductive lines are alternately disposed at left and right sides of a desired sub memory cell array among the sub memory cell arrays, respectively; . The semiconductor memory device of claim 1, wherein the first and second interconnection plugs disposed on the left and right sides of the sub memory cell array are disposed in a line.