KR100324336B1 - Level shift initialize circuit for memory device - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift initialization circuit of a memory device. In the related art, when a level shifter is operated when a level of an initial low potential voltage does not become a normal level when powering up a memory device at high speed, There was a problem that could not be delivered. Therefore, the present invention includes a switching element in the level shifter, and configures a switching control unit to control the on / off operation of the switching element, and if the level of the initial low potential voltage does not reach the normal level, the switching element is cut off so that the level shifter When the level of the low potential voltage reaches the normal level, the switching element is turned on so as to level shift the high potential voltage to prevent malfunction.

Description

Level shift initialization circuit of a memory device {LEVEL SHIFT INITIALIZE CIRCUIT FOR MEMORY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a level shift initialization circuit of a memory element for reliably holding the initialization of the level shifter portion when the initial power is applied to the memory element. In particular, the present invention relates to a power failure due to an error in the initialization setting of the level shifter when the initial power is applied. A level shift initialization circuit of a memory element is provided to prevent occurrence of up-up defects.

FIG. 1 is a detailed view illustrating a level shift initialization circuit of a conventional memory device. As shown in FIG. 1, the gates of the first and second PMOS transistors P1 and P2 connected to a source voltage terminal are respectively referred to. 2, respectively connected to the drains of the first PMOS transistors P2 and P1, and the first and second NMOS transistors N1 (to the drains of the first and second PMOS transistors P1 and P2). N2) is connected in series, and the cathode of the first inverter INV1 for inverting the input signal is connected to the source of the first NMOS transistor N1 and simultaneously connected to the gate of the second NMOS transistor N2 with the source grounded. The common drain of the second PMOS transistor P2 and the second NMOS transistor N2 is connected to an output terminal OUT through a second inverter INV2, and the first NMOS transistor N1. The gate of is connected to the low potential input terminal LOW_VDD and is configured.

Looking at the prior art configured as described above is as follows.

When the input signal In of the low state comes before the initial power is applied to the memory device, the first inverter INV1 converts the signal into the high state, so that the source and the second NMOS of the first NMOS transistor N1 are changed. Commonly supplied to the gate of the transistor N2.

Then, the first NMOS transistor N1 is turned off and the second NMOS transistor N2 is turned on so that the node A level shifts the low potential voltage LOW_VDD.

Then, when an initial power is applied to the memory device, when a high state input signal In comes, the first inverter INV1 converts the signal into a low state, so that the source and the second yen of the first NMOS transistor N1 are changed. Commonly supplied to the gate of the MOS transistor N2.

Then, the second NMOS transistor N2 is turned off, and the first NMOS transistor N1 is turned on because it is the same as the gate and the source.

As the first NMOS transistor N1 is turned on, a low signal is applied to the gate of the second PMOS transistor P2 to turn on the second PMOS transistor P2 so that the node A has a high potential voltage HIGH_VDD. Level shift.

However, in the prior art as described above, when the level shifter is used at power-up at a high speed in a memory device, the level shifter operates before the initial low potential voltage LOW_VDD reaches a normal level, thereby causing a normal high potential at node A. There is a problem that a malfunction occurs because the voltage (HIGH_VDD) is not delivered.

Accordingly, an object of the present invention for solving the conventional problems as described above is to prevent the level shifter from malfunctioning until the initial low potential voltage reaches a constant level, thereby initializing the level shift of the memory device. In providing a circuit.

1 is a detailed diagram of a level shift initialization circuit of a conventional memory element.

Fig. 2 is a detailed diagram of the level shift initialization circuit of the memory device of the present invention.

***** Explanation of symbols for the main parts of the drawing *****

C: Capacitor INV: Inverter

N: NMOS transistor P: PMOS transistor

10: switch control unit 11: reference level adjusting unit

12: signal generator

The present invention for achieving the above object includes a switching element for controlling the operation of the level shifter, and a switching control unit for controlling the on / off operation of the switching element, so that the level of the low potential voltage at the initial power-up Until the normal level is reached, the operation of the level shifter is blocked so as not to malfunction.

Hereinafter, with reference to the accompanying drawings in detail as follows.

FIG. 2 is a detailed diagram of a level shift initialization circuit of a memory device according to an embodiment of the present invention. As shown in FIG. 2, the gate of the first PMOS transistor P1 having a source connected to a power supply voltage terminal is the second PMOS transistor ( A gate of the second PMOS transistor P2 is connected to a drain of the first PMOS transistor P1 and simultaneously connected to a source of the switching device P3. The first and second NMOS transistors N1 and N2 are connected in series to the drains of the second PMOS transistors P1 and P2, and the cathode of the first inverter INV1 for inverting the input signal is connected to the first yen. The source of the MOS transistor N1 and the drain of the switching element P3 are connected to the gate of the second NMOS transistor N2 which is connected to the ground in common, and is connected to the second PMOS transistor P2. Common drain of the second NMOS transistor N2 Is connected to the output terminal OUT through the second inverter INV2, the gate of the first NMOS transistor N1 is connected to the low potential input terminal LOW_VDD, and the low potential voltage LOW_VDD is initially at a predetermined level. A switch control unit 10 is provided connected to the gate of the switching element P3 to provide a switching control signal for turning off the operation of the level shifter before reaching.

The switch control unit 10 includes a reference level adjusting unit 11 for adjusting the reference level of the low potential voltage, and a signal generator 12 for outputting a switching control signal according to the adjusted level. In the level adjuster 11, a fourth PMOS transistor P4 and a fifth PMOS transistor P5 having a gate and a drain connected in common are sequentially connected to a low potential voltage terminal LOW_VDD, and the fifth PMOS transistor is connected. Capacitor C1 is connected between P5 and a ground side, and the signal generator 12 has a sixth PMOS transistor P6 and a third NMOS transistor N3 at the high potential voltage terminal HIGH_VDD. ) Are sequentially connected, and the gates of the sixth PMOS transistor P6 and the third NMOS transistor N3 are commonly connected to the connection point of the fifth PMOS transistor P5 and the capacitor, PMOS transistor P6 and third NMOS transistor ( The connection point of N3) is configured to generate a switching control signal via the third inverter INV3.

Referring to the operation and effect of the present invention configured as described in detail as follows.

When the initial power is applied to the memory device, when the high state input signal In comes, the first inverter INV1 converts the signal to the low state, so that the source and the second NMOS of the first NMOS transistor N1 are changed. The gate is supplied to the gate of the transistor N2 and simultaneously supplied to the gate of the second NMOS transistor N2.

At this time, when the level of the low potential voltage LOW_VDD dropped by 2V _T through the fourth PMOS transistor P4 and the fifth PMOS transistor P5 of the switching controller 10 becomes the normal level, the sixth PMOS Transistor P6 is turned on and third NMOS transistor N3 is turned off.

As the sixth PMOS transistor P6 is turned on, the second PMOS transistor P2 is turned on by a low signal supplied to its drain.

Therefore, the node A level shifts the high potential voltage HIGH_VDD supplied from the high potential voltage terminal.

When the initial power is applied to the memory device, the level of the low potential voltage LOW_VDD does not reach the normal level through the fourth PMOS transistor P4 and the fifth PMOS transistor P5 of the switching controller 10. Otherwise, as the sixth PMOS transistor P6 is turned off and the third NMOS transistor N3 is turned on, the low potential voltage is supplied to the input side of the third inverter INV3.

As the third inverter INV3 inverts the low potential voltage to a high potential voltage and supplies it to the gate of the switching device P3, the switching device P3 is turned off.

As such, when the level of the low potential voltage LOW_VDD does not reach the normal level, the switching device P3 is turned off so that the high potential voltage is not transmitted to the node A.

Then, before the level of the low potential voltage LOW_VDD reaches the normal level, the level shifter operates to prevent the malfunction caused by the failure of the normal high potential voltage being transmitted to the node A.

The reference level adjusting unit 11 of the switching control unit 10 adjusts the level of the low potential voltage LOW_VDD by the fourth and fifth PMOS transistors P4 and P5. If it is not reached, another transistor may be added or reduced to adjust to the most suitable level, or the capacitor C1 may be adjusted to change.

As described in detail above, the present invention prevents the level shifter from operating when the level of the low potential voltage does not reach the normal level when the initial power is applied to the memory device, and when the level of the low potential voltage reaches the normal level. By operating the level shifter, it is possible to securely hold the initial setting value to prevent the occurrence of defects during power-up.

Claims (5)

A gate of a first PMOS transistor having a source connected to a power supply voltage terminal is connected to a drain of the second PMOS transistor, and a gate of the second PMOS transistor is connected to a drain of the first PMOS transistor and simultaneously switched. The first and second NMOS transistors are connected in series with the source of the device, and the first and second NMOS transistors are connected in series with the drains of the first and second PMOS transistors, and the cathode of the first inverter for inverting the input signal is the source of the first NMOS transistor. A common drain of the second PMOS transistor and the second NMOS transistor are connected to the gate of the second NMOS transistor which is connected to the drain of the switching element and the source is grounded. The gate of the first NMOS transistor is connected to a low potential input terminal, and initially the low potential voltage reaches a predetermined level. A switch control unit for providing a signal for turning off the operation of the level shifter before reaching the initialization level shift in the memory element, characterized in that configured is connected to the gate of the switching element in the circuit. 2. The level shift initialization of the memory device according to claim 1, wherein the switching controller includes a reference level adjusting unit for adjusting a reference level of the low potential voltage, and a signal generator for outputting a switching control signal according to the adjusted level. Circuit. The level shift initialization circuit of claim 2, wherein the reference level adjusting unit is configured by sequentially connecting a PMOS transistor and a capacitor having a common gate and drain connected to a low potential voltage terminal in series. 4. The level shift initialization circuit of claim 3, wherein the reference level adjustment unit is adjustable by increasing or decreasing the number of MOS transistors. 2. The level shift initialization circuit of claim 1, wherein the switching element is a MOS transistor.