KR100324314B1 - Sign / Cosine Function Generation Circuit - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sine / cosine function generation circuit. In the related art, since the sampling value of the sine / cosine function is stored in the ROM as it is, the size of the ROM is increased and the number of gates is increased, thereby increasing power consumption. Accordingly, the present invention provides a cosine ROM for storing a difference value between a sampled cosine of 0 to 90 degrees and a previous sampled cosine as two bits of data; A first restoring unit receiving the stored data from the cosine ROM and restoring the original sampling value; A first flip-flop that receives the recovered sampling value from the first restoring unit and synchronizes it with a clock; A sign ROM storing a difference value between a sampled sine value of 0 to 90 degrees and a previously sampled sine value as 2 bits of data; A second restoring unit receiving data from the sign ROM and restoring the data to an original sampled sign value; A second flip-flop that receives the recovered sampling value from the second restoring unit and synchronizes it with a clock; A first multiplexer which receives data from the first and second flip-flops and changes the cosine function value according to the phase by a predetermined control signal; A first compensator for receiving data from the first multiplexer and determining a sign according to a phase to compensate a function value; A third flip-flop that receives data from the compensator and synchronizes with a clock signal to output the data; A second multiplexer which receives data from the first and second flip-flops and changes a function value wrapped according to a phase by a predetermined control signal; A second compensator for receiving data from the second multiplexer and determining a sign according to a phase to compensate a function value; A fourth flip-flop that receives data from the second compensator and synchronizes the data by a clock signal; It is composed of a control unit that controls each unit as a whole. Instead of storing the sampled cosine / sine function value of 0 to 90 degrees as 9-bit data, the difference value with all sampling values is obtained and the difference value is converted into 2-bit data. Storing it in a ROM can reduce the size of the chip by reducing the size of the ROM.

Description

Sign / Cosine Function Generation Circuit

The present invention relates to a sign (SIN) / cosine (COS) function generating circuit, in particular when the value between 0 ~ 90 degrees in the ROM using the symmetry and similarity of the sign (SIN) and cosine (COS) The present invention relates to a SIN / COS function generation circuit capable of reducing the size of the chip by storing only the difference value.

As shown in Fig. 1, in order to create a sign (SIN) and a cosine (COS) function in a conventional TV encoder, the sign (CIN) / cosine (COS) function values of 0 to 90 degrees are stored in a table in ROM, and then It is configured to read the value of the ROM while increasing the value to make the SIN / COS function using the similarity and symmetry of the sign and cosine.

FIG. 2 is a block diagram showing a configuration of a conventional sine / cosine function generating circuit. As shown therein, a cosine rom 10 storing a sampled SIN value of 0 to 90 degrees as 9 bits of data is shown in FIG. and; A first flip-flop 11 for receiving data of the cosine rom 10 and synchronizing it; A sign ROM 15 for storing a sampled sign (SIN) value of 0 to 90 degrees as 9 bits of data; A second flip-flop 16 for receiving data from the sign ROM 15 and synchronizing it; A first multiplexer (12) for receiving data from the first and second flip-flops (11) and (16) and changing a cosine (COS) function value according to a phase by a predetermined control signal; A compensator (13) for receiving data from the first multiplexer (12) and determining a sign according to a phase to compensate a function value; A third flip-flop (14) for receiving data from the compensator (13) and synchronizing with a clock signal to output the data; A second multiplexer (17) for receiving data from the first and second flip-flops (11) and (16) and changing a sign function value according to a phase according to a predetermined control signal; A compensator (18) for receiving data from the second multiplexer (17) and determining a sign according to a phase to compensate for a function value; A fourth flip-flop 19 which receives data from the compensator 18 and outputs the data in synchronization with a clock signal; The controller 20 is configured to collectively control the respective units. The operation of the conventional apparatus will be described with reference to FIGS. 3 and 4.

First, the cosine (COS) and the sign (SIN) are sampled with 512 pieces of 9-bit data at 0 to 90 degrees, and stored in the cosine ROM 10 and the sign ROM 15, respectively.

In this case, the cosine ROM 10 and the sign ROM 15 have a size of 512 × 9, and the address for reading the ROMs 10 and 15 is composed of 9 bits. Data of the sign ROM 15 is sequentially read by an address generated by the controller 20 to be described later, and the address is increased by one.

Thereafter, the first and second flip-flops 11 and 16 synchronize the data read from the cosine rom 10 and the sine rom 15 every clock so as to synchronize the first and second multiplexers 12, Output to (17).

Then, the first and second multiplexers 12 and 17 receive the synchronized data, respectively, and cosine / SIN according to a phase by a predetermined control signal of the controller 20 to be described later. Change the value.

In this case, referring to FIGS. 3 and 4, the functions of the first and second multiplexers 12 and 17 will not be described. The cosine (SOS) value and the sign (SIN) value are not changed between 0 and 90 degrees. The control signal ctrl1 of the controller 20 has a value of '0' so that the first and second multiplexers 12 and 17 select the B input terminal, and at 90 to 180 degrees, the cosine (COS) And sign (SIN) value is changed and the control signal (ctrl1) has a value of '1' so that the first and second multiplexers 12, 17 select the A input terminal, between 180 ~ 270 degrees The values of the cosine (COS) and the sign (SIN) are not changed, and the control signal ctrl1 has a value of '0', and the first and second multiplexers 12 and 17 select the B input terminal, and 270 Between ~ 360 degrees, the cosine (COS) and the sign (SIN) value is changed and the control signal (ctrl1) has a value of '1' so that the first and second multiplexers 12, 17, A input terminal Select.

When the sign is determined according to the phases of the cosine (COS) and the sign (SIN) respectively output from the first and second multiplexers 12 and 17, the first and second compensators 13, It is entered in 18 and compensated.

That is, the first and second compensators 13 and 18 have a cosine (COS) and a sign (SIN) value of '+' between 0 and 90 degrees, and the control signals (ctrl2) and (ctrl3) are All of them are '0', Cosine value is '-' between 90 and 180 degrees, and SIN value is '+', and control signals (ctrl2) and (ctrl3) are '1' and '0'. ', Cosine (SOS) and Sign (SIN) are'-'between 180 and 270 degrees, and control signals (ctrl2) and (ctrl3) are all' 1 ', and between 270 and 360 degrees The COS value is '+', the SIN value is '-', and the control signals ctrl2 and ctrl3 are '0' and '1'.

Thereafter, the outputs of the first and second compensators 13 and 18 are synchronized with the cosine (COS) by the clock signals in the third and fourth flip-flops 14 and 19, respectively. The value of the function SIN) is output as shown in Figs. 3 (a) and 3 (b).

However, the conventional apparatus operating as described above has a problem in that since the sampling value of the sine / cosine function is stored in the ROM as it is, the size of the ROM is increased and the number of gates is increased, thereby increasing power consumption.

Therefore, the present invention devised in view of the above problems uses only the symmetry and similarity of the sign and cosine to store only the difference when storing a value between 0 and 90 degrees in the ROM so that the size of the chip can be reduced. The purpose is to provide a sign / cosine function generation circuit.

Figure 1 shows the configuration of a ROM and a data storage method for a conventional sine / cosine function generation circuit.

Figure 2 is a block diagram showing the configuration of a conventional sine / cosine function generation circuit.

3 is a final output waveform diagram in FIG. 2;

FIG. 4 is a truth table of control signals of a control part in FIG. 2; FIG.

Figure 5 shows the configuration of the ROM for the sine / cosine function generation circuit of the present invention and a data storage method.

Figure 6 is a block diagram showing the configuration of the present invention sign / cosine function generation circuit.

Fig. 7 is a final output waveform diagram in Fig. 5;

FIG. 8 is a truth table of control signals of a controller in FIG. 5; FIG.

***** Description of the symbols for the main parts of the drawings *****

11,14,16,19: Flip-flop 12,17,202,402: Multiplexer

13, 18: Compensation part 100: Cosine ROM

200,400: Restorer 201,401: Register

203: Subtractor 403: Adder

500: control unit

The present invention for achieving the above object is a cosine ROM for storing the difference between the sampled cosine of 0 ~ 90 degrees and the previous sampled cosine value as two bits of data; A first restoring unit receiving the stored data from the cosine ROM and restoring the original sampling value; A first flip-flop that receives the recovered sampling value from the first restoring unit and synchronizes it with a clock; A sign ROM storing a difference value between a sampled sine value of 0 to 90 degrees and a previously sampled sine value as 2 bits of data; A second restoring unit receiving data from the sign ROM and restoring the data to an original sampled sign value; A second flip-flop that receives the recovered sampling value from the second restoring unit and synchronizes it with a clock; A first multiplexer which receives data from the first and second flip-flops and changes the cosine function value according to the phase by a predetermined control signal; A first compensator for receiving data from the first multiplexer and determining a sign according to a phase to compensate a function value; A third flip-flop that receives data from the first compensator and synchronizes with a clock signal to output the data; A second multiplexer which receives data from the first and second flip-flops and changes a function value wrapped according to a phase by a predetermined control signal; A second compensator for receiving data from the second multiplexer and determining a sign according to a phase to compensate a function value; A fourth flip-flop that receives data from the second compensator and synchronizes the data by a clock signal; Characterized in that it comprises a control unit for the overall control of each unit.

Hereinafter, with reference to the accompanying drawings, the operation and effects of an embodiment of a sine / cosine function generation circuit according to the present invention will be described.

FIG. 6 is a block diagram showing the configuration of the present invention. The present invention illustrates a block diagram showing the structure of the present invention. The difference between the sampled cosine (COS) and the sampled cosine (COS) of 0 to 90 degrees is shown in FIG. A cosine rom 100 storing 2 bits of data; A first restoring unit (200) for receiving the stored data from the cosine rom (100) and restoring the original sampling value; A first flip-flop (11) which receives the recovered sampling value from the first restoring unit (200) and synchronizes it with a clock; A sign ROM 300 for storing a difference value between a sampled sine value of 0 to 90 degrees and a previously sampled sine value as two bits of data; A second restoring unit (400) for receiving data from the sign ROM (300) and restoring it to an original sampled sign (SIN) value; A second flip-flop (16) which receives the recovered sampling value from the second restoring unit (400) and synchronizes it with a clock; A first multiplexer (12) for receiving data from the first and second flip-flops (11) and (16) and changing a cosine (COS) function value according to a phase by a predetermined control signal; A first compensator (13) for receiving data from the first multiplexer (12) and determining a sign according to a phase to compensate a function value; A third flip-flop 14 which receives data from the first compensator 13 and outputs the data in synchronization with a clock signal; A second multiplexer (17) for receiving data from the first and second flip-flops (11) and (16) and changing a sign function value according to a phase according to a predetermined control signal; A second compensator (18) for receiving data from the second multiplexer (17) and determining a sign according to a phase to compensate for a function value; A fourth flip-flop (19) for receiving data from the second compensator (18) and synchronously outputting the data by a clock signal; The controller 500 is configured to collectively control each unit.

The first restoring unit 200 includes: a first register 201 storing an initial value '511' of a cosine (COS); A third multiplexer (202) for receiving the initial value and the previous sampling value of the first register (201) and multiplying them by a predetermined control signal; And a subtractor 203 which receives the multiplexed value of the third multiplexer 202 and the cosine (COS) value of the cosine ROM 100 and subtracts it to restore the original sampling value.

The second restoring unit 400 includes a second register 401 for storing an initial value '0' of the sign SIN; A fourth multiplexer 402 for receiving the initial value and the previous sampling value of the second register 401 and multiplying them by a predetermined control signal; And an adder 403 configured to receive the multi-transmitted value of the fourth multiplexer 402 and the sign (SIN) of the sign ROM 300, add the received signal, and restore the original sampling value. The operation of the will be described.

First, the cosine rom 100 and the sine rom 300 do not store the sampled cosine (COS) and the sign (SIN) as 9-bit data without being stored as 9-bit data. Value is stored as two bits of data, respectively, as shown in FIG.

At this time, the first restoring unit 200 receives the two-bit data stored in the cosine ROM 100 and the output of the flip-flop 11 to be described later. Restore the sampling value of.

The operation of the first reconstructor 200 will be described in detail. First, the first register 201 stores an initial value '512' of the cosine (COS), and the multiplexer 202 stores the initial value and the following description. The feedback data of the first flip-flop 11 is input and multi-transmitted by the control signal of the controller 500 to be output.

In this case, the multiplexer 202 selects an initial value when the reset or phase is 0, 90, 180, 270 degrees, and otherwise selects feedback data of the first flip-flop 11.

Subsequently, the subtractor 203 receives the data on the difference value of the cosine ROM 100 and the data output from the multiplexer 202 and subtracts the data to restore the original sampling data.

Thereafter, the first flip-flop 11 receives the cosine (COS) sampling data recovered from the subtractor 203 and outputs the same by synchronizing with the clock.

Similarly, the data about the difference value stored in the sign ROM 300 is restored by the predetermined control signal of the controller 500 in the second restoring unit 400.

First, the second register 401 stores the initial value '0' of the sign SIN, and the multiplexer 402 receives the initial value and feedback data of the flip-flop 16 which will be described later. Multi-transmit by the control signal of) and output.

In this case, the multiplexer 402 selects an initial value when the reset or phase is 0, 90, 180, 270 degrees, and otherwise selects feedback data of the flip-flop 16.

Next, the adder 403 receives the data of the difference value of the sign ROM 300 and the data output from the multiplexer 402 and adds the data to restore the original sampling data.

Thereafter, the second flip-flop 16 receives the recovered sign (SIN) sampling data from the adder 403 and outputs it in synchronization with a clock.

Then, the first and second multiplexers 12 and 17 receive the synchronized data from the first and second flip-flops 11 and 16, respectively, and phase them by the control signal of the controller 500. In other words, as shown in FIG. 8, the cosine (COS) and the sign (SIN) values are not changed between 0 and 90 degrees, and the control signal ctrl1 has a value of '0' so that the first and second multiplexers are adjusted. (12, 17) In the first multiplexer 12, the output of the first flip-flop 11 is applied to the A input terminal, and the output of the second flip-flop 16 is applied to the B input terminal, and the second multiplexer 17 is applied to the first multiplexer 17. 1 is applied opposite to the multiplexer) to select the input terminal B, and the cosine (COS) and the sign (SIN) value are changed between 90 and 180 degrees, and the control signal (ctrl1) has a value of '1' and The first and second multiplexers 12 and 17 select the A input terminal, and the cosine (COS) and the sign (SIN) values are not changed between 180 and 270 degrees, and the control signal (ctrl1) is set to '0'.With the value, the first and second multiplexers 12 and 17 select the B input terminal, and the cosine (COS) and the sign (SIN) values are changed between 270 and 360 degrees, and the control signal ctrl1 is With the value of '1', the first and second multiplexers 12 and 17 select the A input terminal.

Thereafter, the first and second compensators 13 and 14 receive the cosine and the sinin values output from the first and second multiplexers 12 and 17, respectively. The sign is determined according to the phase and the value is corrected according to the sign.

Referring to the functions of the first and second compensators 13 and 18 in detail, between 0 and 90 degrees, the cosine (COS) and the sign (SIN) values are positive, and the control signal (ctrl2), (ctrl3) becomes '0', Cosine value is '-' between 90 and 180 degrees, SIN value is '+', and control signals (ctrl2) and (ctrl3) are all '0'. 'COS' and 'SIN' are all '1' between 180 and 270 degrees, and the control signals (ctrl2) and (ctrl3) are all '1' and from 270 to 360 degrees The COS value is '+' and the SIN value is '-' and the control signals (ctrl2) and (ctrl3) are output as '0' and '1' respectively.

In other words. In the above, the first and second compensators 13 and 18 become negative when the values of the control signals ctrl2 and ctrl3 are '1', and the values of the control signals ctrl2 and ctrl3 are 0. If it is a positive value.

Thereafter, the third flip-flop 14 receives the output data of the first compensator 13 and outputs a cosine (COS) function value as shown in FIG. The flip-flop 19 receives the output data of the second compensator 18 and outputs a SIN function value as shown in FIG. 7B in synchronization with the clock.

Here, the SIN / COS function value is used to generate a chrominance signal in a TV encoder.

As described in detail above, the present invention does not store the sampled cosine / sine function value of 0 to 90 degrees as 9-bit data without obtaining the difference value from all the sampling values and stores the difference value as 2-bit data. By saving it to the chip, the size of the ROM can be reduced to reduce the size of the chip.

Claims (3)

A cosine ROM for storing a difference value between a sampled cosine value of 0 to 90 degrees and a previously sampled cosine value as 2-bit data; A first restoring unit receiving the stored data from the cosine ROM and restoring the original sampling value; A first flip-flop that receives the recovered sampling value from the first restoring unit and synchronizes it with a clock; A sign ROM storing a difference value between a sampled sine value of 0 to 90 degrees and a previously sampled sine value as 2 bits of data; A second restoring unit receiving data from the sign ROM and restoring the data to an original sampled sign value; A second flip-flop that receives the recovered sampling value from the second restoring unit and synchronizes it with a clock; A first multiplexer which receives data from the first and second flip-flops and changes the cosine function value according to the phase by a predetermined control signal; A first compensator for receiving data from the first multiplexer and determining a sign according to a phase to compensate a function value; A third flip-flop that receives data from the compensator and synchronizes with a clock signal to output the data; A second multiplexer which receives data from the first and second flip-flops and changes a function value wrapped according to a phase by a predetermined control signal; A second compensator for receiving data from the second multiplexer and determining a sign according to a phase to compensate a function value; A fourth flip-flop that receives data from the second compensator and synchronizes the data by a clock signal; A sign / cosine function generation circuit characterized in that the control unit for controlling the overall control unit. The display apparatus of claim 1, wherein the first recovery unit comprises: a first register configured to store an initial value '511' of the cosine; A third multiplexer which receives the initial value and the previous sampling value of the first register and multi-transmits them by a predetermined control signal; And a subtractor configured to receive a multi-transmission value of the third multiplexer and a cosine value of the cosine ROM to subtract the cosine value to restore the original sampling value. The method of claim 1, wherein the second recovery unit comprises: a second register configured to store an initial value '0' of the signature; A fourth multiplexer which receives the initial value and the previous sampling value of the second register and multi-transmits them by a predetermined control signal; And an adder configured to receive the multiplexed value of the fourth multiplexer and the sine value of the sine ROM, add the sine value, and restore the original sampling value.