JP2623983B2 - Line switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line switching circuit,
In particular, the present invention relates to a line switching circuit that switches without interruption on the receiving side of a wireless digital transmission system in which one protection line is provided for N (N ≧ 1) working lines.

[0002]

2. Description of the Related Art When switching between working and protection is performed without interruption on the receiving side of a wireless digital transmission system in which one protection line is provided for N (N ≧ 1) working lines, The data signal of the line is compared.
If the bit width at the stage of comparing and judging the data signal between the working and protection lines is the same as the bit width at the stage of switching, the pilot signal is always transmitted to the protection line. When the phase response of the destuff system PLL at the receiving end of the protection line is stabilized when switching to the
If it is determined that the phases of the data signals between the protection lines match, the phase of the data signal between the working and protection lines does not match at the time of switching due to fluctuations in the phase response of the PLL.
A bit error occurs due to the switching operation.

Therefore, conventionally, in order to avoid the occurrence of this bit error, the bit width M at the stage of switching is larger than the bit width L at the stage of comparing and judging data signals. Circuit switching is performed with a simple circuit configuration. As such a line switching circuit, for example, a circuit as shown in FIG. 3 is conventionally known. FIG.
Shows a configuration example when M = 4 and L = 2. Hereinafter, the operation will be described with reference to the time chart of each unit shown in FIG.

[0004] The first column conversion circuit 101 comprises a clock 11 and a row of data signals 1 transmitted through the working line.
2, the output control signal 1 from the comparison / determination circuit 301
6, the data signal 12 in one column is converted into data signals 14-1 to 14-4 (having a 4-bit width) of four columns and output, and the data signal in the first column is output. The frequency-divided clock 13 corresponding to 14-1 is output. Four columns of data signals (14-1 to 14-4) are supplied to the first data processing circuit 40.
2 is input to the selection circuit 302, and the divide-by-4 clock 13 is output to the first data processing circuit 402 outside the figure.

[0005] The second column conversion circuit 201 comprises a clock 21 and a row of data signals 2 transmitted through a protection line.
2, the output control signal 2 from the comparison / determination circuit 301
6, the data signals 22 in one column are converted into data signals 24-1 to 24-4 (having a 4-bit width) in four columns and output, and the data signals in the first column are output. The frequency-divided clock 23 corresponding to 24-1 is output. The four columns of data signals (24-1 to 24-4) are supplied to the second data processing circuit 50.
2 is input to the selection circuit 302, and the divide-by-4 clock 23 is output to the second data processing circuit 502 and out of the figure.

It should be noted that, as a precaution, the pilot signal is always transmitted to the protection line as described above, but if it is detected that the line quality has deteriorated on the working line, the pilot signal is transmitted. Is switched to the data signal transmitted on the working line. As a result, the phase response of the PLL provided in the second column conversion circuit 201 fluctuates. The first column conversion circuit 101 also includes a PLL, but does not cause a fluctuation problem because the data signal is always handled.

The first data processing circuit 402 outputs a 4-bit input data signal 14- based on the output clock 13.
1 to 14-4 are converted into 2-bit data signals 45-1 to 45-4. At this time, the remaining 2-bit width portion other than the 2-bit width data signal is set to a low level ("L" level), for example. This first data processing circuit 4
02 is input to the comparison determination circuit 301.

The second data processing circuit 502 outputs a 4-bit input data signal 24- based on the output clock 23.
1 to 24-4 are converted into 2-bit data signals 55-1 to 55-4. At this time, the remaining 2-bit width portion other than the 2-bit width data signal is set to, for example, a high level ("H" level). This second data processing circuit 5
02 is input to the comparison determination circuit 301.

The comparison / determination circuit 301 includes output data signals 45-1 to 45-4 of the first data processing circuit 402 and an output data signal 55- of the second data processing circuit 502. 1 to
55-4 are compared with each other to determine whether or not the phases of the data signals transmitted in parallel on the working line and the protection line match, to output a determination signal 31 out of the figure. Referring to the switching control signal 35 input from outside the figure, the column conversion circuit (101 or 20) on the side not currently selected is selected.
An output control signal (16 or 26) is output to 1) to control the phase of the column conversion circuit.

The selection circuit 302 outputs an output data signal (14) of the first column conversion circuit 101 based on the switching control signal 35.
-1 to 14-4) and the output data of the second column conversion circuit 201.
One of the data signals (24-1 to 24-4) is selected, and the data signals 32-1 to 32-4 are output to the third column conversion circuit 303. At this time, the output data signal (32
-1 to 32-4) are output in synchronization with the clock 34 input from outside the figure.

The third column conversion circuit 303 outputs the clock 34
Based on the output data signal (32-1) of the selection circuit 302.
To 32-4) are converted into a data signal 33 in a row and output outside the figure. Here, the clock 34 is an output of a PLL that operates according to the divide-by-4 clock (13, 23), and has the same phase as the divide-by-4 clock (13 or 23) on the side selected by the selection circuit 302. Is controlled as follows.

[0012]

In the conventional line switching circuit described above, when converting a data signal having an M bit width into a data signal having an L bit width, a signal other than the data signal remains (M). −
L) The bit width portion is set to the "H" level or the "L" level. However, since the data signal is either the "H" level or the "L" level, a comparison is made.
If all of the data signals in the column are at "H" level or "L" level, it may be determined that the data phases between the working line and the protection line match in any state. Then, although the original switching range is L bits, the maximum M
(M> L) Switching is performed in a state where the bit phase is shifted, and the phase control is delayed by an amount corresponding to the increase in the phase matching range, so that the phase response fluctuation of the PLL at the time of switching becomes large and output jitter at the time of switching increases. There is a problem of doing.

The present invention has been made in view of such a problem, and has as its object to provide a line switching circuit capable of preventing an increase in output jitter at the time of switching.

[0014]

In order to achieve the above object, a line switching circuit according to the present invention has the following configuration.
That is, the line switching circuit of the present invention receives a row of data signals and a clock transmitted through the working line and converts the row of data signals to M (M ≧ 2) based on the output control signal. The data is converted into a column data signal (having a width of M bits) and output, and the input clock is frequency-divided by M to generate a frequency-divided M clock corresponding to the data signal of the first column in the M column. A first column conversion circuit for outputting a signal; and a second column conversion for receiving the one-line data signal and clock transmitted via the protection line and performing the same processing as the first column conversion circuit. Circuit; receiving the output data signal of the first column conversion circuit and the M-divided clock, and converting the data signal of M-bit width to L (L <L
M) a first data processing circuit for converting and outputting a data signal having a bit width; and receiving an output data signal of the second column conversion circuit and an M-divided clock, and A second data processing circuit for converting a data signal having a width into a data signal having an L (L <M) bit width and outputting the converted data signal; the first and second data circuits;
The output data signals of the M columns of the data processing circuit are compared with each other,
Based on the result of the comparison, the phase matching of data signals transmitted in parallel on the working line and the protection line is determined, and when the phases do not match, the output control signal is output and the first or second column conversion circuit is output. And a selection circuit for selecting and outputting the output data signal of one of the M columns of the first or second column conversion circuit in accordance with a switching control signal supplied from outside; A clock synchronized with a clock corresponding to the output data signal of the first column of the selection circuit is externally supplied, and the output data signals of M columns of the selection circuit are converted into one column based on the external input clock. A third column conversion circuit for converting the data into a data signal and outputting the converted data signal;
In a line switching circuit for switching between active and standby without interruption on the receiving side of a wireless digital transmission system in which one protection line is provided for (N ≧ 1) active lines; first PN pattern A first PN pattern generator for generating a second PN pattern having a pattern different from the first PN pattern; and a second PN pattern generator for generating a second PN pattern having a pattern different from the first PN pattern. And the first data conversion circuit inserts the first PN pattern into a (ML) bit width portion remaining when performing the conversion operation; The data conversion circuit remains during the conversion operation (M-
L) The second PN pattern is inserted into a bit width portion.

[0015]

Next, the operation of the line switching circuit of the present invention configured as described above will be described. In the present invention, data of M bit width is used.
When the data signal is converted into a data signal having an L bit width, the remaining (ML) bit width portion other than the data signal includes PN
Insert a pattern. As a result, since the PN pattern is different between the active system and the standby system, even if all of the four columns of data signals to be compared and determined are at the "H" level or the "L" level, the phase matches. Possible bit width (phase matching range)
Since the "H" level and the "L" level become the same as the bit width of the data signal generated at random, it is possible to prevent an increase in output jitter at the time of switching.

[0016]

FIG. 1 shows a line switching circuit according to an embodiment of the present invention. The same components as those in the conventional example (FIG. 3) are denoted by the same reference numerals. Hereinafter, as in the conventional case, M = 4, L
= 2, the description will focus on the part according to the present invention. FIG. 2 is a time chart of each part.

As shown in FIG. 1, in the present invention, two P
An N pattern generator (103, 203) is provided. These generate different PN patterns. The data processing circuit (102, 202) basically has a 4-column 4-bit width data of the column conversion circuit (101, 201), similarly to the conventional data processing circuit (402, 502). Data signals (14-1 to 14-4, 241-1 to 24-4)
Column 4-bit width data signals (15-1 to 15-4, 25
-1 to 25-4). When performing the conversion,
In the remaining 2-bit width portion other than the data signal, the first data processing circuit 102 generates a first PN pattern generator 103.
And the second data processing circuit 202 inserts the output of the second PN pattern generator 203. Specifically, for example, as shown in the time chart of FIG.
The PN pattern is inserted only in the columns (15-1 and 25-1), and the rest is the same as the conventional one.

Thus, the first PN pattern and the second P
Since this is different from the N pattern, even if all of the four columns of data signals which are compared and determined by the comparison and determination circuit 301 are at the "H" level or the "L" level, the phase can be matched. Since the bit width (phase matching range) is within the same 2 bit width as the bit width of the data signal where the "H" level and the "L" level occur randomly, it is possible to prevent an increase in output jitter at the time of switching. .

[0019]

As described above, according to the line switching circuit of the present invention, when converting a data signal having an M-bit width into a data signal having an L-bit width, a signal other than the data signal is left. (M
-L) Since different PN patterns are inserted between the active system and the standby system in the bit width portion, all of the four columns of data signals to be compared and determined are at the "H" level or Even in the case of the "L" level, the bit width (phase matching range) at which the phase can be matched is the same as the bit width of the data signal in which the "H" level and the "L" level occur randomly. Therefore, there is an effect that an increase in output jitter at the time of switching can be prevented.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of a line switching circuit according to one embodiment of the present invention.

FIG. 2 is a time chart of the circuit according to the embodiment of the present invention.

FIG. 3 is a configuration block diagram of a conventional line switching circuit.

FIG. 4 is a time chart of a conventional circuit.

[Explanation of symbols]

 Reference Signs List 101 first column conversion circuit 102 first data processing circuit 103 first PN pattern generator 201 second column conversion circuit 202 second data processing circuit 203 second PN pattern Generator 301 Comparison / judgment circuit 302 Selection circuit 303 Third column conversion circuit

Claims (1)

(57) [Claims] 1. Receiving a row of data signals and a clock transmitted through a working line, and converting the row of data signals to M (M ≧ 2) rows of data based on an output control signal. Signal (M
A first column conversion for converting the input clock into M and outputting an M-divided clock corresponding to the data signal of the first column in the M column. A second column conversion circuit which receives a row of data signals and a clock transmitted via a protection line and performs the same processing as the first column conversion circuit; and the first column. A first data which receives an output data signal of a conversion circuit and an M-divided clock, converts an M-bit data signal into an L (L <M) bit-width data signal, and outputs the converted data signal. A data processing circuit; receiving the output data signal of the second column conversion circuit and the M frequency-divided clock, and converting the data signal of M bit width to L (L <L
M) a second data processing circuit for converting the data signal into a data signal having a bit width and outputting the data signal; and comparing the output data signals of M columns of the first and second data processing circuits, respectively. Based on the comparison result, the data transmitted in parallel on the working line and the protection line.
And a comparison / judgment circuit that outputs the output control signal when the phases do not match and controls the phase of the first or second column conversion circuit; in accordance with an externally provided switching control signal A selection circuit for selecting and outputting an output data signal of M columns of one of the first and second column conversion circuits; and a clock corresponding to an output data signal of a first column of the selection circuit. A third column conversion circuit for externally receiving a clock synchronized with the above, and converting the output data signals of the M columns of the selection circuit into one column of data signals based on the external input clock; A line switching circuit that switches between working and protection without an instantaneous interruption on the receiving side of a wireless digital transmission system in which one protection line is provided for N (N ≧ 1) working lines; PN
A first PN pattern generator for generating a pattern; a second PN pattern generator for generating a second PN pattern having a pattern different from the first PN pattern. And the first data conversion circuit is provided with the (ML) bit width portion remaining when performing the conversion operation.
The second data conversion circuit inserts the second PN pattern into the (ML) bit width portion remaining during the conversion operation. A line switching circuit characterized by the above.