KR100323675B1 - apparatus for reducing output error of timing recovery device in digital TV - Google Patents

Abstract

It is to provide a timing error reduction device of the timing recovery device for reducing the output error of the timing recovery device by the multipath channel to prevent the deterioration of field synchronization detection performance. The timing recovery with an analog / digital converter and a segment integrator is provided. An apparatus for reducing an output error of a device, comprising: a segment synchronization signal detector for outputting a segment synchronization signal indicating that a segment synchronization signal is detected after detecting a point at which the value integrated in the segment integrator is maximum, and then detecting a segment synchronization signal for each segment; And an equalizer which equalizes the digital complex I-channel signal converted by the analog-to-digital converter according to the segment synchronization signal output from the segment synchronization signal detection unit, and adds an equalizer so that the timing and the equalizer are connected to each other simultaneously. As it works Reducing the output error of the timing recovery device according to the multipath channel there is an effect that it is possible to prevent the deterioration of the field sync detection performance.

Description

Apparatus for reducing output error of timing recovery device in digital TV}

The present invention relates to a digital TV, and more particularly, to an output error reduction device of a timing recovery device.

In a digital communication system, the receiver must convert the received analog signal into a digital signal for sampling at the appropriate moment.

Determining the right moment to take a sample is called timing recovery.

The timing recovery method used in VSB (Vestigial Side Band) digital TV is a timing recovery method using a synchronization signal. This method does not perform timing recovery using random data, but detects a segment synchronization signal periodically entering the data stream. After that, the timing is restored using this.

Hereinafter, a timing recovery apparatus for a digital TV according to the prior art will be described with reference to the accompanying drawings.

1 is a diagram for restoring symbol timing of a timing recovery apparatus according to the prior art, comprising: an analog-to-digital converter 1 for converting a received analog composite I-channel signal into a digital composite I-channel signal according to a sampling frequency; A correlation filter (2) and a signal output from the correlation filter (2), which multiply the four symbols of the digital composite I-channel signal converted by the digital converter (1) with a predetermined coefficient of four symbols and add them together. The SEG_SYNC signal, which is a flag signal indicating that the segment integrator signal is detected after detecting the segment integrator 3 that integrates in one segment period and the point where the value integrated in the segment integrator 3 is the maximum, as the segment synchronization signal. Is kept high, and the segment sync signal detector 4 which outputs a SEG_LOCK signal for each segment indicating the segment sync signal, A phase detector 5 for detecting a phase from the digital composite I-channel signal converted by the analog-to-digital converter 1 according to the SEG_SYNC signal and the SEG_LOCK signal detected by the segment sync signal detector 4, and the phase detector 5 The sampling frequency is varied by controlling the voltage according to the loop filter 6 for outputting a pulse width modulation (PWM) signal according to the phase detected by the loop filter 6 and the pulse width modulation (PWM) signal output from the loop filter 6. It consists of a voltage controlled oscillator 7.

FIG. 2 is a diagram illustrating a detailed configuration of the segment sync signal detector of FIG. 1, FIG. 3 is a diagram showing a characteristic curve of the correlation filter of FIG. 1, and FIG. 4 is a detection of a segment sync signal by the correlation accumulation value of FIG. 3. 5 is a diagram showing a waveform, and FIG. 5 is a diagram showing a timing error waveform of the phase detector of FIG.

FIG. 6 is a diagram for detecting a data segment synchronizing signal of a timing recovery apparatus according to the prior art, and includes a first data field synchronizing signal reference unit 11 for outputting field synchronizing data promised according to the data segment synchronizing signal, and FIG. A first subtractor 12 subtracting the field synchronizing data output from the first data field synchronizing signal reference unit 11 and the analog composite I-channel signal, and a signal subtracted from the first subtractor 12 to synchronize the data segment A first integrator 13 for integrating segment by signal in accordance with a signal, a first minimum error segment detector 14 for detecting a minimum error segment from a signal integrated for each segment in the first integrator 13, and the first minimum A first reliability counter 15 for outputting a first data field synchronization signal when the minimum error segment detected by the error segment detector 14 reaches a predetermined number of times; A second data field synchronizing signal reference unit 16 for outputting the field synchronizing data promised according to the data segment synchronizing signal, and the field synchronizing data and the analog composite I channel output from the second data field synchronizing signal reference unit 16; A second subtractor 17 for subtracting the signal, a second integrator 18 for integrating the signal subtracted by the second subtractor 17 for each segment according to the data segment synchronization signal, and the second integrator 18 The second minimum error segment detector 19 which detects the minimum error segment from the signal integrated for each segment in S and the first data field when the minimum error segment detected by the second minimum error segment detector 19 reaches a predetermined number of times. And a second reliability counter 20 for outputting a synchronization signal.

The operation of the timing recovery apparatus of the digital TV according to the prior art configured as described above will be described in detail with reference to the accompanying drawings.

First, the analog-to-digital converter 1 converts the received analog composite I-channel signal into a digital composite I-channel signal according to a freely oscillating sampling frequency and outputs the resultant signal.

The correlation filter 2 then multiplies the four symbols of the digital composite I-channel signal converted by the analog-to-digital converter 1 with the coefficient four symbols set in advance, corresponding positions thereof, and adds the resultant signal.

That is, as shown in FIG. 2, the correlation filter 2 numerically calculates similar information with four symbols {5, -5, -5, 5} in synchronization with respect to four symbols of the received analog composite I-channel signal. do.

In this case, the correlation filter 2 adds four symbol values for each symbol input and filter coefficients {1, -1, -1, 1}, which are the same pattern as the segment synchronization signal, by multiplying corresponding positions with each other, as shown in FIG. Likewise, the largest value comes from the sync part.

However, since the same pattern of symbols may appear in the data sequence, it is impossible to conclude that the position of the maximum value is the sync part based on the calculation result of only one segment. This situation is especially true for noisy channels.

To solve this, the output of the correlation filter 2 is input to the segment integrator 3 consisting of 832 taps and accumulated in one segment period.

The segment integrator 3 accumulates inputs cyclically in one segment.

As the correlation values continue to accumulate for several segments, only the correlation values in the synchronization interval are consistently increased as shown in FIG.

Of course, the correlation cumulative value of random data may also increase, but the cumulative value appears small because each data is independent and has a probability distribution with an average of zero. The same is true of the effects of noise.

Accordingly, the segment sync signal detector 4 detects the point where the value integrated in the segment integrator 3 is the maximum as the segment sync signal, and then sets the SEG_SYNC signal high (the flag signal indicating that the segment sync signal is detected). high) and outputs a SEG_LOCK signal for each segment indicating a segment synchronization signal.

In other words, the segment synchronizing signal detector 4 may determine that there is a segment synchronizing signal at a point where the segment synchronizing correlation value of the segment integrator 3 is sufficiently accumulated and maximized to a positive value.

Therefore, although the correlation values for the values read at the point shifted by the free oscillating clock are accumulated, the correlation detection method works effectively by accumulating the correlation values for several segments, and the segment synchronization signal detector 4 finally synchronizes. When the detection is completed, the SEG_LOCK signal, which is a flag signal indicating that the segment synchronization signal is detected, is kept high, and the SEG_SYNC signal indicating the segment synchronization signal is output once for each segment.

The signals are output to a timing recoverer (not shown), so that the SEG_LOCK signal determines whether to operate the timing recovery, and the SEG_LOCK signal indicates the position of the segment synchronization signal.

Then, the phase detector 5 detects a phase from the digital composite I-channel signal converted by the analog-to-digital converter 1 according to the SEG_SYNC signal and the SEG_LOCK signal detected by the segment sync signal detector 4, and then the resultant signal. Outputs

Here, the phase detector 5 is a quadrature filter serving as a phase detector with respect to the synchronous four symbols, and the analog / signal according to the high of the SEG_LOCK signal detected by the segment synchronization signal detector 4. After detecting the phase as shown in FIG. 5 from the digital composite I-channel signal converted by the digital converter 1, the detected phase value is output in accordance with the SEG_SYNC signal.

That is, when the data converted by the analog-to-digital converter 1 is exactly {5, -5, -5, 5}, the phase detector 5 is converted to a value of 0 when the timing is shifted to the left. Negative values are shifted to the right and positive values are converted.

Accordingly, the loop filter 6 outputs a pulse width modulation (PWM) signal according to the phase error detected by the phase detector 5, and the voltage controlled oscillator 7 outputs the pulse width output from the loop filter 6. The sampling frequency of the analog / digital converter 1 is controlled by varying the sampling frequency by controlling the voltage according to the modulation (PWM) signal and then outputting the resultant signal.

On the other hand, when the segment sync is detected and timing restoration is completed, field sync can be detected.

That is, as shown in Fig. 6, the first data field sync signal reference section 11 outputs the field sync data promised according to the data segment sync signal.

Then, the first subtractor 12 subtracts the field synchronizing data output from the first data field synchronizing signal reference unit 11 and the analog composite I channel signal and outputs the resultant signal.

Accordingly, the first integrator 13 integrates the signal subtracted by the first subtractor 12 for each segment according to the data segment synchronization signal and then outputs the resultant signal.

That is, the first integrator 13 accumulates the difference between the field synchronization data and the input data promised for each segment period in which the segment synchronization signal is input by the first subtractor 12, and outputs the resultant signal.

Then, the first minimum error segment detector 14 detects the minimum error segment from the signal integrated for each segment in the first integrator 13 and outputs the resultant signal.

That is, when the signal integrated by the segment in the first integrator 13 is equal to or less than a predetermined level, the first minimum error segment detector 14 considers this as a field synchronization signal and outputs the resultant signal.

Accordingly, the first reliability counter 15 outputs a first data field synchronization signal when the minimum error segment detected by the first minimum error segment detector 14 reaches a predetermined number.

That is, the first reliability counter 15 counts the number of times considered as the field synchronization signal in the first minimum error segment detector 14 and outputs the first data field synchronization signal as the field synchronization detection signal when the predetermined number of times is reached. .

The second data field synchronizing signal reference section 16 outputs the field synchronizing data promised according to the data segment synchronizing signal.

Then, the second subtractor 17 subtracts the field synchronizing data and the analog composite I channel signal output from the second data field synchronizing signal reference unit 16 and outputs the resultant signal.

Accordingly, the second integrator 18 integrates the signal subtracted by the second subtractor 17 for each segment according to the data segment synchronization signal and outputs the resultant signal.

That is, the second integrator 18 accumulates the difference between the field synchronization data and the input data promised for each segment period in which the segment synchronization signal is input by the second subtractor 17, and outputs the resultant signal.

Then, the second minimum error segment detector 19 detects the minimum error segment from the signal integrated for each segment in the second integrator 18 and outputs the resultant signal.

That is, when the signal integrated by the segment in the second integrator 18 is equal to or less than a predetermined level, the second minimum error segment detector 19 considers this as a field synchronization signal and outputs the resultant signal.

Accordingly, the second reliability counter 20 outputs a first data field synchronization signal when the minimum error segment detected by the second minimum error segment detector 19 reaches a predetermined number.

That is, the second reliability counter 20 counts the number of times considered as the field synchronization signal by the second minimum error segment detector 19 and outputs the first data field synchronization signal as the field synchronization detection signal when the predetermined number of times is reached. .

However, the timing recovery apparatus of the digital TV according to the prior art has a problem in that an output error of the timing recovery apparatus increases due to this effect when a multipath channel exists in digital TV broadcasting.

Accordingly, the present invention has been made to solve the above problems, and provides an output error reduction device of the timing recovery device for reducing the field synchronization detection performance by reducing the output error of the timing recovery device by the multipath channel. Its purpose is.

1 is a diagram for symbol timing recovery of a timing recovery apparatus according to the prior art;

FIG. 2 is a diagram illustrating a detailed configuration of the segment sync signal detector of FIG.

3 illustrates a characteristic curve of the correlation filter of FIG.

4 is a diagram illustrating a detection waveform of a segment synchronizing signal based on a correlation accumulation value of FIG. 3; FIG.

5 is a diagram illustrating a timing error waveform of the phase detector of FIG.

6 is a diagram for detecting a data segment synchronization signal of a timing recovery apparatus according to the prior art;

7 is a view showing an output error reduction apparatus of a timing restoration apparatus according to the present invention.

8A to 8C are diagrams illustrating each sub waveform of FIG. 7.

Explanation of symbols for main parts of drawings

101: analog to digital converter 102: equalizer

103: correlation filter 104: segment integrator

105: segment sync signal detector 106: phase detector

107 loop filter 108 voltage controlled oscillator

A characteristic of the output error reduction device of the timing recovery device according to the present invention for achieving the above object is, in the output error reduction device of the timing recovery device having an analog / digital converter and a segment integrator, A segment sync signal detector for detecting a point at which the integrated value is maximum as a segment sync signal, and outputting a segment sync signal for every segment indicating that the segment sync signal has been detected, and a segment sync signal output from the segment sync signal detector; And an equalizer for equalizing the digital complex I-channel signal converted by the analog-to-digital converter.

The equalizing unit bypasses the digital composite I-channel signal converted by the analog-to-digital converter because there is no segment synchronization detection signal in an initial state.

The segment sync detection signal is characterized in that the SEG_LOCK signal for determining whether to operate the timing recovery and the SEG_LOCK signal for indicating the position of the segment sync signal.

The equalizer outputs the digital composite I-channel signal output from the analog / digital converter according to the SEG_SYNC signal during a period in which the SEG_LOCK signal output from the segment synchronization signal detector is high {5, -5, -5, 5}. Another feature is to generate the signal, obtain the error signal, equalize it, and output the resultant signal.

The equalizer is another feature of allowing tap coefficient updating only in a synchronous period because the transmission signal is not known in the remaining period.

According to the present invention, by adding a linear equalizer and simultaneously operating the timing and the equalizer in conjunction with each other, it is possible to reduce the output error of the timing recovery apparatus by the multipath channel, thereby preventing the degradation of the field sync detection performance.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, a preferred embodiment of the output error reduction apparatus of the timing restoration apparatus according to the present invention will be described with reference to the accompanying drawings.

7 is a view showing an output error reduction apparatus of a timing recovery apparatus according to the present invention, wherein the analog-to-digital converter 101 converts a received analog composite I-channel signal into a digital composite I-channel signal according to a sampling frequency. An equalizer 102 for equalizing the digital composite I-channel signal converted by the analog-to-digital converter 101 according to the segment synchronization detection signal, and four symbols of the digital composite I-channel signal equalized by the equalizer 102 in advance and in advance; A correlation filter 103 for multiplying the set coefficient 4 symbols by corresponding positions and adding the segment, the segment integrator 104 for integrating the signal output from the correlation filter 103 in one segment period, and the segment integrator 104. SEG_SYNC signal, which is the flag signal indicating that the segment synchronization signal is detected, is detected after detecting the point at which the integrated value is maximized as the segment synchronization signal. And a segment sync signal detector 105 for outputting a SEG_LOCK signal indicating a segment sync signal for each segment, and the analog / digital converter according to the SEG_SYNC signal and the SEG_LOCK signal detected by the segment sync signal detector 105. A phase detector 106 for detecting a phase from the digital complex I-channel signal converted at 101, a loop filter 107 for outputting a pulse width modulation (PWM) signal according to the phase detected at the phase detector 106, and And a voltage controlled oscillator 108 for controlling the voltage according to the pulse width modulated (PWM) signal output from the loop filter 107 to vary the sampling frequency, and the present invention is not limited thereto. Do not.

8A to 8C are diagrams illustrating each sub waveform of FIG. 7.

Referring to the accompanying drawings, the operation of the output error reduction apparatus of the timing recovery apparatus configured as described above will be described in detail as follows.

First, the analog-to-digital converter 101 converts the received analog composite I channel signal into a digital composite I channel signal according to a sampling frequency and outputs the resultant signal.

Then, the equalizer 102 equalizes the digital composite I-channel signal converted by the analog-to-digital converter 101 according to the segment synchronization detection signal, and then converts the resultant signal into a frame synchronization signal detector (not shown) and the correlation filter 103. )

That is, the equalizer 102 bypasses the digital composite I-channel signal converted by the analog-to-digital converter 101 because there is no segment synchronization detection signal in the initial state.

Then, the correlation filter 103 multiplies the four symbols of the digital composite I-channel signal equalized by the equalizer 102 with the coefficient four symbols set in advance, corresponding positions thereof, and adds the result signals.

The segment integrator 104 then integrates the signal output from the correlation filter 103 in one segment period and outputs the resultant signal.

Accordingly, the segment sync signal detector 105 detects a point where the value integrated in the segment integrator 104 becomes the maximum as a segment sync signal, and then sets the SEG_SYNC signal, which is a flag signal indicating that the segment sync signal is detected, to be high. and the SEG_LOCK signal indicating the segment synchronizing signal is output as a segment synchronizing detection signal to the timing recoverer (not shown), equalizer 102 and phase detector 106 for each segment.

Then, the equalizer 102 equalizes the digital composite I-channel signal output from the analog-to-digital converter 101 according to the SEG_SYNC signal and the SEG_LOCK signal output from the segment synchronization signal detector 105, and then frame the result signal. Output to a synchronization signal detector (not shown) and correlation filter 103.

That is, the equalizing unit 102 shows the digital composite I-channel signal output from the analog-to-digital converter 101 as shown in FIG. 8A while the SEG_LOCK signal output from the segment synchronizing signal detecting unit 105 is high. A signal of {5, -5, -5, 5} as shown in FIG. 8B is generated according to the SEG_SYNC signal as described above, an error signal is obtained, equalized, and the resultant signal is a frame sync signal detector (not shown) and a correlation filter. Output to (103).

Since the equalizing unit 102 does not know the transmission signal in the remaining sections, it is necessary to allow tap coefficient updating only in the synchronous section as shown in FIG. 8C.

In other words, the equalizing unit 102 reduces the mean square error between the segment synchronizing signal {5, -5, -5, 5} and the data of the digital complex I-channel signal converted by the analog-to-digital converter 101 during the synchronizing period. The tap coefficient is updated.

The data passing through the filter with the updated tap coefficient reduces the mean square error (MSE) from the originally transmitted signal, which is {5, -5, -5, 5}. This means that the phase error in the equalizer 102 is compensated for.

Thereafter, the correlation filter 103, the segment integrator 104, and the segment synchronization signal detector 105 repeatedly perform the above process according to the equalized signal of the equalizer 102.

The timing recoverer restores timing according to the segment sync detection signal detected by the segment sync signal detector 105.

In addition, the phase detector 106 detects a phase from the digital composite I-channel signal converted by the analog-to-digital converter 101 according to the SEG_SYNC signal and the SEG_LOCK signal detected by the segment sync signal detector 105, and then the result signal. Outputs

The loop filter 107 then outputs a pulse width modulation (PWM) signal according to the phase detected by the phase detector 106.

Accordingly, the voltage controlled oscillator 108 controls the voltage according to the pulse width modulation (PWM) signal output from the loop filter 107 to change the sampling frequency, and then transfers the resulting signal to the analog / digital converter 101. The output will be repeated.

Through this process, the first symbol period of the four symbol periods of the synchronization section passes through the DPLL including the equalizer 102, the phase detector 106, the loop filter 107, and the voltage controlled oscillator 108. The timing correction is performed, but the timing correction is performed by operating only the equalizer 102 without operating the DPLL during the remaining three symbol periods.

The equalizer 102 can obtain an error signal for each of the four symbols of the synchronization symbol section, but in the quadrature filter, which is the phase detector 106 of the DPLL, the correlation value necessary for phase detection is applied to the entire synchronization signal four symbols. It can only be obtained once.

As such, the timing phase error is made by linear compensation through the equalizer 102, and compensation is performed while converting the sampling position through the DPLL.

If there is a ghost in the input signal in this process, the loft is reduced while passing through the equalizer 102.

In other words, the equalizer 102 updates the tap coefficient in a direction in which the MSE decreases during the synchronization period, and compensates linearly by the filter. The tap coefficients are updated close to each other, and the signal with the ghost is compensated for as it passes through the filter with the updated tap coefficients, thereby reducing the error caused by the ghost.

As a result, the equalizer 102s compensate for the timing phase error and reduce the timing recovery output error generated by the ghost in the timing recovery step.

As described above, the output error reducing apparatus of the timing restoring apparatus according to the present invention adds an equalizer to simultaneously operate the timing and the equalizer in conjunction with each other, thereby reducing the output error of the timing restoring apparatus by the multipath channel. There is an effect that can prevent the degradation of.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (5)

In the output error reduction device of the timing recovery device having an analog / digital converter and a segment integrator, A segment synchronizing signal detector for detecting a point at which the value integrated in the segment integrator is maximum as a segment synchronizing signal and outputting a segment synchronizing detection signal for every segment indicating that the segment synchronizing signal is detected; And an equalizer which equalizes the digital composite I-channel signal converted by the analog-to-digital converter according to the segment-synchronous signal detected by the segment-synchronous signal detector. The method of claim 1, The equalizing unit In the initial state, there is no segment synchronizing signal, thereby bypassing the digital composite I-channel signal converted by the analog-to-digital converter. The method of claim 1, The segment sync detection signal is And an SEG_LOCK signal for determining the timing recovery operation and a SEG_LOCK signal for indicating the position of the segment synchronization signal. The method of claim 1, The equalizing unit The digital composite I-channel signal output from the analog-to-digital converter is a signal of {5, -5, -5, 5} according to the SEG_SYNC signal while the SEG_LOCK signal output from the segment synchronization signal detector is high. And an error signal is obtained, equalized, and outputted as a result signal. The method of claim 1, The equalizing unit Since the transmission signal is unknown in the remaining section, the output error reduction device of the timing recovery device characterized in that to allow the tap coefficient update only in the synchronization section.