KR100279618B1 - High-Definition Timing Restorer and Synchronizer Using the Same - Google Patents

Abstract

The present invention relates to a high-definition TV (HDTV) of the ATSC standard or a synchronization technology in a digital TV defined in such a standard, comprising: a matched filter for filtering an input composite signal according to a receiver; A first sampler configured to receive a complex signal output from the matched filter and sample the sampled signal according to a sampling clock; A limiter for limiting the output of the first sampler and supplying it to a multiplier side, which will be described later; A differentiator for differentiating a complex signal output from the matched filter; A second sampler sampling the output signal of the differentiator according to a sampling clock; A multiplier configured to receive the output signals of the first and second samplers and multiply them; An accumulator for receiving and accumulating the output signal of the multiplier; A voltage adjustable oscillator configured to receive an output signal of the accumulator and track a timing such that the cumulative value becomes 0 and supply a sampling clock to the first and second samplers.

Description

High-Definition Timing Restorer and Synchronizer Using the Same

The present invention relates to a synchronization technology in a high definition TV (HDTV) of the ATSC standard or a digital TV defined in such a standard. In particular, a symbol timing recovery operation is performed simultaneously with a synchronization signal detection operation using a maximum likelihood estimator. The present invention relates to a high-definition timing recovery device using a maximum likelihood estimator and a synchronization device using the same.

In a digital communication device, the output of the demodulator must be periodically sampled at the correct timing t _m = mT + τ at the symbol rate and the value read.

Here, T denotes a symbol interval, and τ denotes a delay time occurring during the transmission from the transmitter to the receiver. In order to perform such periodic sampling, a clock signal is required at the receiver, and a process of extracting such a clock signal from the receiver is called symbol timing recovery.

In relation to HDTV, the present invention defines a synchronization system including a synchronization detection unit that detects a segment synchronization signal periodically input into a data stream as well as symbol timing recovery.

Timing recovery can be performed in a number of ways. The first thing to think about is to send the clock used by the transmitter with the information signal. At this time, timing recovery is easy. However, such a system requires an additional frequency band to transmit the clock and requires more power.

There is no additional clock transmission in digital TV using VBB HDTV or the same transmission standard as the residual sideband transmission method. Therefore, a self-synchronization method of extracting a clock signal from a received signal is employed. use.

1A and 1B, a simplified transmission / reception block and shape of a signal in a VSB HDTV will be described, and at which point sampling of a signal should be made. For reference, the connection of the symbol timing recoverer 17 shown in this figure is a virtual picture not applied to the HDTV.

In Figs. 1A and 1B, a symbol composed of MPEG-2 compressed video data and AC3 compressed audio data bit stream and then grouped by 3 bits is input to the impulse modulator 11 to correspond to the symbol value. It is converted into a pulse signal of magnitude and outputted in the symbol period T. The output is input to a transmission filter 12 having an impulse response characteristic as shown in FIG. 1C.

The impact response h (t) of the transmission filter 12 is a function of 'Squre-root Raised Cosine'. It is FIG. 1D which converted this to the frequency domain, and it is a case where (alpha) ≠ 0 among what was shown with the solid line here. In FIG. 1D, a portion indicated by a dotted line is a portion to show that the lower sideband frequency component is removed when the residual sideband (VSB) modulator 13 is later passed through. Raised Cosine (Raised Cosine) is the name given in Figure 1d because the left and right outer part is formed by cutting a part of the cosine function.

The reason why the square root is applied to the cosine function is as described later, but the reception filter 15 designed as a matched filter is a transmission filter to obtain an optimal reception effect in an additive white noise (AWGN) channel. This is because it has the same characteristics as (12).

The channel characteristics can be seen as a bundle of filters when transmitting and receiving. Multiplying these two functions removes the square root and becomes a cosine function with the overall filter characteristics. The channel represented by the cosine function placed on the channel satisfies the Nyquist Criterion (Ref. 1) P188 to exclude adjacent symbol interference (ISI).

Based on [Ref. 1], the shock response h (t) of the transmission filter 12, the shock response f (t) of the reception filter 15, and the cosine function p (t) on which the two shock responses are bound are formulated. Expressed as

The function of the frequency domain with Fourier transform of the above equation is expressed as

As mentioned earlier, if h (t) and f (t) are designed identically, the above expression becomes the squared cosine function of square root.

In the above formula, α is called a roll-off factor, which has a value between 0 and 1. As shown in FIG. 1D, if the value is 0, the ideal low pass filter is H (jω) in the frequency domain and becomes a rectangular shape, thereby minimizing the occupied frequency band, but in the time domain function h (t) as the T period. Intermediate values of the appearing null points remain for long symbol periods, causing interference between adjacent symbols in non-ideal channels (AWGN or ghost channels).

If the value of α increases, the value between Null decreases as the value goes from h (t) to the outside, but in the frequency domain, the cosine region placed on the outside increases more and the excess frequency band increases. It becomes wider. As the value of a changes from 0 to 1, the excess frequency band changes from 0% to 100%. In the VSB HDTV standard, the frequency band is defined as 11.5%.

In FIG. 1D, a frequency band value of 0.31 MHz corresponds to an excess frequency band, and a frequency band allocated to one broadcasting station is 6 MHz, which includes the excess frequency band. The remaining 5.38 MHz, subtracted by 0.3 MHz of the excess bands on both sides, becomes the frequency bandwidth of the signal, and the frequency 10.76 MHz, which is doubled, becomes the frequency of the symbol (1 / T), that is, the frequency on which the symbol is carried. Loading symbols at twice the frequency bandwidth is called Nyquist Rate Transmmi-ssion.

One thing to be mentioned is that h (t) shown in FIG. 1C is non-causal. In other words, the value is developed at a negative time. To make this causal, we have to move 5T to the right in the example of FIG. 1E.

The transmission filter 12 is designed as described above, and the waveforms of the symbols passing through the transmission filter 12 are as shown in FIG. 1E.

The most basic start of data transmission is to send one symbol in one symbol period (T). However, in this case, the frequency bandwidth required for data transmission is increased because narrow pulses in the time domain occupy a wide band in the frequency domain. Therefore, one symbol is transmitted over several symbol periods for transmission efficiency and effective bandwidth limitation. In order to reduce the frequency band, a symbol such as h (t) described above is transmitted instead of a pulse or a rectangle.

In this case, the important fact is that in order to send every symbol input in the period T over one symbol interval, the signal of the form h (t), which is spread over one symbol interval for each symbol, must be overlapped with the T interval. Fortunately, in the channel that satisfies the Nyquist condition, the values of h (t) are all zeros in mT, which is a multiple of the symbol period, so that there is no inter-symbol interference (ISI) and every T time for overlapping incoming signals. By reading the value each time, the original symbol value without interference can be obtained. An example is shown in FIG. 1E, where the transmitted symbol is 7, -5,1, -1,7,5, -1, -7,5. In this way, if the sample interval T is sampled and the value is read, the value sent from the transmitter can be read correctly. This is where the importance of symbol timing recovery can be understood.

For reference, the symbol equalizer generated by the ghost generated in the multipath channel is removed from the channel equalizer. In FIG. 1A, a signal of part (a) is called x (t) and expressed as a formula as follows.

Here, I _n is a symbol value, and h (t-nT) is h (t) shifted by nT, and n indicates how many symbol periods h (t) is spread from side to side.

The information signal x (t) thus constructed is not directly input to the residual sideband modulator 13. Since it is not easy to recover the carrier from the carrier suppressed modulated signal, a DC value of 1.25 is uniformly added to the information signal x (t) to help the carrier recover the carrier. Since the DC frequency portion of the baseband is modulated, it is located at the frequency of the carrier carrier, so adding DC uniformly in the baseband means that there is always a carrier in the modulated passband. This added value is called a pilot signal.

The baseband signal output from the transmission filter 12 is now input to the residual sideband modulator 13 to be carrier suppressed residual sideband modulated. In the frequency domain, the frequency component from the dotted line portion to the right end in FIG. 1D is parallelly moved to the carrier carrier frequency position. When the baseband signal obtained by adding the pilot signal 1.25 to the information signal x (t) is called s (t) and the carrier carrier frequency is f _c , the VSB signal v (t) transmitted through the channel is expressed as follows. do.

v (t) = s (t) cos2πf _c t + s _h (t) sin2πf _c t

Here, s _h (t) is a Hilbert transform. Hilbert transform is obtained by shifting the phase of the signal by 90 °.

The signal v (t) transmitted from the broadcasting station through the above process is input to the demodulator 14 of the receiver so that the carrier carrier is removed and restored to baseband s (t). The output of the demodulator 14 is input to the reception filter 15 having the same impact response as the transmission filter 12 described above. By constructing the impact response f (t) of the receiving filter 15 in the same manner as that of the transmitting filter 12, it is possible to receive the most advantageous signal in terms of signal-to-noise ratio (SNR) in the additive white noise channel. matched filter).

The equation modeling p (t) by combining the transmission filter 12 and the reception filter 15 is shown above. The output s (t) of the receive filter 15 is now input to the sampler 16 and the sampling timing is determined by the clock signal output from the symbol timing recoverer 17. In the figure, the timing is obtained from s (t) to illustrate the basic concept, and the clock is given to the sampler 17. Techniques for symbol timing recovery are addressed in the prior art description and the present invention.

In FIG. 2, an eye diagram drawn by overlapping the output passing through the addable white noise channel and the reception filter 16 in two symbol periods is shown according to SNR. A model of the additive white noise channel is shown in FIG. 3.

White noise occurs throughout the transmitter and receiver, and the cause is thermal noise due to electron browning motion. The thermal noise appears in addition to the signal s (t). (A) of FIG. 2 is a case where SNR = 50dB of small noise, (b) is 20dB, and (c) is 0dB, where the signal power and noise power are the same.

As can be seen in Figure 2 in the good channel (eye) open a lot (eye), the eye is almost closed at about 20dB, it can be seen that the meaning as a signal at 0dB has little meaning. Here, the size of the eye is also related to the width of the excess bandwidth in FIG. 1D showing the impact response of the transmission / reception filter described above. If the excess frequency band is wide, the eye opens a lot, and if it is small, the eye closes a lot.

The width of the excess frequency band varies the design of the symbol timing recovery block. When the excess frequency band is wide, the first conceivable method is the Spectral Line Method [Ref. 1]. Filtering the signal in the excess frequency band with a very narrow bandpass filter yields a timing tone equal to 1/2 of the symbol frequency (1 / T), which can be multiplied and used as a clock signal. have.

This method can be used when the number of symbols is small and the excess frequency band is wide. However, in VSB HDTV, the number of symbols is 8 and the excess frequency band is 11.5%, which is relatively narrow. Therefore, it is proved experimentally that the timing tone obtained here has a lot of jitter.

Another conceivable method in [Ref. 1] is the timing recovery by means of the mean error minimization (MMSE) technique. In this technique, the value sampled at a certain point is determined to be the most similar size among the predetermined symbol values, and then the timing is slightly modified using the difference between the value and the sampled value.

However, this method is also not applicable to VSB HDTV. This is because the levels of the signal received from the broadcasting station are not constant. In analog TV, of course, when the receiver is activated, the tuner or IF stage roughly adjusts the signal, but it is not complete, and the final level adjustment depends on the synchronization signal that knows a fixed or some value.

This process is called Automatic Gain Control (AGC). Unfortunately, since no symbol timing is found initially, no synchronization can be found, and as a result, a signal that is not AGC initially is obtained. Due to such constraints, the existing techniques perform synchronization detection first without performing symbol timing using data itself, and restore symbol timing depending on the detected synchronization signal.

Before describing the prior art, the VSB HDTV data structure of FIG. 4 will be described. HDTV data is roughly divided into the data itself, a segment synchronization signal appearing over four symbols, and a frame synchronization signal inserted in 313 segment periods.

The frame synchronization is composed of one segment and contains a training signal for operating the channel equalizer in a contracted pattern. One segment is composed of 832 symbols including four symbols. Segment sync is set to 5, -5, -5,5 in order, and unlike the analog TV, sync detection is very difficult because it uses the level value that general data can have. 4 is merely a symbol value, and signals modified by a cosine filter placed as described above are actually modulated and transmitted like an analog signal.

5A shows an example of a symbol timing recoverer according to the prior art. This technique is a method proposed by Zenith, who owns the original patent for VSB HDTV transceivers [Ref. 1]. The key to this technique is not to recover the timing with the symbol data itself, but first to find the segment sync signal and then correct the timing error using the data tendency (5, -5, -5,5) of the segment sync signal. have.

The analog composite signal (ACS) including the synchronous signal demodulated through the demodulator is input to the sampler 51, the output of which is read as digital data on the one hand and input to the channel equalizer side, and on the other hand, the synchronizer correlator filter ( 52) and a quadrature filter (55). The synchronizer correlator filter 52 has the characteristics as shown in FIG. 5B and operates every symbol, and the synchronizer correlator filter 52 numerically measures the similarity with the four symbols of the sync portion with respect to two symbols left and right from the reference point. Used for calculation purposes.

That is, at each symbol input, the value read from the left and right two taps and the coefficient shown in FIG. 5B are multiplied and added to the corresponding positions, resulting in the largest value in the synchronization portion. The same pattern of synchronization can occur in the data streams, so a calculation of only one segment shows the maximum value, so you can't conclude that there is a sync.

This situation is especially true for noisy channels. To solve this problem, the output of the synchronizer correlator filter 52 is input to the segment integrator 53 composed of 832 taps so that one segment is accumulated in a cycle. That is, the segment integrator 53 cyclically accumulates inputs with one segment as a cycle. As you continue to accumulate correlation values for multiple segments, only the correlation values in the actual sync interval will grow consistently.

In noise-affected areas, or parts of the data that were once in sync-like patterns, the values did not grow consistently across segments, because negative values exist in the correlation. Although this method currently detects a correlation value for values read at a point shifted by a free oscillating voltage-controlled oscillator (VCO) 58, this synchronization detection method is established by performing for several segments.

The signal processed as described above in the synchronizer correlator filter 52 is input to the sync detector and determiner 54, and when a desired level or more is sensed, a signal indicating that sync has been found is output. This is segment sync. Here, the meaning of the synchronization detecting and determining unit 54 means that the counter is used to check whether the 832 symbol is present again at the current synchronization position to ensure that the correlation value is higher than the reference level.

The prismatic filter 55 has a filtering characteristic as shown in FIG. 5C. The synchronization portion of data input to the prismatic filter 55 is processed to generate an output as shown in FIG. 5E. This waveform is called an S curve, and the square filter 55 has a value of 0 when the sampling timing is normally matched, that is, when the data read from the analog composite signal (ACS) is exactly 5, -5, -5,5. In the case of a slight bias to the left, a negative value is output. In the case of a slight bias to the right, a positive value is output. The output generated in this way is input to the phase detector 56.

The phase detector 56 is designed to read the output of the square filter 55 whenever a segment synchronization occurs. That is, the phase detector 56 is designed to act as a kind of latch. If this is not the case, it is because the voltage-regulated oscillator 58 is controlled by a completely meaningless value obtained by angular filtering of non-synchronous data. In other words, the square filter 55 is designed to generate an S curve when performing a calculation with a sync pattern.

The output of the phase detector 56 is input to the low pass filter 57 to reduce the influence of noise and to control the speed of the phase error reflection. The output of this low pass filter 57 is finally input to the voltage controlled oscillator 58 to shift the sampling timing left or right according to the error value. In this way, the voltage-controlled oscillator 58, which was initially free-running, tracks the timing.

6A shows another example of a symbol timing recoverer according to the related art [Ref. 1]. The basic operation thereof is the same as that of FIG. 5A, except that a method of detecting a timing error is different. The operation thereof will be described below.

First, a baseband analog composite signal (ACS) is input to a sampler 60 and its output is input to a frequency phase corrector 61. The frequency phase corrector (FPLL) 61 corrects the phase error caused by the carrier carrier of the baseband signal demodulated from the carrier suppressed modulated signal and outputs it to the matched filter 62 side.

The matching filter 62 is designed to have the same characteristics as the transmission filter as described above, and the output of the matching filter 62 is input to the segment sync detector 63. An embodiment of the segment sync detector 63 is shown in FIG. 6B, the technical configuration of which is similar to that in FIG. 5A.

That is, as shown in FIG. 6B, an input signal is input to a synchronizer correlator 63A having the same characteristics as the synchronizer correlator filter 52 described above to detect a correlation value, and the values are segment delay (segment of FIG. 5A). (Same as integrator 53) (63D) in order to accumulate as the segment progresses. When the accumulated correlation value is higher than or equal to a desired level, the synchronization generator 63H generates segment synchronization. The values accumulated in the segment delayer 63D continue to accumulate as long as the system operates, and as a result, an overflow may occur, so that the correlation value output from the segment delayer 63D after finding synchronization is divided. Accumulate by dividing by 1/2 through 63E, which is the multiplexer 63F.

The output of the matched filter 62 is also input to the timing error detector 64 on the other hand. This timing error detector 64 is composed of two symbol delayers 64A and 64B and one subtractor 64C as shown in FIG. 6C. Two inputs input to the subtractor 64C, i.e., a value passed through one symbol delayer 64A and two successively passed through two symbol delayers 64A and 64B, are each inside of the segment synchronization part. The value of the two symbols (-5, -5), and the difference between the two points represents the degree of deviation of the sampling point. The sign of this value indicates whether the point is biased forward or backward.

The timing error signal obtained through the above process is input to the latch 65. As described above, the latch 65 is controlled by the segment synchronizing signal to pass the timing error to the loop filter 66 which is designed in a digital manner only for the synchronizing period.

The loop filter 66 performs a kind of low pass filter, and its output signal is input to the sigma-delta D / A converter 67 and represented in binary. The binary representation of the signal is input to the low pass filter 68 and used to remove the influence of noise. The output signal of the low pass filter 68 is finally input to the voltage controlled oscillator 69 to adjust the oscillation frequency, and the sampler 60 is timing based on the oscillation signal of the voltage controlled oscillator 69. Data is periodically sampled at the new point that reflects the error.

On the other hand, Fig. 7 shows how the synchronization correlation value detected by Figs. 5A and 6A accumulates for 32 segments (= 26624) as the segment progresses. That is, FIG. 7A illustrates a case where SNR = 20dB and (b) 0dB. As you can see, after about 30 segments have been entered, synchronization is found. In the meantime, of course, the voltage-regulated oscillators 58 and 69 continue to free oscillate, and only after the synchronization is found, the symbol timing is tracked.

For reference, in FIG. 7, portions in which the correlation value is increased to a negative value are not useful as correlation values appearing at the point shifted to the left and right of a symbol, rather than the exact synchronization middle portion.

In the conventional synchronization apparatus applied to the VSB HDTV as described above, since the segment synchronization is first detected and the data sampling timing is modified and tracked using only the detected synchronization data, timing tracking is impossible from the beginning and is accurate. By operating the sync correlation filter using the sampled data at the point where it was not, the synchronization was found only after many segments were input. As a result, the initial operation time of the TV receiver was delayed. Moreover, after finding synchronization, it is still difficult to provide correct timing in noisy channels by calculating and reflecting timing errors with only the synchronization data input at 832 symbol periods, and passing the loop filter to reduce the noise of the channel as needed. In case of delaying the reflection, there is a problem that the drift due to the temperature of the local oscillator of the transmitting station or the receiving station is not easily followed.

Accordingly, a technical problem to be achieved by the present invention is to simultaneously perform symbol synchronization detection and symbol timing recovery by using a symbol timing recoverer composed of a maximum likelihood estimator and a synchronization detector composed of a conventional correlator filter and a segment delay, and recover symbol timing. The present invention provides a high-definition timing reconstructor and a synchronization device using the same, which reconstructs all symbol data instead of using only synchronization data, and simultaneously performs segment synchronization detection when restoring symbol timing. The present invention also provides a symbol timing decompressor using the maximum estimator as the first feature, and a synchronization device for detecting synchronization using the symbol timing decompressor.

1A is a simplified VSB transmission block diagram in the prior art.

1B is a receive block diagram of a VSB high definition active simplified in the prior art.

FIG. 1C is a time axis and frequency side shock response characteristic diagram of the transmission filter of FIG. 1A; FIG.

FIG. 1D is a time axis and frequency side shock response characteristic diagram of the reception filter of FIG. 1B; FIG.

1E is a waveform diagram of part (a) in FIG. 1A.

2 (a) to 2 (c) are waveform diagrams showing waveforms superimposed on a reception filter through an additive white noise channel at two symbol periods.

3 is a channel modeling diagram of additive white noise (AWGN).

4 is a data format diagram of VSB high definition active with segment synchronization.

5A is a symbol timing recovery block diagram according to the prior art;

5B is a characteristic diagram of a synchronizer correlator filter in FIG. 5A.

Fig. 5C is a characteristic diagram of the square filter in Fig. 5A.

5D is a block diagram of a segment integrator in FIG. 5A.

5E is a waveform diagram of part (a) in FIG. 5A.

6A is another block diagram of a symbol timing recoverer according to the prior art.

6B is a detailed block diagram of the segment sync detector in FIG. 6A.

6C is a detailed block diagram of the timing error detector in FIG. 6A.

FIG. 6D is an explanatory diagram of sampling points of segment synchronization in FIG. 6A; FIG.

7 (a) and 7 (b) are explanatory diagrams of a conventional segment sync detection performance measured while changing the SNR.

8A is a stochastic path explanatory diagram of symbols.

8B is an explanatory diagram of slopes along a symbol path in a section of 0.5T.

9 (a) to 9 (c) are explanatory diagrams showing a product of a negative sign and a slope of a symbol at each point while varying the SNR and the number of observed symbols.

10 is a block diagram of a first example of a maximum likelihood estimator showing an application of the invention.

11 is a block diagram of a second example of a maximum likelihood estimator showing an application of the invention.

12 is an exemplary block diagram of a maximum likelihood estimator in accordance with the present invention.

13 is a block diagram of a first example of a maximum likelihood estimator showing an application of the invention.

14 is a block diagram of a second example of a maximum likelihood estimator showing an application of the invention.

15 is an exemplary block diagram of the ML timing recoverer in FIG.

FIG. 16 is a first example block diagram of the ML timing recoverer in FIG. 14; FIG.

FIG. 17 is a block diagram of a second example of an ML timing recoverer in FIG. 14; FIG.

FIG. 18 is a detailed block diagram illustrating an implementation of the voltage regulated oscillator in FIGS. 15 and 16.

FIG. 19 is a detailed block diagram showing a first embodiment of the segment sync detector in FIGS. 13 and 14; FIG.

20 is a detailed block diagram illustrating a second implementation of the segment sync detector in FIGS. 13 and 14.

*** Description of the symbols for the main parts of the drawings ***

121: Matched filter 122,125: Sampler

123: limiter 124: differential

126: multiplier 127: accumulator

128: voltage controlled oscillator

FIG. 10 is a block diagram of a first embodiment of the maximum likelihood estimator showing the application of the present invention. As shown therein, the signal-to-noise ratio (SNR) in an additive white noise channel is designed to have the same impact response f (t) as the transmission filter. A matched filter 101 for allowing a good signal reception in terms of; A nonlinear device (102) for nonlinear processing the analog composite signal input from the matched filter (101); A differentiator (103) for differentiating the output signal of the nonlinear device (102); A sampler (104) for sampling and outputting the output signal of the differentiator (103) according to a sampling clock; An accumulator (105) for accumulating differential signals output from the sampler (104); The input signal of the accumulator 105 is inputted, and the timing is tracked so that the cumulative value becomes 0. The voltage adjusting oscillator 106 outputs a sampling clock to the sampler 104.

11 is a block diagram of a second embodiment of the maximum likelihood estimator showing the application of the present invention. As shown in FIG. 11, the signal-to-noise ratio (SNR) in an additive white noise channel is designed to have the same impact response f (t) as the transmission filter. A matched filter 111 for enabling a good signal reception in terms of; A sampler 112 for receiving a complex signal output from the matched filter 111 and sampling the sampled signal according to a sampling clock; A differentiator 1113 for receiving and differentiating a composite signal output from the matched filter 111; A sampler (114) for sampling the output signal of the differentiator (113) according to a sampling clock; A multiplier 115 for multiplying the output signals of the samplers 112 and 114; An accumulator 116 that receives and accumulates an output signal of the multiplier; The voltage adjusting oscillator 117 outputs a sampling clock to the samplers 112 and 114 by tracking the timing of receiving the output signal of the accumulator 116 so that the accumulated value becomes 0.

12 is an exemplary block diagram of a high-definition timing recoverer for achieving the object of the present invention. As shown therein, a matching filter 121 for filtering an input composite signal according to a receiving side; A sampler 122 that receives a complex signal output from the matched filter 121 and samples the sampled signal according to a sampling clock; A limiter 123 for supplying the output of the sampler 122 to the multiplier 126 which will be described later; A differentiator 124 that receives and differentiates the composite signal output from the matched filter 121; A sampler 125 for sampling the output signal of the differentiator 124 according to a sampling clock; A multiplier 126 that receives the output signals of the samplers 122 and 125 and multiplies the multipliers; An accumulator 127 for receiving and accumulating the output signal of the multiplier 126; It is composed of a voltage-adjustable oscillator 128 that receives the output signal of the accumulator 127 and tracks timing so that the cumulative value becomes 0, and supplies sampling clocks to the samplers 122 and 125. When described in detail with reference to Figure 13 to Figure 22 attached to the operation of the present invention.

8A and 8B exemplarily illustrate a focus point on a stochastic path and a slope of a symbol according to the present invention, and FIG. 9 illustrates a negative sign and a slope of a symbol at each point obtained by varying the SNR and the number of observed symbols. The focus point on the product is shown by way of example.

That is, FIG. 8A shows the probabilistic location of each symbol and the resulting path of the symbol value with respect to the symbol period. Consider a symbol having a value of 7,5,1, -1, -3, -5, -7 divided by half according to the sign.

If the symbol interval is T, the average of the symbols with positive values at -T time is (a), and the average of the symbols with negative values is (a). (C) becomes Now the symbol time, i.e., the average position of positive symbols at (0T) is (D), the average position of symbols with negative values is (E), and then at stochastic time T in the same way (A), (sa), (a) become. Going back, the average of (a) and (b) is again (b). In the same way, the average of (a) and (a) is also (g). Thus, the symbol value of (D) to be observed at time 0T can be regarded as coming from (B), and the symbol whose trajectory is drawn at (D) goes to (G). It is shown by the thick solid line.

Now, the case of (e) can be considered the same, and drawing the trajectory would be the opposite of the case of (e). In this case, if the sign (negative and positive) of the symbols is detected and the absolute value is obtained, only the path passing through (d) described above remains. If you calculate the slope for this path, the slope at point (D) is zero. This is a very important fact: if you take the slope at each symbol point (mT) and multiply the sign of that symbol's value, the slope becomes zero.

There is also a point where the slope is zero. That is, -0.5T and 0.5T points in FIG. 8B. The thick solid lines illustrate the path of symbols passing through the point as an example. For symbols with positive values, the slope is equally likely to be negative and positive, and so is negative. Therefore, multiplying the symbols of the symbols by these slopes is also zero.

FIG. 9 illustrates the average value obtained by multiplying the slope and the symbol sign while observing a lot of data with an eye diagram. That is, (a) of FIG. 9 shows 832 observation symbols at SNR 20dB, (b) 832 observation symbols at SNR 0dB, and (c) 4160 observation symbols at SNR 0dB. As described above, the slope value is 0 at -0.5T and 0.5T before and after each symbol interval mT and a half symbol period therefrom. Now you can restore the timing by shifting the timing so that the slope value is zero.

Here, the slope of zero appearing before and after the half period need not be considered. This is because if the value to be used as the voltage for adjusting the oscillator is moved to the right if the value is negative and to the left if the value is positive, the timing will remain only near 0T.

There is no problem even if the SNR is very bad. That is, although the timing error is somewhat large in FIG. 9 (b), it may be solved by setting a long observation interval as in FIG. 9 (c). Even if it is not done, as will be described later, new symbols are continuously input and the point continues. Since the timing tracking with only one segment of the symbol does not cause any problem.

The above descriptions are based on [Ref. 4].

10-12 show an embodiment of the maximum likelihood estimator according to the present invention.

For example, in FIG. 10, the matched filter 101 is designed to have the same impact response f (t) as the transmit filter to enable reception of a composite signal in a good state in terms of signal-to-noise ratio (SNR) in an additive white noise channel. The nonlinear device 102 nonlinearly processes the analog composite signal input from the matching filter 101.

In addition, the differentiator 103 differentiates the output signal of the nonlinear device 102, and the sampler 104 samples and outputs the output signal of the differentiator 103 in accordance with the sampling clock.

The accumulator 105 accumulates the differential signal output from the sampler 104, and the voltage-controlled oscillator 106 receives the output signal of the accumulator 105 and tracks the timing so that the accumulated value becomes 0. The sampling clock is supplied to the sampler 104.

The average value of the Logged Likelihood Function applied to the multi-level PAM according to the probability distribution of the symbols is called Λ _L (τ) as a function of timing τ. After removing (Constant), it is expressed as the following expression.

Here, y _n (τ) is a sample of the matched filtered signal at t = mT + τ. The requirement for this probability function to be maximum for τ is that the derivative of τ must be zero. Differentiating the above equation gives the following equation.

What this equation means is that if you control the τ so that the square of the matched filtered signal is squared, or multiply the matched filtered signal by its derivative, then it is the most 'likelihood' timing. Based on the above equations, the maximum likelihood estimators are derived as shown in FIGS. 10 and 11, and FIG. 12 differs in that a sign is used instead of a symbol value as a modification of FIG. 11.

Hereinafter, in the block diagrams and the description of the present invention, a symbol timing recoverer using the maximum likelihood estimator is referred to as an "ML timing recoverer".

In Fig. 13, the analog composite signal ACS is supplied to the sampler 131 on the one hand and to the ML timing recoverer 132 on the other hand. At this time, the ML timing reconstructor 132 accumulates derivative values of the data SDs sampled by receiving the analog composite signal ACS, and tracks timing so that the accumulated value becomes a value of zero to correct the phase. The sampling clock signal SCK is generated and the sampling clock signal SCK is input to the sampler 131. This is made possible by performing nonlinear processing on the data SD before obtaining the derivative at the sampling point.

On the other hand, the segment sync detector 133 recursively accumulates a correlation value with a sync signal composed of 4 symbols supplied from the sampler 131 at 832 symbol periods in a delay configured with 832 taps, and the accumulated value is at a predetermined level. If it is input as the above value, it determines as a synchronization signal and generates the segment synchronization signal SS.

The ML timing decompressor 132 and the segment synchronization detector 133 operate simultaneously when the receiver is activated, and quickly find the synchronization signal using the data SD sampled by the timing to be corrected.

The analog composite signal ACS is supplied to the sampler 141 on the one hand and to the ML timing recoverer 142 on the other hand. At this time, the ML timing restorer 142 accumulates derivative values of the data SDs sampled by receiving the analog composite signal ACS, and tracks timing so that the accumulated value becomes a value of zero, thereby correcting phase. The sampling clock signal SCK is generated, and the sampling clock signal SCK is input to the sampler 141. However, unlike the ML timing decompressor 132 of FIG. 13, the ML timing decompressor 142 multiplies the derivative value at the sampling point by multiplying the value of the sampling data SD or its sign.

Meanwhile, the segment sync detector 143 recursively accumulates a correlation value with a sync signal composed of 4 symbols supplied from the sampler 141 at 832 symbol periods in a delay unit composed of 832 taps, and the accumulated value is at a predetermined level. If it is input as the above value, it determines as a synchronization signal and generates the segment synchronization signal SS.

The ML timing decompressor 142 and the segment synchronization detector 143 operate simultaneously when the receiver is activated, and quickly find the synchronization signal using the data SD sampled by the timing to be corrected.

FIG. 15 illustrates an embodiment of the ML timing recoverer in FIG. 13. The characteristic of the ML timing reconstructor is that if the analog complex signal processed by the nonlinear machine 150 is differentiated and accumulated, the timing is shifted to a value of 0. That is, the timing stays at the point where the symbol value exists, so that accurate timing can be maintained.

That is, the analog composite signal ACS is input to the nonlinear machine 150 to be processed nonlinearly, and its output signal is differentially processed by the differentiator 151 and then sampled by the sampler 152. The signal sampled by the sampler 152 is accumulated by the accumulator 153, and the adjustment voltage generator 154 outputs a control command to the voltage controlled oscillator (VCO) 155 according to the accumulated derivative value. Will be set.

For example, when the accumulated derivative value is a negative value, a control signal for shifting the timing to the right and a left value to the left may be output to control the voltage-controlled oscillator 155. In order to improve the timing correction speed of the voltage-controlled oscillator 155, the accumulated value may be bypassed and operated. At this time, there may be a lot of shaking from side to side even in the normal position.

In addition, the adjustment voltage generator 154 may be implemented as a loop filter in a general PLL to be immune to noise or to adjust the speed of timing error correction. In addition, the accumulator 153 may be reset at a predetermined symbol period so that the accumulator 153 may be accumulated at a corrected new timing. To this end, the counter 156 receives a clock from the voltage controlled oscillator 155 to count the number of symbols, and periodically resets the accumulator 153 to the accumulator 153.

FIG. 16 illustrates one embodiment of FIG. 11.

FIG. 16 illustrates the first embodiment of the ML timing recoverer 142 in FIG. 14, and its basic operation is the same as that of FIG. 15. However, instead of using the nonlinear unit 150 as shown in FIG. 15 before differentiating the analog composite signal ACS input from the differentiator 151, the data SD and the derivative value sampled by the multiplier 157 are not used. The difference is that multiplication also serves as the maximum likelihood estimator.

FIG. 17 illustrates an embodiment of FIG. 12.

FIG. 17 illustrates a second embodiment of the ML timing recoverer 142 in FIG. 14, and its basic operation is the same as that of FIG. 16. However, instead of multiplying the sampled data SD by the derivative as shown in FIG. 16, the value is limited to 1 and -1 through the limiter 158 to obtain only a sign and multiply it.

Meanwhile, as the first embodiment of the nonlinear machine 150 in FIG. 15, a squarer ( ), And as a second embodiment, an absoluteizer ( ), And as a third embodiment, a hyper cosine (ln cosh (.)) Having a log can be given.

15 to 17, the first embodiment of the regulation voltage generator 154 may be a bypass, the second embodiment may be a limiter, and the third embodiment may be a low pass filter. The fourth embodiment may include a circuit in which the limiter 181 and the low pass filter 182 are connected in series as shown in FIG. 18.

Here, the bypass is to input the accumulated value of the input differential value to the voltage-controlled oscillator 155 as it is so that the amount of movement of its oscillation output can be controlled according to the magnitude of the accumulated value. In addition, the limiter is for controlling the voltage-controlled oscillator 155 only by the sign of the input accumulated value. In addition, the low pass filter is to remove the noise that can be carried on the input cumulative value or to prevent the cumulative value of the derivative representing the timing error from changing significantly, so that the error correction speed can be precisely controlled. The output signal of the limiter 181 is filtered by the low pass filter 182 for the same reason.

FIG. 19 illustrates one embodiment of the segment sync detectors 133 and 143 in FIGS. 13 and 14.

The sampled data SD is input to the synchronizer correlator filter 191 having the characteristics as shown in FIG. 5B to calculate a correlation value. This operation is performed at every symbol period, and it is converted into a value that is similar to synchronization considering both left and right symbols at the symbol position to be calculated.

Since the symbol values at positions corresponding to the coefficients of the synchronizer correlator filter 191 are multiplied and all four multiplied result values are added, a large value is output in the synchronization portion. Among random data, many patterns such as sync can be generated probabilisticly, and even if the patterns are not synchronized, signals may be distorted in a noisy channel and become out of sync. For this reason, it is impossible to look at only one segment (832 symbols) and conclude that a large correlation value is that of a synchronization part.

In order to solve this problem, the output of the synchronizer correlator filter 191 is input to the segment delay unit 192 to accumulate and store correlation values for several segments. In other words, the segment delay unit 192 is composed of exactly 832 taps, through which the correlation values accumulate as they cycle through the segment period. When several segments pass, the correlation value increases greatly at the true synchronization point, and the correlation value is relatively small in the once large section because of the influence of noise or the data itself. The position having the predominant correlation value thus obtained can be set as the synchronization section.

The segment synchronization detector 193 receives the output signal of the segment delay unit 192 to determine a point at which a value equal to or greater than a desired level is displayed as a synchronization position, and generates a segment synchronization signal at that point. Even after the synchronization is found through this process, the values of the segment delay unit 192 continue to increase and overflow may occur. Therefore, after synchronization detection, the accumulated correlation value should be reduced to 1/2 and added. 192 is designed to perform this function.

The segment sync signal is input to all devices required by the receiver such as a frame sync detector and a channel equalizer. In addition, the amplification degree of the input analog composite signal (ACS) is not properly controlled until the synchronization detection, and the amplification degree of the signal may be adjusted based on the four symbol values 5, -5, -5,5 constituting the synchronization. Will be.

The basic operation of FIG. 20 is the same as that of FIG. The only difference is that the limiter 190 obtains only the sign of the input data and calculates the correlation value with the synchronization signal using only this sign. In this case too, there is a large correlation in the synchronization part.

Meanwhile, the list of references cited in the detailed description of the present invention is as follows.

[1] Digital Communication-Lee / Messerschmitt, Second Edition. P739-764

[2] IEEE Transactions on Consumer Electronics, Vol. 41, No. 3, August 1995.

[3] IEEE Transactions on Consumer Electronics, V.42N.3, 8/01/96

[4] Digital Communications-Proakis, Third Edition P358-373

As described in detail above, the present invention enables the segment synchronization detection and the symbol timing recovery to be performed at the same time, thereby improving the processing speed by more than twice compared to the conventional synchronization detection time, and operating well in the 0dB situation. In the present invention, only 832 symbols are used to detect the timing error, and even when the signal-to-noise ratio is bad, the timing is deviated by a small amount on average. For example, when three segments (2996 symbols) are used for the observation section, There is an effect that enables stable and reliable timing tracking. As a result, the present invention makes it possible to improve the detection speed by performing symbol timing recovery simultaneously with the synchronization signal detection using the maximum likelihood estimator, and also has the effect of improving the timing tracking performance after the synchronization detection.

Claims (10)

A matching filter for filtering the input composite signal according to the receiving side; A first sampler configured to receive a complex signal output from the matched filter and sample the sampled signal according to a sampling clock; A limiter for limiting the output of the first sampler and supplying it to a multiplier side, which will be described later; A differentiator for differentiating a complex signal output from the matched filter; A second sampler sampling the output signal of the differentiator according to a sampling clock; A multiplier configured to receive the output signals of the first and second samplers and multiply them; An accumulator for receiving and accumulating the output signal of the multiplier; And a voltage-adjustable oscillator configured to supply a sampling clock to the first and second samplers by tracking the timing of receiving the output signal of the accumulator so that the accumulated value becomes 0. 2. The apparatus of claim 1, further comprising: a limiter for limiting the sampled data to 1, -1 to obtain only a sign and to supply the multiplier; A regulated voltage generator generating a control command according to the accumulated value in the accumulator and supplying the control command to a voltage regulated oscillator; And a counter which receives a clock from the voltage-regulated oscillator to count the number of symbols, and further includes a counter that periodically issues a reset command to the accumulator based on the clock. 3. The high-definition timing recovery device according to claim 2, wherein the regulating voltage generator is composed of a bypass filter. The high-definition timing recovery device according to claim 2, wherein the regulating voltage generator is composed of a limiter. 3. The high-definition timing recovery device according to claim 2, wherein the regulating voltage generator is comprised of a low pass filter. 3. The high-definition timing recovery device according to claim 2, wherein the regulating voltage generator is composed of a limiter and a low pass filter. A sampler for sampling and outputting an analog composite signal according to a sampling clock; Accumulate the derivative of the sampled data by receiving the analog composite signal, track the timing so that the accumulated value becomes 0, generate a phase-corrected sampling clock signal SCK, and supply it to the sampler. An ML timing restorer; A correlation value with a synchronization signal composed of predetermined symbols supplied from the sampler at predetermined symbol periods is cyclically accumulated in a delay tab composed of predetermined taps. When the accumulated value is input at a predetermined level or more, the synchronization signal is determined as a synchronization signal. A synchronization device using a high-definition timing recoverer characterized by comprising a segment synchronization detector for generating a signal. 8. The apparatus of claim 7, wherein the segment sync detector comprises: a sync correlator filter that receives the sampled data and filters the multiplied symbol values at positions corresponding to the coefficients and adds all of the result values; A segment delay unit for inputting the output of the synchronizer correlator filter to accumulate and store correlation values for several segments; A synchronization device using a high-definition timing reconstructor comprising a segment synchronization detector configured to receive an output signal of the segment delay unit and determine a point at which a value equal to or greater than a desired level appears as a synchronization position and generate a segment synchronization signal at the point. . 8. The apparatus of claim 7, wherein the segment sync detector comprises: a limiter for obtaining only a sign of the input data to be sampled; A synchronizer correlator filter for receiving the output signal of the limiter and filtering the result by multiplying the symbol values at positions corresponding to coefficients and adding the result values; A segment delay unit for inputting the output of the synchronizer correlator filter to accumulate and store correlation values for several segments; A synchronization device using a high-definition timing reconstructor comprising a segment synchronization detector configured to receive an output signal of the segment delay unit and determine a point at which a value equal to or greater than a desired level appears as a synchronization position and generate a segment synchronization signal at the point. . A sampler for sampling and outputting an analog composite signal according to a sampling clock; Accumulate the derivative of the sampled data by receiving the analog composite signal ACS, and track the timing so that the accumulated value becomes a value of zero to generate a sampling clock signal SCK whose phase is corrected to generate the sample. An ML timing restorer for supplying to and multiplying the derivative value at the sampling point by the value of the sampling data or the sign thereof; A correlation value with a synchronization signal composed of predetermined symbols supplied from the sampler at predetermined symbol periods is cyclically accumulated in a delay tab composed of predetermined taps. When the accumulated value is input at a predetermined level or more, the synchronization signal is determined as a synchronization signal. A synchronization device using a high-definition timing recoverer characterized by comprising a segment synchronization detector for generating a signal.