KR100319914B1 - Phase Control Loop Circuits for Multicarrier Communication Systems - Google Patents

Abstract

The present invention relates to a phase control loop circuit for a multi-carrier communication system, comprising: an analog / digital converter, a zero error detector, a first bandwidth limiter, a time / frequency band converter, a phase detector, a second bandwidth limiter, an alternator and a frequency It consists of an oscillator. Therefore, in a system having a period of controlling the synchronous phase only by the tone signal, during the training period, since only one pilot tone for phase control exists, the phase control loop is operated in this time band. At the end of this period, the data begins to appear in the entire sub-channel, shifting the control of the phase control loop to the frequency band, reducing sync acquisition time as quickly as possible to enter tracking mode.

Description

Phase Control Loop Circuit for Multicarrier Communication System

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase locked loop (PLL) circuit for a multi-carrier communication system. In particular, in a multi-carrier system such as a DMT system, during the initial training period, only one subchannel is loaded with data. Control the phase control loop in the time band to reduce the phase acquisition time as much as possible. After this period, the phase control loop is moved to the frequency domain so that the phase error is continuously tracked so that the phase falls into the lock-in range more quickly. It relates to a control loop circuit.

In general, when designing a phase control loop circuit for synchronization in a digital communication system, it is a common example to operate without dividing into a time band or a frequency band. In the multi-carrier method, some classification is necessary. .

In the case of a multi-carrier communication system, it is not easy to design a phase control loop circuit for synchronizing in the time band because the signals enter and interfere with each other in the time band as viewed from the receiving end. In particular, in the case of a DMT (Discrete Multi-Tone) system, a frequency band signal and a time band signal are mixed in the system itself by using a fast fourier transform (FFT) as a means of modulation and demodulation. In other words, the signal is a frequency band before it is modulated, and the signal from the time after it is modulated until it is demodulated at the channel passing and receiving ends. After demodulation, the signal is interpreted as a frequency band signal. Therefore, in order to analyze and synchronize a signal, it is necessary to analyze the frequency band and the time band separately. Therefore, a phase control loop circuit is designed as an algorithm that synchronizes by analyzing the degree of phase shift of a given data in a frequency band which is relatively easy to implement.

The structure of the phase control loop circuit basically consists of three components, each of which is called a phase detector (PD), a loop filter, and a voltage controlled oscillator (VCO). In addition, the operation mode of the general phase control loop is largely divided into an acquisition mode, a tracking mode, and a steady state mode.

In the initial state of the system, the phase control loop circuit starts operation from the acquisition mode, and the loop must go through the acquisition process in the initial state, and enters the tracking mode after the acquisition process is completed, and the phase control loop is locked. It is said. The steady state mode is the most ideal state in which the phase control loop remains locked, and in reality the lock may be lost in the tracking mode. In this case, you have to go back to capture mode and find the tracking mode again. In other words, in terms of time, the loop continues the operation by endlessly repeating capture and tracking. In this process, the loop must capture the frequency and phase of the input signal. At this time, it may be divided into a lock-in range and a pull-in range according to the magnitude of the initial difference between the input signal frequency and the local voltage controlled oscillator.

When the difference between the frequency of the input signal and the reference frequency is small enough, the loop will pick up the frequency at a moment that can be ignored without the aid of a special auxiliary circuit. At this time, the frequency difference of this range that can capture frequency is called lock-in range. In addition, the frequency range between the frequency of the input signal and the reference frequency is larger than the lock-in range, and the frequency range in which spontaneous frequency capturing by a loop is possible without the help of an external circuit is called a pull-in range. In this process, tracking down to the lock-in range takes considerable time.

In the case of multi-carrier systems, designing a phase-control loop for synchronization in the time band allows the frequency of the signal component to occur when data begins to be loaded on each of the divided channels even though the synchronization is performed during a given training period. As the number of divided channels is mixed together and mixed together, a continuous filter that can separate only the tone signal is needed to operate the phase control loop continuously in the time band. The cost and effort to produce such a filter is a constraint on the implementation of a phase-control loop algorithm to synchronize in the time band. Due to this problem, it is generally easy to implement a phase control loop for synchronization in a frequency band in a frequency division communication system.

Therefore, in a multi-carrier communication system such as DMT, in order to design a phase control loop for synchronization, the received time band data is transferred to a frequency band and divided into data of partial channels, and one divided channel is divided. It is common to catch the phase error by comparing the phase value of the promised data coming in with the phase value of the reference data.

For example, in the case of a DMT system that is determined as a standard method in the United States among the transmission schemes for Asymmetric Digital Subscriber Line (ADSL), a given channel is divided into 256 subchannels to be given for each sub-channel. By considering the SNR (Signal to Noise Ratio), an appropriate number of bits is allocated to each divided channel to transmit data to maximize the channel capacity of a given total channel.

According to the ADSL standard of T1E1.4 on the DMT system, a certain period of time is allocated to the training period in order to synchronize the transmission data in the system initialization stage for starting the whole system.

At this time, the pilot tone using a constant data pattern is used for the 64th sub-channel of the full division channel as a means for synchronizing the entire system initialization process. Looking at the initial synchronization process, we make a promised data pattern with the receiver for the pilot tone on the 64th subchannel in frequency, modulate it with an Inverse Fast Fourier Transform (IFFT) and pass it through the digital analog converter. Done.

The received signal is demodulated by taking an FFT (Fast Fourier Transform) again via an analog digital converter.

At this time, the phase of the demodulated signal and the phase of the promised signal are compared with each other, and the oscillation frequency of the voltage controlled oscillator is changed in consideration of the degree of distortion, thereby changing the sampling frequency of the analog digital converter and the analog digital converter at the correct position. Do the sampling.

However, in the DMT system, in order to change the oscillation frequency of the voltage controlled oscillator of the phase control loop, it is necessary to know the data of the 64th subchannel after demodulating by FFT. In this case, when the definition of one DMT symbol is regarded as an FFT execution unit, the frequency change period of the voltage controlled oscillator is equal to or greater than at least one DMT symbol. That is, there is a disadvantage in that the pull-in time is longer than that in the time band for operating the phase control loop in the frequency band.

When the pull-in time becomes too long, or when the two frequency differences exceed the pull-in range, a special auxiliary circuit must be used to help the frequency-controlled oscillation of the voltage-controlled oscillator. One way to reduce the pull-in time is to consider how to operate the phase control loop in the time band. However, in order to operate the phase control loop in the time band, a sophisticated filter capable of filtering out the 64th subchannel is required, which also increases the complexity when implemented in hardware.

Accordingly, an object of the present invention is to phase-control the phase control loop in the time band during the initial training period in the multi-carrier and system such as the DMT system, the data is loaded only in one sub-channel in order to solve the above problems To reduce the time as much as possible, and to provide a phase control loop circuit that shifts the control of the phase control loop to the frequency domain and tracks the phase error continuously at the end of this period, thereby entering the lock-in range more quickly.

Phase control loop circuit for a multi-carrier communication system according to the present invention to achieve the above object

Analog / Digital Converters for Quantizing Analog Received Signals into Digital Received Signals:

A zero error detector for comparing the number of output samples of the analog / digital converter and the number of zero crossings of the digital reception signal of a time band for each period of the analog received signal, and outputting an error thereof:

A first bandwidth limiter for limiting the time band by summing the errors output from the zero error detector:

A time / frequency band converter for converting a digital reception signal of a time band into a signal of a frequency band for a predetermined time:

A phase detector for detecting a phase error of a synchronization signal from the signal in the frequency band:

A second bandwidth limiter for limiting the frequency band by summing the phase errors of the detected synchronization signals:

During the initial training period, an error signal output from the first bandwidth limiter is selectively outputted in a period in which data is provided in only one subchannel, and after this period, an error signal output from the second bandwidth limiter is selectively outputted. Changer: and

It characterized in that it comprises a frequency oscillator for changing the sampling frequency of the analog / digital converter by the error signal output from the switch.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of a phase control loop circuit according to the present invention, and converts an analog received signal x (t) into a digital received signal x (kT) to convert a time / frequency band converter 14 and a zero crossing detector. The number of output samples of the analog / digital converter 11 and the digital reception signal x (time) of the analog / digital converter 11 to be supplied to (12) and the analog / digital converter 11 for each period of the analog reception signal x (t). kT)) to compare the number of zero crossing points, add the error value output from the zero error detector 12 and the zero error detector 12 that supplies the error value to the first bandwidth limiter 13, The first bandwidth limiter 13 supplied to the switching unit 17 and the digital reception signal x (kT) of the time band for a predetermined time are converted into the values X (f) of the frequency band to provide a phase detector ( The phase error of the synchronization signal from the time / frequency band converter 14 and the values X (f) of the frequency band. A phase detector 15 for detecting and supplying to the second bandwidth limiter 16, a second bandwidth limiter 16 for adding the phase error of the detected synchronization signal to the switching device 17, and the entire system; The output of the first bandwidth limiter 13 is input for a predetermined period of time determined in the initialization operation at this startup, and the output of the second bandwidth limiter 16 is inputted after the end of this period to control the oscillation of the frequency oscillator 18. And a frequency oscillator 18 for generating a conversion control signal for determining the sampling period of the analog / digital converter 11 by the oscillation control signal.

The operation of the phase control loop circuit shown in FIG. 1 will now be described with reference to FIGS. 2 and 3. At this time, in explaining the operation principle of the present invention, a DMT system using the phase control loop circuit shown in FIG.

First, the analog-to-digital converter 11 quantizes the analog reception signal x (t). In this case, when the period of one DMT symbol is regarded as T ₁ of FIG. ₂ , the sampling period of the analog-to-digital converter 11 becomes T ₁ / N.

Here, N is the number of samples constituting one DMT symbol and becomes an FFT execution unit.

In the zero crossing detector 12, the signal x (kT) is extracted from the front end of the time / frequency band converter 14 such as the FFT, which is a time band, during the period in which only the pilot tone signal for synchronizing phase is present, and the received signal x The number of zero-crossing points of (t) is compared with the number of samples sampled by the analog-to-digital converter 11.

For example, if the sampling period of the analog-to-digital converter 11 is eight times the period of the received signal x (t), the number of zero crossing points is two during one period of the received signal x (t). The number of must be eight.

However, in the initialization phase when the synchronization is not correct, the number of samples may vary, resulting in seven or nine. Here, the sampling timing rate of the analog / digital converter 11 can be known by summing and comparing the number of zero crossing points and the number of samples, respectively, for a predetermined time.

That is, set the appropriate reference value, calculate the ratio of (number of samples / number of zero crossing points) and if the value is larger than the reference value, the sampling timing of the analog / digital converter 11 is faster, and if the value is smaller than the reference value, sampling is performed. The timing may be determined to be slow. The error value is calculated and supplied to the first bandwidth limiter 13. At this time, the error value is represented as a value proportional to the frequency and phase difference between the received signal x (t) and the output signal of the frequency oscillator 18. In the first bandwidth limiter 13, the input error value is summed and the output value is used as the oscillation control signal of the frequency oscillator 18 through the switch 17.

On the other hand, a feedback loop using the time difference from the sampling timing as a correction using an algorithm that causes the sampling timing of the analog-to-digital converter 11 to converge to an average position where the ratio of the number of zero crossing points and the number of samples becomes constant. By eliminating the frequency offset and phase offset. That is, the phase control loop directly acts on the sample of the received signal to produce an error signal, and the value is fed back to perform direct control to correct the sampling time point.

Next, from the time when data starts to be loaded on the entire subchannels, the control right for phase synchronization is corrected by the phase detector 15 and the second bandwidth limiter 16 to continuously remove the phase error and phase offset. Go through the process.

On the other hand, in the switching unit 17, the first bandwidth limiter is divided into a time when data is loaded only on the 64th sub-channel used for the pilot tone among all sub-channels and a time when data starts on the entire sub-channel. (13) and the output signal of the second bandwidth limiter 16 is connected to the control terminal of the frequency oscillator 18 to change the sampling frequency of the analog / digital converter 11.

FIG. 3 shows that when a pilot tone signal for capturing a synchronous phase is quaternary phase shift keying (QPSK), a phase of the received signal is compared with a phase of the reference coordinate A (1,1) so that the received signal is converted to the reference coordinate A (1). , 1) shows the convergence process.

In this case, (a) of FIG. 3 shows a process of gradually converging to the reference coordinate when the phase control loop is driven only in the frequency band. In this case, the convergence speed is 1 / T ₁ of FIG. 2 as an inverse of the period of one DMT symbol.

(B) of FIG. 3 shows a convergence method when the phase control loop is designed by the method proposed by the present invention. In the period when only the pilot tone comes, a phase control loop is applied to the algorithm that finds the point where the zero point of the received signal intersects at the front end of the FFT. Converge. At this time, the convergence speed is 1 / T ₂ of FIG. ₂ as a frequency of the input signal itself.

It can be seen that the convergence speed of the phase control loop circuit according to the present invention is faster. That is, the core of the present invention is to remove the frequency offset and the phase offset in the time band so that the overall phase control loop can be synchronized more quickly.

As described above, the phase control loop circuit according to the present invention is suitable for a system having a period for controlling the synchronous phase only by the tone signal. That is, during a training period, only one pilot tone exists for phase control in a certain period of time, so that the phase control loop operates in the time band during this period, and when this period ends and data starts to appear on all subchannels, Moving the control loop of the control loop to the frequency band reduces the acquisition time as quickly as possible to get into tracking mode as soon as possible.

1 shows a phase control loop circuit according to the present invention for a multi-carrier communication system.

FIG. 2 is a waveform diagram of signals before and after passing through an analog digital converter seen in time band in FIG.

3 is a diagram showing a tone signal in constellation coordinates for comparing a method of tracking a phase error in a conventional phase control loop circuit and a method of tracking a phase error in a phase control loop circuit according to the present invention.

Claims (2)

An analog / digital converter for quantizing the analog received signal into a digital received signal; A zero error detector for comparing the number of output samples of the analog / digital converter and the number of zero crossing points of the digital reception signal of a time band at each period of the analog reception signal, and outputting an error thereof; A first bandwidth limiter for limiting a time band by summing an error output from the zero error detector; A time / frequency band converter for converting a digital reception signal of a time band into a signal of a frequency band for a predetermined time; A phase detector for detecting a phase error of a synchronization signal from the signal of the frequency band; A second bandwidth limiter for adding up the phase error of the detected synchronization signal to limit the frequency band; During the initial training period, an error signal output from the first bandwidth limiter is selectively outputted in a period in which data is provided in only one subchannel, and after this period, an error signal output from the second bandwidth limiter is selectively outputted. Transfer machine; And And a frequency oscillator for changing the sampling frequency of the analog / digital converter by the error signal output from the switching device. The phase control loop circuit of claim 1, wherein an error value output from the zero error detector is proportional to a frequency and a phase difference between the received signal and an output signal of the frequency oscillator.