KR100318858B1 - Multi-Etchantd and metal membrane layer patterning of the TFT-LCD making method - Google Patents
Multi-Etchantd and metal membrane layer patterning of the TFT-LCD making method Download PDFInfo
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- KR100318858B1 KR100318858B1 KR1019990005010A KR19990005010A KR100318858B1 KR 100318858 B1 KR100318858 B1 KR 100318858B1 KR 1019990005010 A KR1019990005010 A KR 1019990005010A KR 19990005010 A KR19990005010 A KR 19990005010A KR 100318858 B1 KR100318858 B1 KR 100318858B1
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 47
- 239000002184 metal Substances 0.000 title claims abstract description 47
- 238000000034 method Methods 0.000 title claims abstract description 12
- 238000000059 patterning Methods 0.000 title claims description 5
- 239000012528 membrane Substances 0.000 title 1
- 238000005530 etching Methods 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 229910000838 Al alloy Inorganic materials 0.000 claims abstract description 5
- 101100440985 Danio rerio crad gene Proteins 0.000 claims abstract description 5
- 101100440987 Mus musculus Cracd gene Proteins 0.000 claims abstract description 5
- 101100467905 Mus musculus Rdh16 gene Proteins 0.000 claims abstract description 5
- 239000010408 film Substances 0.000 abstract description 16
- 238000005253 cladding Methods 0.000 abstract description 5
- 239000010409 thin film Substances 0.000 abstract description 4
- 239000000470 constituent Substances 0.000 abstract description 2
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract 1
- 238000004904 shortening Methods 0.000 abstract 1
- 238000001039 wet etching Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 2
- 229910000583 Nd alloy Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000003411 electrode reaction Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
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- Engineering & Computer Science (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Liquid Crystal (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- ing And Chemical Polishing (AREA)
Abstract
본 발명은 TFT-LCD(박막 트렌지스터-액정 디스플레이)의 제조공정 중에서 크레드층과 메탈층으로 이루어진 금속막층의 패턴과 동시에 에칭이 가능하도록 하는 박막층의 구조 및 에칭용 에천트에 관한 것이다BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a thin film layer and an etchant for etching to enable simultaneous etching of a pattern of a metal film layer consisting of a crad layer and a metal layer in a manufacturing process of a TFT-LCD (thin film transistor-liquid crystal display).
종래 TFT-LCD의 제조공정중 크레드층(Mo)과 메탈층(Al)의 구성 원소의 전기화학적 특성상 동일 에천트에 의해 원하는 패턴의 동시 에칭이 되지않아 별도의 에천트를 사용하므로 상대적 공정수가 증가하여 제조원가의 상승 및 생산성저하 요인이 되었다.Due to the electrochemical characteristics of the constituent elements of the cladding layer (Mo) and the metal layer (Al) during the manufacturing process of the conventional TFT-LCD, since the same pattern does not simultaneously etch a desired pattern, a separate etchant is used to increase the relative number of processes. As a result, manufacturing costs have increased and productivity has decreased.
따라서 본 발명은 크레드층을 Ti, 메탈층을 Al 또는 Al + Nd(1∼10wt％)의 Al합금을 사용하여 구성하고 이를 에칭하기 위한 에천트를 HF + HIO4+ HN03로 구성하여 크레드층과 메탈층을 동시 에칭할 수 있도록 함으로서 기존대비 공정 단축에 의해 제조원가를 절감하고 생산성 제고를 통한 가격경쟁력을 제공하는 것이다.Therefore, in the present invention, the cladding layer is made of Ti, the metal layer is made of Al or Al + Nd (1-10wt%) Al alloy, and the etchant for etching the creed layer is composed of HF + HIO 4 + HN0 3 . By allowing the simultaneous etching of the metal layer and the metal layer, manufacturing costs are reduced by shortening the process compared with the existing one, and price competitiveness is provided by improving productivity.
Description
본 발명은 TFT-LCD(박막 트렌지스터-액정 디스플레이)의 제조공정 중에서 크레드층인과 메탈층으로 이루어진 금속막층의 패턴닝을 위해 동시에 에칭이 가능하도록 하는 금속막층의 구조 및 이를 에칭하기 위한 멀티 에천트에 관한 것이다.The present invention provides a structure of a metal film layer that enables simultaneous etching for the patterning of a metal film layer consisting of a cradle layer and a metal layer in a manufacturing process of a TFT-LCD (thin film transistor-liquid crystal display), and a multi-etchant for etching the same. It is about.
TFT(Thin Film Transistor)-LCD의 구성 요소 중에서 게이트(Gate)전극, 소스(Source)전극 및 드레인(Drain)전극은 금속막층으로 되어 있으며, 이 금속막은 Al, Cu 와 같은 전기저항이 낮은 금속이 적용되어지고 있다.Among the components of thin film transistor (TFT) -LCD, the gate electrode, the source electrode, and the drain electrode are made of a metal film layer, and the metal film is made of metal having low electrical resistance such as Al and Cu. Is being applied.
그런데, 이 금속막은 EM(Electro - Migration)현상 때문에 Al, Cu 단독으로 사용이 어려운 상태이므로 현재는 EM현상 방지를 위해 메탈 금속막의 상부에 크레드 (Clad) 막을 도포 하는 크레드/메탈(Metal) 형태의 금속막층으로 구성되어있다.However, since the metal film is difficult to use Al and Cu alone due to EM (Electro-migration) phenomenon, it is currently in the form of a cradle / metal type to apply a clad film on top of the metal metal film to prevent EM phenomenon. It consists of a metal film layer.
그리고 후공정인 패턴의 형성을 위한 습식식각공정 에서는 에천트(Etchant)를 사용하여 45°를 유지하는 사다리꼴의 에칭 프로파일(Etch Profile)을 가지도록 패턴 식각을 하여야 한다.In the wet etching process for the formation of the pattern, which is a post-process, the pattern is etched to have a trapezoidal etching profile that maintains 45 ° using an etchant.
그러나 기존의 습식식각공정 에서는 크레드층과 메탈층의 구성 원소의 전기화학적 특성상 동일 에천트에 의해 원하는 패턴의 동시 에칭이 되지 않아 별도의 에천트를 사용하여 크레드층(Mo)식각과 메탈층(Al)식각을 별도로 실시하므로서 상대적으로 공정수가 증가하게 된다.However, in the conventional wet etching process, since the desired pattern is not etched simultaneously by the same etchant due to the electrochemical properties of the constituent elements of the clad layer and the metal layer, a separate etchant is used to etch the crad layer (Mo) and the metal layer (Al). As the etching is performed separately, the number of processes increases relatively.
따라서 패턴과 에칭이 동시에 이루어지지 않는 관계로 공정수가 자연히 증가하여 제조원가를 상승시키는 요인이 되며, 이로 인하여 생산성이 저하되는 원인이 되는 것이다.Therefore, since the number of processes is naturally increased because the pattern and the etching are not performed at the same time, the manufacturing cost is increased, which causes a decrease in productivity.
즉, 기존의 TFT-LCD용 금속막층은 크레드층이 Mo, 메탈층이 Al으로 구성되어 있어서 Mo과 Al은 wjs극 전위차가 크기 때문에 패턴닝(Patterning) 공정인 습식식각 과정에서 갈바닉 전지(Galvanic Cell)를 형성하여 전기화학적 에칭현상이 일어나 Mo은 음극, Al은 양극 역할을 하여 메탈층인 Al의 에칭속도가 크레드층인 Mo에 비해 매우 빠르기 때문에 원하는 패턴의 형성을 위한 동시 에칭이 불가능한 실정 이다.That is, in the conventional TFT-LCD metal film layer, since the cladding layer is made of Mo and the metal layer is made of Al, Mo and Al have a large wjs pole potential difference, so a galvanic cell is used in the wet etching process, which is a patterning process. ), And the electrochemical etching phenomenon occurs, Mo acts as a cathode, Al acts as an anode, so the etching rate of Al, which is a metal layer, is much faster than Mo, which is a crad layer.
본 발명은 상기와 같은 문제점을 해소하기 위해 안출된 것으로 크레드층과 메탈층을 한번에 동시에 에칭시켜 원하는 패턴을 구성시킴으로서 TFT-LCD의 제조공정 단축에 따른 제조원가를 절감하도록 하는 금속막층의 구조 및 이러한 금속막층의 에칭을 위한 멀티-에천트(Multi-Etchant)를 제공하는 것이다.The present invention has been made to solve the above problems, and the structure of the metal film layer to reduce the manufacturing cost of the TFT-LCD manufacturing process by forming a desired pattern by simultaneously etching the cradle layer and the metal layer at a time and such metal It is to provide a Multi-Etchant for etching the film layer.
도 1 은 스텐다드 패턴의 TFT-LCD 도.1 is a TFT-LCD diagram of a standard pattern.
1 : 크레드층2 : 메탈층1: Creed layer 2: Metal layer
이러한 목적을 갖는 본 발명은 크레드층과 메탈층으로 구성된 TFT-LCD용 금속막층에 있어서, 상기 크레드층은 Ti로 구성하고, 상기 메탈층은 Al 또는 Al + Nd(1 ∼ 10wt％)의 Al합금으로 구성됨을 특징으로 하는 동시 에칭이 가능한 TFT-LCD용 금속막층의 구조에 의해 이루어진다.또한 본 발명은 Ti로 이루어진 크레드층과 Al 또는 Al + Nd(1 ∼ 10wt％)의 Al합금으로 이루어진 메탈층으로 구성된 동시 에칭이 가능한 TFT-LCD용 금속막층을 에칭하는 에천트에 있어서, 상기 에천트가 HF + HIO4+ HN03
상기의 금속막층을 동시에 에칭시킬 수 있는 멀티-에천트는 분자식(Formula)은 HF + HIO4+ HN03로 구성된다.상기에서 HF는 0.1 ∼ 7.0wt％, HIO4는 0.01 ∼ 5.0wt％, HN03는 1.0 ∼ 65.0wt％ 이다.The multi-etchant capable of simultaneously etching the metal layer is composed of a formula of HF + HIO 4 + HN0 3 , where HF is 0.1 to 7.0 wt%, HIO 4 is 0.01 to 5.0 wt%, and HN0. 3 is 1.0-65.0 wt%.
본 발명은 멀티 에천트의 적용시 Al과 전극전위차를 최소화할 수 있도록 하여 원하는 패턴의 동시 에칭이 가능하도록 하는 것이다.The present invention is to minimize the Al and the electrode potential difference when applying the multi-etchant to enable simultaneous etching of the desired pattern.
본 발명은 패턴의 동시 에칭이 가능하므로서 공정의 단축이 가능하여 제조원가를 절감하고 생산성 제고 등을 통한 TFT-LCD의 가격경쟁력 제고를 가져올 수 있는 것이다.In the present invention, since the pattern can be simultaneously etched, the process can be shortened, thereby reducing the manufacturing cost and increasing the price competitiveness of the TFT-LCD through productivity.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019990005010A KR100318858B1 (en) | 1999-02-12 | 1999-02-12 | Multi-Etchantd and metal membrane layer patterning of the TFT-LCD making method |
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| KR1019990005010A KR100318858B1 (en) | 1999-02-12 | 1999-02-12 | Multi-Etchantd and metal membrane layer patterning of the TFT-LCD making method |
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| KR19990037892A KR19990037892A (en) | 1999-05-25 |
| KR100318858B1 true KR100318858B1 (en) | 2002-01-04 |
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| KR20060094487A (en) * | 2005-02-24 | 2006-08-29 | 간또 가가꾸 가부시끼가이샤 | Etchant compositions for metal laminated films having titanium and aluminum layer |
| KR101317473B1 (en) * | 2006-08-23 | 2013-10-18 | 간또 가가꾸 가부시끼가이샤 | Etchant compositions for metal laminated films having titanium and aluminum layer |
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