KR100317485B1 - Method of manufacturing a semiconductor device - Google Patents
Method of manufacturing a semiconductor device Download PDFInfo
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- KR100317485B1 KR100317485B1 KR1019990060513A KR19990060513A KR100317485B1 KR 100317485 B1 KR100317485 B1 KR 100317485B1 KR 1019990060513 A KR1019990060513 A KR 1019990060513A KR 19990060513 A KR19990060513 A KR 19990060513A KR 100317485 B1 KR100317485 B1 KR 100317485B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000010410 layer Substances 0.000 claims description 60
- 239000003990 capacitor Substances 0.000 claims description 24
- 150000004767 nitrides Chemical class 0.000 claims description 20
- 125000006850 spacer group Chemical group 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 11
- 239000011229 interlayer Substances 0.000 claims description 10
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 6
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- 230000004888 barrier function Effects 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 description 33
- 229920002120 photoresistant polymer Polymers 0.000 description 13
- 238000005530 etching Methods 0.000 description 10
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000002596 correlated effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
- H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
- H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02293—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process formation of epitaxial layers by a deposition process
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02538—Group 13/15 materials
- H01L21/0254—Nitrides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02551—Group 12/16 materials
- H01L21/02554—Oxides
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76865—Selective removal of parts of the layer
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 고집적 메모리 반도체 장치의 0.1㎛ 이하의 게이트 길이를 갖는 셀에서 게이트를 스페이서형으로 형성하여 집적화하므로, 게이트 길이에 대한 임계 치수 균일성을 향상시킬 수 있고, 비트라인 콘택에 대한 디자인 룰 마진을 증가시킬 수 있는 반도체 소자의 제조 방법에 관하여 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in the cell having a gate length of 0.1 μm or less of a highly integrated memory semiconductor device, the gates are formed in an integrated form, so that the critical dimension uniformity with respect to the gate length can be improved. A method of manufacturing a semiconductor device capable of increasing a design rule margin for bit line contacts is described.
Description
본 발명은 반도체 소자의 제조 방법에 관한 것으로, 특히 고집적 메모리 반도체 장치의 0.1㎛ 이하의 게이트 길이(gate length)를 갖는 셀에서 게이트를 스페이서형(spacer type)으로 형성하여 집적화(integration)하므로, 게이트 길이에 대한 임계 치수 균일성(CD uniformity)을 향상시킬 수 있고, 비트라인 콘택에 대한 디자인 룰 마진(design rule margin)을 증가시킬 수 있는 반도체 소자의 제조 방법에 관하여 기술된다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device. In particular, a gate is formed in a spacer type in a cell having a gate length of 0.1 μm or less in an integrated memory semiconductor device, and thus, the gate is integrated. Disclosed is a method of fabricating a semiconductor device that can improve CD uniformity over length and can increase design rule margin for bitline contacts.
일반적으로, 반도체 소자가 고집적화 되어감에 따라 4G 이상 고집적 메모리반도체 장치의 셀에서는 0.1㎛ 이하 길이를 갖는 게이트의 형성이 요구되고 있다. 그러나, 현재 사용되는 있는 노광장비로 미세 게이트 길이를 갖는 게이트를 형성하기 어려운 실정이며, 기존의 노광 장비를 이용하되 미세 게이트 길이를 갖는 게이트를 형성하기 위한 연구가 진행중이다.In general, as semiconductor devices become highly integrated, formation of gates having a length of 0.1 μm or less is required in cells of 4G or more highly integrated memory semiconductor devices. However, it is difficult to form a gate having a fine gate length with an exposure apparatus that is currently used, and research is being conducted to form a gate having a fine gate length using existing exposure equipment.
도 1a 내지 도 1c는 종래 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도이다.1A to 1C are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device.
도 1a를 참조하면, 반도체 기판(11)에 소자 분리막(12)을 형성하여 액티브 영역(active region)을 정의(define)한 후, 게이트 산화막(13), 도프트 폴리실리콘층(14), 금속층(15) 및 하드 마스크층(16)을 순차적으로 형성한다. 하드 마스크층(16) 상에 게이트 마스크를 사용한 사진 공정으로 포토레지스트 패턴(10)을 형성한다.Referring to FIG. 1A, after the device isolation layer 12 is formed on the semiconductor substrate 11 to define an active region, the gate oxide layer 13, the doped polysilicon layer 14, and the metal layer are defined. 15 and the hard mask layer 16 are sequentially formed. The photoresist pattern 10 is formed on the hard mask layer 16 by a photolithography process using a gate mask.
상기에서, 금속층(15)은 WSix 혹은 W을 사용하여 형성한다. 하드 마스크층(16)은 질화물을 사용하여 형성한다.In the above, the metal layer 15 is formed using WSix or W. The hard mask layer 16 is formed using nitride.
도 1b를 참조하면, 포토레지스트 패턴(10)을 식각 마스크로한 식각 공정으로 하지층들(16, 15, 14 및 13)을 순차적으로 식각하여 게이트(145)를 형성한다. LDD 이온 주입으로 드레인 접합부(17a) 및 소오스 접합부(17b)를 형성한다. 이후, 전체 구조상에 산화막(18) 및 질화막(19)을 순차적으로 형성한다.Referring to FIG. 1B, a gate 145 may be formed by sequentially etching the underlayers 16, 15, 14, and 13 by an etching process using the photoresist pattern 10 as an etching mask. The LDD ion implantation forms the drain junction 17a and the source junction 17b. Thereafter, the oxide film 18 and the nitride film 19 are sequentially formed on the entire structure.
도 1c를 참조하면, 전면 건식 식각으로 질화막 및 산화막(19 및 18)을 식각하여 게이트(145) 측벽에 게이트 절연 스페이서(189)를 형성하여 셀 구조를 완성한다.Referring to FIG. 1C, the nitride film and the oxide films 19 and 18 are etched by dry etching to form a gate insulating spacer 189 on the sidewall of the gate 145 to complete a cell structure.
이후, 후속 공정으로 선택적 에피텍셜 성장(Selective Epitaxial Growth; SEG)법을 이용하여 반도체 기판(11)의 노출된 표면에만 폴리실리콘을 성장시켜 드레인 접합부(17a)에는 비트라인 콘택 랜딩 패드(bit line contact landing pad)를, 소오스 접합부(17b)에는 캐패시터 콘택 랜딩 패드(capacitor contact landing pad)를 형성한다.Subsequently, polysilicon is grown only on the exposed surface of the semiconductor substrate 11 using a selective epitaxial growth (SEG) method in a subsequent process, so that the bit line contact landing pad (bit line contact) is formed on the drain junction 17a. A landing pad is formed, and a capacitor contact landing pad is formed at the source junction 17b.
전술한 바와 같이, 기존의 방법으로 게이트 길이가 0.1㎛ 이하인 고집적 반도체 장치의 셀을 형성할 경우, 기존의 장비로는 게이트 임계 치수의 균일성을 보장하지 못하는 단점이 있으며, 또한 포토레지스트 패턴 사이의 브릿지(Bridge) 문제 및 포토레지스트 패턴 단선의 문제점이 있다. 기존의 장비를 이용하여 0.1㎛ 이하의 포토레지스트 패턴을 형성하더라도, 후속 공정인 건식 식각 공정에서 게이트 라인들이 쓰러져 버리는 문제점이 있다.As described above, when forming a cell of a highly integrated semiconductor device having a gate length of 0.1 μm or less by the conventional method, there is a disadvantage in that the existing equipment does not guarantee uniformity of gate critical dimensions, and also between the photoresist patterns There is a problem of bridge and photoresist pattern disconnection. Even if the photoresist pattern having a thickness of 0.1 μm or less is formed using existing equipment, gate lines may fall down in a dry etching process, which is a subsequent process.
따라서, 본 발명은 고집적 메모리 반도체 장치의 0.1㎛ 이하의 게이트 길이를 갖는 셀에서 게이트를 스페이서형으로 형성하여 집적화하므로, 게이트 길이에 대한 임계 치수 균일성을 향상시킬 수 있고, 비트라인 콘택에 대한 디자인 룰 마진을 증가시킬 수 있는 반도체 소자의 제조 방법을 제공함에 그 목적이 있다.Accordingly, the present invention forms and integrates gates in a spacer type in a cell having a gate length of 0.1 μm or less in an integrated memory semiconductor device, thereby improving critical dimension uniformity with respect to the gate length, and designing a bit line contact. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of increasing rule margin.
이러한 목적을 달성하기 위한 본 발명에 따른 반도체 소자의 제조 방법은 소자 분리막이 형성된 반도체 기판 상에 희생막을 형성한 후, 게이트 형성 부분이 정의되도록 패터닝 하는 단계: 상기 패터닝된 희생막의 측벽에 스페이서형 게이트를형성하는 단계: 상기 패터닝된 희생막을 제거한 후, 드레인 접합부 및 소오스 접합부를 형성하고, 게이트의 측벽에 게이트 절연 스페이서를 형성하는 단계; 상기 반도체 기판이 노출된 부분의 상기 드레인 접합부에는 비트라인 콘택 랜딩 패드를, 상기 소오스 접합부에는 제 1 캐패시터 콘택 랜딩 패드를 형성한 후, 전체 구조상에 하드 마스크층을 형성하는 단계; 상기 하드 마스크층을 포함한 전체 구조상에 제 1 층간 절연막을 형성한 후,상기 비트라인 콘택 랜딩 패드와 연결되는 비트라인을 형성하는 단계; 상기 비트라인을 포함한 전체 구조상에 제 2 층간 절연막을 형성한 후, 상기 제 1 캐패시터 콘택 랜딩 패드와 연결되는 제 2 캐패시터 콘택 랜딩 패드를 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of fabricating a semiconductor device, the method comprising: forming a sacrificial layer on a semiconductor substrate on which an isolation layer is formed, and then patterning a gate forming portion to be defined: a spacer-type gate on a sidewall of the patterned sacrificial layer Forming a drain junction and a source junction, and forming a gate insulating spacer on sidewalls of the gate; Forming a bit line contact landing pad at the drain junction of the exposed portion of the semiconductor substrate and a first capacitor contact landing pad at the source junction, and then forming a hard mask layer over the entire structure; Forming a first interlayer insulating layer on the entire structure including the hard mask layer, and then forming a bit line connected to the bit line contact landing pad; And forming a second interlayer insulating layer on the entire structure including the bit line, and then forming a second capacitor contact landing pad connected to the first capacitor contact landing pad.
도 1a 내지 도 1c는 종래 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도.1A to 1C are cross-sectional views of a device for explaining a method of manufacturing a conventional semiconductor device.
도 2는 본 발명의 실시예에 따른 반도체 소자의 레이아웃.2 is a layout of a semiconductor device in accordance with an embodiment of the present invention.
도 3a 내지 도 3i는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도.3A to 3I are cross-sectional views of devices for explaining a method of manufacturing a semiconductor device in accordance with an embodiment of the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11: 반도체 기판 12: 소자 분리막11: semiconductor substrate 12: device isolation film
13: 게이트 산화막 14: 도프트 폴리실리콘층13: gate oxide film 14: doped polysilicon layer
15: 금속층 145: 게이트15: metal layer 145: gate
16: 하드 마스크층 17a 및 17b: 드레인 및 소오스16: hard mask layers 17a and 17b: drain and source
18: 산화막 19: 질화막18: oxide film 19: nitride film
189: 게이트 절연 스페이서 10, 20: 포토레지스트 패턴189: gate insulating spacer 10, 20: photoresist pattern
21: 반도체 기판 22: 소자 분리막21: semiconductor substrate 22: device isolation film
23: 희생막 24: 게이트 산화막23: sacrificial film 24: gate oxide film
25: 도프트 폴리실리콘층 26: 금속층25: doped polysilicon layer 26: metal layer
256: 게이트 27a 및 27b: 드레인 및 소오스256: gates 27a and 27b: drain and source
28: 제 1 산화막 29: 제 1 질화막28: first oxide film 29: first nitride film
289: 게이트 절연 스페이서 31: 비트라인 콘택 랜딩 패드289: gate insulating spacer 31: bitline contact landing pad
32: 제 1 캐패시터 콘택 랜딩 패드 33: 제 2 산화막32: first capacitor contact landing pad 33: second oxide film
34: 제 2 질화막 35: 제 1 층간 절연막34: 2nd nitride film 35: 1st interlayer insulation film
36: 비트라인 콘택 37: 비트라인36: bit line contact 37: bit line
38: 캡핑층 39: 제 2 층간 절연막38: capping layer 39: second interlayer insulating film
41: 캐패시터 콘택 42: 제 2 캐패시터 콘택 랜딩 패드41: Capacitor contact 42: Second capacitor contact landing pad
이하, 본 발명을 첨부된 도면을 참조하여 상세히 설명하기로 한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 실시예에 따른 반도체 소자의 레이아웃이고, 도 3a 내지 도 3i는 본 발명의 실시예에 따른 반도체 소자의 제조 방법을 설명하기 위한 소자의 단면도이다.2 is a layout of a semiconductor device according to an embodiment of the present invention, and FIGS. 3A to 3I are cross-sectional views of devices for describing a method of manufacturing a semiconductor device according to an embodiment of the present invention.
도 3a를 참조하면, 반도체 기판(21)에 소자 분리막(22)을 형성하여 액티브 영역(active region)을 정의(define)한 후, 전체 구조상에 희생막(23)을 형성한다. 희생막(23) 상에 포토레지스트 패턴(20)을 형성하되, 포토레지스트 패턴(20)은 도 2에 나타나 있듯이, 게이트(256)를 형성하고자 하는 부분을 제외한 캐패시터 콘택(41)이 형성될 부분에 형성된다.Referring to FIG. 3A, the isolation layer 22 is formed on the semiconductor substrate 21 to define an active region, and then the sacrificial layer 23 is formed on the entire structure. A photoresist pattern 20 is formed on the sacrificial layer 23, and the photoresist pattern 20 is a portion where the capacitor contact 41 is to be formed except for a portion where the gate 256 is to be formed, as shown in FIG. 2. Is formed.
상기에서, 희생막(23)은 산화물이나 질화물로 형성하며, 그 증착 뚜께가 후속에서 형성되는 스페이서형 게이트의 높이 및 게이트 길이와 상관 관계를 가지므로 이에 맞추어 그 두께를 조절한다. 포토레지스트 패턴(20)의 폭(width)은 후속 캐패시터 콘택(41)이 형성될 부분, 즉 게이트(256) 사이의 거리가 된다. 따라서, 0.1㎛ 게이트 길이를 갖는 셀을 가정한다면, 캐패시터 콘택(41)의 폭은 0.15 내지 0.16㎛ 정도의 공간이 되므로, 기존의 장비로 포토레지스트 패턴(20)을 형성하는데 그만큼 부담이 줄어든다.In the above, the sacrificial film 23 is formed of an oxide or nitride, and the thickness of the sacrificial film 23 is correlated with the height and gate length of the spacer gate formed later. The width of the photoresist pattern 20 is the distance between the gate 256 and the portion where the next capacitor contact 41 is to be formed. Therefore, if a cell having a gate length of 0.1 μm is assumed, the width of the capacitor contact 41 becomes about 0.15 to 0.16 μm, so that the burden is reduced to form the photoresist pattern 20 with existing equipment.
도 3b를 참조하면, 포토레지스트 패턴(20)을 식각 마스크로한 식각 공정으로 희생막(32)을 패터닝한 후, 게이트 산화막(24), 도프트 폴리실리콘층(25) 및 금속층(26)을 순차적으로 형성한다. 금속층(26)은 WSix 혹은 W을 사용하여 형성한다.Referring to FIG. 3B, after the sacrificial layer 32 is patterned by an etching process using the photoresist pattern 20 as an etching mask, the gate oxide layer 24, the doped polysilicon layer 25, and the metal layer 26 are formed. Form sequentially. The metal layer 26 is formed using WSix or W.
도 3c를 참조하면, 전면 건식 식각 공정으로 금속층(26), 도프트 폴리실리콘층(25) 및 게이트 산화막(24))을 식각하여 패터닝된 희생막(23)의 좌우 측벽에 스페이서형 게이트(256)를 형성한다.Referring to FIG. 3C, a spacer gate 256 is formed on left and right sidewalls of a sacrificial layer 23 patterned by etching the metal layer 26, the doped polysilicon layer 25, and the gate oxide layer 24 by a front dry etching process. ).
상기에서, 게이트(256)의 길이가 되는 부분은 도프트 폴리실리콘층 및 금속층(25 및 26)의 증착 두께에 따라서 결정되므로, 0.1㎛ 이하로 증착을 실시하게 되면 게이트 길이도 그에 따라 0.1㎛ 이하로 형성된다. 현재, 박막 증착 공정의 균일성은 약 1%를 보장하고 있는 기술 수준이므로, 게이트 길이의 임계 치수 변화(CD Variation)는 약 1%로 보장할 수 있게 되는 장점을 가지고 있다. 또한, 스페이서형 게이트(256)의 상부 부분의 폭이 감소함으로써 비트라인 콘택 마스크(bit line contact mask)를 사용한 사진 공정시에 발생하는 오배열(misalign)에 대해서 그만큼의 디자인 룰 마진(design rule margin)을 확보할 수 있게 된다.In the above description, the length of the gate 256 is determined according to the deposition thicknesses of the doped polysilicon layer and the metal layers 25 and 26. Is formed. At present, since the uniformity of the thin film deposition process is a technology level that guarantees about 1%, the CD dimension of the gate length can be guaranteed to about 1%. In addition, the width of the upper portion of the spacer gate 256 is reduced, so that the design rule margin for misalignment occurring during the photolithography process using a bit line contact mask. ) Can be secured.
도 3d를 참조하면, 희생막(23)을 제거한 후, LDD 이온 주입으로 드레인 접합부(27a) 및 소오스 접합부(27b)를 형성하고, 게이트(256)를 포함한 전체 구조상에 제 1 산화막(28) 및 제 1 질화막(29)을 순차적으로 형성한다.Referring to FIG. 3D, after the sacrificial film 23 is removed, the drain junction 27a and the source junction 27b are formed by LDD ion implantation, and the first oxide film 28 and the entire structure including the gate 256 are formed. The first nitride film 29 is formed sequentially.
도 3e를 참조하면, 전면 건식 식각으로 제 1 질화막 및 제 1 산화막(29 및 28)을 식각하여 게이트(256) 측벽에 게이트 절연 스페이서(289)를 형성하여 셀 구조를 완성한다. 이후, 선택적 에피텍셜 성장(Selective Epitaxial Growth; SEG)법을 이용하여 반도체 기판(21)의 노출된 표면에만 폴리실리콘을 성장시켜 드레인 접합부(27a)에는 비트라인 콘택 랜딩 패드(31)를, 소오스 접합부(27b)에는 제 1 캐패시터 콘택 랜딩 패드(32)를 형성한다.Referring to FIG. 3E, the first nitride film and the first oxide films 29 and 28 are etched by dry etching to form a gate insulating spacer 289 on the sidewall of the gate 256 to complete the cell structure. Thereafter, polysilicon is grown only on the exposed surface of the semiconductor substrate 21 using the selective epitaxial growth (SEG) method, so that the bit line contact landing pad 31 is formed on the drain junction 27a and the source junction. A first capacitor contact landing pad 32 is formed at 27b.
상기에서, 스페이서형 게이트(256)의 윗부분이 곡면으로 형성된 부분에서 게이트 절연 스페이서(289) 형성을 위한 식각 공정시에 제 1 질화막(29)이 제거될 가능성이 있는데, 이는 후속의 비트라인 콘택 및 캐패시터 콘택이 형성될 부분이므로 보완을 해주어야 한다. 보완해주지 않을 경우 콘택 공정시 게이트(256)가 이 부분에서 노출되어 콘택 랜딩 패드와 단락될 가능성이 있다. 또한, 패드(31 및 32)를 형성하기 위한 선택적 에피텍셜 성장 공정을 과도하게 할 경우 패드(31 및 32)와 게이트(256)가 단락될 가능성이 높기 때문에 패드(31 및 32)가 게이트(256)의 높이보다 낮도록 형성한다.In the above, there is a possibility that the first nitride film 29 is removed during the etching process for forming the gate insulating spacer 289 in a portion where the upper portion of the spacer-type gate 256 is curved, which is a subsequent bit line contact and Capacitor contacts are to be formed and must be supplemented. If not complemented, there is a possibility that the gate 256 may be exposed in this portion and short-circuit with the contact landing pad during the contact process. In addition, when the selective epitaxial growth process for forming the pads 31 and 32 is excessive, the pads 31 and 32 may be gated 256 because there is a high possibility that the pads 31 and 32 and the gate 256 may be shorted. To be lower than the height.
도 3f를 참조하면, 하드 마스크층 역할을 하는 층으로 제 2 산화막(33) 및 제 2 질화막(34)을 패드(31 및 32)를 포함한 전체 구조상에 형성하고, 이로 인하여스페이서형 게이트(256)는 캡핑(capping)된다.Referring to FIG. 3F, the second oxide film 33 and the second nitride film 34 are formed on the entire structure including the pads 31 and 32 as a layer serving as a hard mask layer, thereby forming a spacer gate 256. Is capped.
도 3g를 참조하면, 제 2 질화막(34)을 포함한 전체 구조상에 제 1 층간 절연막(35)을 형성한다. 비트라인 콘택 마스크를 사용한 식각 공정으로 비트라인 콘택 랜딩 패드(31)의 표면이 노출되도록 제 1 층간 절연막(35), 제 2 질화막(34) 및 제 2 산화막(33)을 식각하여 비트라인 콘택(36)을 형성한다.Referring to FIG. 3G, a first interlayer insulating film 35 is formed on the entire structure including the second nitride film 34. The first interlayer insulating layer 35, the second nitride layer 34, and the second oxide layer 33 are etched to expose the surface of the bit line contact landing pad 31 by an etching process using a bit line contact mask. Form 36).
도 3h를 참조하면, 비트라인 콘택(36)을 통해 비트라인 콘택 랜딩 패드(31)와 연결되는 비트라인(37)을 형성한다. 비트라인(37)은 반도체 소자가 고속화되어 감에 따라 전도성이 우수한 금속을 주로 사용하며, 이때 하부층과의 이온 확산 현상을 방지하기 위하여 Ti/TiN 배리어 메탈층을 형성한다. 비트라인(37) 주변에는 비트라인(37)을 보호하기 위하여 질화물 등으로 캡핑층(38)을 형성한다.Referring to FIG. 3H, a bit line 37 connected to the bit line contact landing pad 31 is formed through the bit line contact 36. The bit line 37 mainly uses a metal having excellent conductivity as the semiconductor device speeds up, and forms a Ti / TiN barrier metal layer to prevent ion diffusion with the lower layer. A capping layer 38 is formed of nitride or the like around the bit line 37 to protect the bit line 37.
도 3i를 참조하면, 비트라인(37)을 포함한 전체 구조상에 제 2 층간 절연막(39)을 형성한다. 캐패시터 콘택 마스크를 사용한 식각 공정으로 제 1 캐패시터 콘택 랜딩 패드(32)의 표면이 노출되도록 제 2 층간 절연막(35), 제 1 질화막(29) 및 제 1 산화막(28)을 식각하여 캐패시터 콘택(41)을 형성하고, 선택적 에피텍셜 성장(SEG)법을 이용하여 제 1 캐패시터 콘택 랜딩 패드(32)의 표면에 폴리실리콘을 성장시켜 제 2 캐패시터 콘택 랜딩 패드(42)를 형성한다. 이후의 공정은 통상의 공정을 따라 반도체 장치를 완성시킨다.Referring to FIG. 3I, a second interlayer insulating film 39 is formed on the entire structure including the bit line 37. The second interlayer insulating film 35, the first nitride film 29, and the first oxide film 28 are etched so that the surface of the first capacitor contact landing pad 32 is exposed by an etching process using a capacitor contact mask, thereby causing the capacitor contact 41 to be exposed. ) And polysilicon is grown on the surface of the first capacitor contact landing pad 32 using the selective epitaxial growth (SEG) method to form the second capacitor contact landing pad 42. Subsequent processes complete the semiconductor device according to a conventional process.
상기에서, 캐패시터 콘택(41) 형성을 위한 식각 공정시 제 1 질화막(29) 및 제 1 산화막(28)이 스페이서 모양으로 식각되면서 스페이서형 게이트(256)를 보호하게 된다.In the above, during the etching process for forming the capacitor contact 41, the first nitride layer 29 and the first oxide layer 28 are etched in a spacer shape to protect the spacer gate 256.
상술한 바와 같이, 본 발명은 종래의 0.1㎛ 이하의 길이를 갖는 게이트를 형성할 때 생기는 포토레지스트 패턴의 브릿지 현상, 단선 및 균일성 불량(Non-uniformity)을 개선할 수 있으며, 게이트 건식 식각 시 게이트 라인의 쓰러지는 문제 및 균일성 불량을 극복할 수 있다. 또한, 스페이서형 게이트의 상부 부분의 폭이 감소함으로써 비트라인 콘택 마스크를 사용한 포토레지스트 패턴 형성시 발생하는 오배열에 대해서 그만큼의 디자인 룰 마진을 확보할 수 있게 된다.As described above, the present invention can improve the bridge phenomenon, disconnection, and non-uniformity of the photoresist pattern generated when forming a gate having a length of 0.1 μm or less, and during gate dry etching. Overcoming the gate line collapse problem and uniformity can be overcome. In addition, the width of the upper portion of the spacer-type gate is reduced, so that the design rule margin can be secured for the misalignment generated when the photoresist pattern is formed using the bit line contact mask.
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