KR100316052B1 - Method for forming NMOS type varactor - Google Patents
Method for forming NMOS type varactor Download PDFInfo
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- KR100316052B1 KR100316052B1 KR1019990064637A KR19990064637A KR100316052B1 KR 100316052 B1 KR100316052 B1 KR 100316052B1 KR 1019990064637 A KR1019990064637 A KR 1019990064637A KR 19990064637 A KR19990064637 A KR 19990064637A KR 100316052 B1 KR100316052 B1 KR 100316052B1
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- gate insulating
- insulating film
- forming
- varactor
- manufacturing
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- 238000000034 method Methods 0.000 title claims abstract description 18
- 238000004519 manufacturing process Methods 0.000 claims abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 11
- 239000012535 impurity Substances 0.000 claims abstract description 5
- 239000004020 conductor Substances 0.000 claims abstract description 4
- MWUXSHHQAYIFBG-UHFFFAOYSA-N Nitric oxide Chemical compound O=[N] MWUXSHHQAYIFBG-UHFFFAOYSA-N 0.000 claims description 30
- 238000009279 wet oxidation reaction Methods 0.000 claims description 7
- 238000000137 annealing Methods 0.000 claims description 2
- 238000004140 cleaning Methods 0.000 claims description 2
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 238000009825 accumulation Methods 0.000 description 3
- 229910002651 NO3 Inorganic materials 0.000 description 2
- NHNBFGGVMKEFGY-UHFFFAOYSA-N Nitrate Chemical compound [O-][N+]([O-])=O NHNBFGGVMKEFGY-UHFFFAOYSA-N 0.000 description 2
- 230000007423 decrease Effects 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/92—Capacitors with potential-jump barrier or surface barrier
- H01L29/93—Variable capacitance diodes, e.g. varactors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
- H01L21/02046—Dry cleaning only
- H01L21/02049—Dry cleaning only with gaseous HF
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Abstract
본 발명은 NMOS형 바렉터 제조 방법에 관한 것으로서, 특히 이 제조 방법은 반도체 기판의 n-웰 상부에 주파수 튜닝값을 증가시키기 위하여 질산화막으로 이루어진 게이트절연막을 형성하고, 그 위에 도전체로 이루어진 게이트전극을 형성한 후에 게이트절연막 에지 하부의 n-웰 내에 n+형 불순물이 주입된 소오스/드레인 접합을 형성한다. 그러므로, 본 발명은 게이트절연막의 두께를 변경하지 않고서도 NMOS형 바렉터의 주파수 튜닝 범위를 넓게 확보할 수 있다.The present invention relates to a method for manufacturing an NMOS type varactor, and in particular, the manufacturing method forms a gate insulating film made of an oxynitride film on the n-well of a semiconductor substrate to increase the frequency tuning value, and a gate electrode made of a conductor thereon. After forming the N-type impurity implanted into the n-well under the edge of the gate insulating layer, a source / drain junction is formed. Therefore, the present invention can secure a wide frequency tuning range of the NMOS type selector without changing the thickness of the gate insulating film.
Description
본 발명은 반도체 수동 소자 제조 방법에 관한 것으로서, 특히 역 바이어스(reverse bias) 다이오드인 NMOS형 바렉터(varactor) 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor passive device, and more particularly, to a method for manufacturing an NMOS type varactor, which is a reverse bias diode.
위상 동기 루프(phase locked loop)를 갖는 주파수 합성장치는 주로 무선 수신기에 사용되고 VCO(Voltage Controlled Oscillator)는 그 제작에 있어 가장 중요한 핵심 소자이다. 여기에서 가장 중요한 파라메터는 VCO의 주파수 튜닝 범위를 결정하는 바렉터이다.Frequency synthesizers with phase locked loops are commonly used in wireless receivers, and voltage controlled oscillators (VCOs) are the most important key components in their fabrication. The most important parameter here is the selector that determines the frequency tuning range of the VCO.
대개 VCO의 주파수 튜닝(tuning)은 실리콘 회로의 역 바이어스(reverse bias) 하의 pn 접합 다이오드나 디플렉션-인버젼(depletion-inversion) 영역의 모스 커패시터, GaAs의 쇼키트 다이오드의 가변 커패시턴스에 의해 행해진다. 일반적인 CMOS/BiCMOS 프로세스에서 pn접합 다이오드의 커패시턴스 튜닝 범위는 매우 좁아 VCO의 튜닝 범위로 사용하는데 어렵다.Usually, the tuning of the VCO is done by the pn junction diode under the reverse bias of the silicon circuit, the MOS capacitor in the deflation-inversion region, and the variable capacitance of the schottky diode in GaAs. . In a typical CMOS / BiCMOS process, the capacitance tuning range of the pn junction diode is very narrow, making it difficult to use as the tuning range of the VCO.
그러므로, 최근에는 축적-디플렉션(accumulation-depletion) 영역에서 NMOS형 구조에 기초한 바렉터 또는 pn 접합 다이오드 대신에 합성 커패시터를 이용하여 제한된 튜닝 범위를 해결하고자 하는 연구가 이루어지고 있다.Therefore, in recent years, research has been made to solve a limited tuning range by using a composite capacitor instead of a pn junction diode or a selector based on an NMOS type structure in an accumulation-depletion region.
또, 토포로지가 낮은 크기로 축소됨에 따라 최대 회로내 공급 전압과 최대 사용가능한 다이오드 역전압도 낮아지고 있다. 이로 인해 pn 접합 바렉터를 사용할 경우 컨트롤 전압이 2V이하면 가능한 주파수 튜닝 범위는 중심값에서 10%이하이다. 이 주파수 튜닝 범위는 일반적인 값에 비해 커패시턴스와 인덕턴스의 변화를 보상하기에 충분하지 않다.In addition, as topologies shrink to lower magnitudes, the maximum in-circuit supply voltage and the maximum usable diode reverse voltage are also lowered. Because of this, with a pn junction varistor, if the control voltage is below 2V, the possible frequency tuning range is less than 10% from the center. This frequency tuning range is not enough to compensate for changes in capacitance and inductance over typical values.
일반적으로, NMOS형 구조의 바렉터는 p형 기판 대신에 n-웰에 제조한다는 점을 제외하고는 n채널 MOSFET와 유사하다. 즉, 게이트전극은 캐패시터의 상부 플레이트노드로서의 역할을 하며, 게이트전극 아래의 웰(well)은 캐패시터의 하부 스토리지노드로서의 역할을 한다. 그리고 게이트 절연막은 절연체 역할을 한다.In general, an NMOS-type structure's collector is similar to an n-channel MOSFET except that it is fabricated in an n-well instead of a p-type substrate. That is, the gate electrode serves as the upper plate node of the capacitor, and the well under the gate electrode serves as the lower storage node of the capacitor. The gate insulating film serves as an insulator.
하지만, p-웰에 p채널 MOSFET를 사용하는 구조는 캐리어 이동 수가 때문에 질적으로 열악하다. 그러나, NMOS형 바렉터의 경우에는 Cmax(최대 커패시턴스)이며, Cmin(최소 커패시턴스)이 중심값에서 30%의 튜닝 범위를 확보할 수 있는 이점이 있어 PMOS형 바렉터보다는 이를 많이 사용하고 있다.However, the structure using p-channel MOSFETs in p-wells is poor in quality due to the number of carrier shifts. However, the NMOS type selector is Cmax (maximum capacitance), and Cmin (minimum capacitance) has the advantage of securing a tuning range of 30% from the center value, so it is used more than the PMOS type selector.
그러나, NMOS형 바렉터의 경우 더 넓은 튜닝 범위를 확보하기 위해서는 게이트 절연막인 산화막의 두께를 더 낮추어야 하나, 소자의 전기적 특성에 맞추어 설계된 n-웰 농도, 산화막의 두께등을 다시 제조 공정시 변경한다는 것은 매우 어려운 일이다.However, in order to secure a wider tuning range, the NMOS type selector needs to further reduce the thickness of the oxide film, which is a gate insulating film, but changes the n-well concentration, oxide thickness, etc., designed for the electrical characteristics of the device, during the manufacturing process. It is very difficult.
본 발명의 목적은 상기와 같은 종래 기술의 문제점을 해결하기 위하여 습식 산화법에 의한 게이트절연막대신에 질산화막으로 대체하므로써 더 넓은 주파수 튜닝 범위를 확보할 수 있어 소자의 전기적 특성을 높일 수 있는 NMOS형 바렉터 제조 방법을 제공하는데 있다.An object of the present invention is to replace the gate insulating film by the wet oxidation method in order to solve the problems of the prior art as described above by replacing the nitric oxide film with a wider frequency tuning range can be secured NMOS type bar to improve the electrical characteristics of the device It is to provide a method of manufacturing a collector.
도 1은 본 발명에 따른 질산화(NO) 게이트절연막을 갖는 반도체 수동소자 NMOS형 바렉터 제조 방법을 설명하기 위한 단면도,1 is a cross-sectional view for explaining a method for manufacturing a semiconductor passive device NMOS type varactor having a nitric oxide (NO) gate insulating film according to the present invention;
도 2는 본 발명의 질산화 게이트절연막을 갖는 바렉터와 종래 습식 산화에 의한 게이트절연막을 갖는 바렉터의 전기적 특성을 비교한 그래프.2 is a graph comparing the electrical characteristics of a varactor having a nitrate gate insulating film of the present invention and a varactor having a gate insulating film by conventional wet oxidation.
* 도면의 주요 부분에 대한 부호의 설명 *Explanation of symbols on the main parts of the drawings
10: 반도체 기판10: semiconductor substrate
12: n-웰12: n-well
14: 질산화 게이트절연막14: nitric oxide gate insulating film
16: 게이트전극16: gate electrode
18: 소오스/드레인 접합18: source / drain junction
상기 목적을 달성하기 위하여 본 발명은 반도체 수동소자 바렉터 제조 방법에 있어서, 반도체 기판의 n-웰 상부에 주파수 튜닝값을 증가시키기 위하여 질산화막으로 이루어진 게이트절연막을 형성하는 단계와, 게이트절연막 상부에 도전체로 이루어진 게이트전극을 형성하는 단계와, 게이트절연막 에지 하부의 n-웰 내에 n+형 불순물이 주입된 소오스/드레인 접합을 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method for manufacturing a semiconductor passive device varactor, the method comprising: forming a gate insulating film made of an oxynitride film to increase a frequency tuning value on an n-well of a semiconductor substrate; Forming a gate electrode made of a conductor, and forming a source / drain junction in which n + -type impurities are implanted into the n-well under the edge of the gate insulating layer.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세하게 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 1은 본 발명에 따른 질산화(NO) 게이트절연막을 갖는 반도체 수동소자 NMOS형 바렉터 제조 방법을 설명하기 위한 단면도이다.1 is a cross-sectional view for explaining a method for manufacturing a semiconductor passive device NMOS type varactor having a nitric oxide (NO) gate insulating film according to the present invention.
이를 참조하면, 본 발명의 NMOS형 바렉터 제조 공정은 반도체 기판으로서 실리콘기판(10)에 n-웰(12)을 형성한다. 그리고, 게이트절연막 제조 공정을 진행하기에 앞서 N2분위기에서 HF 세정 공정을 진행하여 기판의 자연 산화막을 제거한다.Referring to this, the NMOS type varactor manufacturing process of the present invention forms the n-well 12 in the silicon substrate 10 as a semiconductor substrate. In addition, the HF cleaning process is performed in an N 2 atmosphere prior to the gate insulating film manufacturing process to remove the native oxide film of the substrate.
그리고, 실리콘기판(10)의 n-웰(12) 표면에 주파수 튜닝값을 증가시키기 위하여 질산화막(NO)으로 이루어진 게이트절연막(14)을 형성한다.In order to increase the frequency tuning value on the surface of the n-well 12 of the silicon substrate 10, a gate insulating film 14 made of a nitric oxide film NO is formed.
여기서, 질산화막(NO) 형성은 700℃∼800℃에서 습식 산화를 진행하고 800℃∼900℃에서 NO 가스를 공급하면서 어닐링(annealing)한다. 이때, 어닐링 공정은 10분∼30분동안 진행하고, NO 가스의 공급은 0.2l∼1l이다.Here, the nitric oxide (NO) formation is subjected to wet oxidation at 700 ° C to 800 ° C and annealed while supplying NO gas at 800 ° C to 900 ° C. At this time, the annealing process proceeds for 10 to 30 minutes, and the supply of NO gas is 0.2l to 1l.
이로 인해, 본 발명은 습식 산화 공정만을 진행하여 게이트절연막을 형성했을때보다 더 넓은 주파수 튜닝 범위를 확보할 수 있다.For this reason, the present invention can secure a wider frequency tuning range than when the gate insulating film is formed only by the wet oxidation process.
그 다음, 상기 게이트절연막(14) 상부에 도전체로서 도프트 폴리실리콘을 증착하고 이를 패터닝하여 게이트전극(16)을 형성한다.Next, doped polysilicon is deposited on the gate insulating layer 14 as a conductor and patterned to form a gate electrode 16.
그리고, 상기 게이트전극(16)에 맞추어 게이트절연막(14)을 패터닝한다.The gate insulating film 14 is patterned according to the gate electrode 16.
이어서, n+ 불순물을 이온 주입하여 게이트절연막(14) 에지 하부의 n-웰(12) 내에 n+형 불순물이 주입된 소오스/드레인 접합(18)을 형성한다.Next, n + impurities are ion-implanted to form a source / drain junction 18 into which n + -type impurities are implanted in the n-well 12 under the edge of the gate insulating layer 14.
상술한 제조 공정에 따라 완성된 본 발명의 NMOS형 바렉터의 동작은 다음과 같다.The operation of the NMOS type varactor of the present invention completed according to the above-described manufacturing process is as follows.
즉, 게이트전극(16)에 플랫밴드(flat band) 전압 이상으로 인가되면 실리콘 기판 표면에는 소오스/드레인 접합(18)에서 공급된 전자에 의해 축적된다. 이때 게이트전극 측면의 커패시턴스는 게이트절연막의 커패시턴스값이다. 그리고, 게이트전극의 전압이 플랫밴드 전압쪽으로 감소함에 따라 실리콘 기판에는 전자 축적이 감소하게 되고 플랫밴드에서는 챠지-프리(charge-free)가 되고 그 이후에는 디플렉션(depletion)이 일어난다. 깊은 축적에서 강한 디플렉션까지 커패시턴스는 최대값(Cmax)에서 최소값(Cmin)으로 변동된다. 축적시 전체 커패시턴스는 게이트절연막의 커패시턴스와 기판에서의 커패시턴스의 결합으로 나타난다.That is, when applied to the gate electrode 16 above the flat band voltage (flat band) voltage is accumulated on the surface of the silicon substrate by the electrons supplied from the source / drain junction 18. At this time, the capacitance of the side of the gate electrode is the capacitance of the gate insulating film. As the voltage of the gate electrode decreases toward the flat band voltage, electron accumulation decreases in the silicon substrate, becomes charge-free in the flat band, and then deflation occurs. From deep accumulation to strong reflection, the capacitance varies from the maximum value Cmax to the minimum value Cmin. During accumulation, the total capacitance is represented by the combination of the capacitance of the gate insulating film and the capacitance in the substrate.
그러므로, 본 발명은 고유전율의 질화물질을 추가 사용하여 질산화막으로 게이트절연막을 형성하기 때문에 최대 커패시턴스와 최소 커패시턴스의 중심에서 ±30%이상의 주파수 튜닝 범위를 확보할 수 있다.Therefore, in the present invention, since the gate insulating film is formed of the nitric oxide film by further using a high dielectric constant nitride material, a frequency tuning range of ± 30% or more can be secured at the center of the maximum capacitance and the minimum capacitance.
도 2는 본 발명의 질산화 게이트절연막을 갖는 바렉터와 종래 습식 산화에의한 게이트절연막을 갖는 바렉터의 전기적 특성을 비교한 그래프이다.2 is a graph comparing the electrical characteristics of the varactor having the nitrate gate insulating film of the present invention and the varactor having the gate insulating film by conventional wet oxidation.
도 2를 참조하면, 종래 900℃에서 습식 산화공정을 진행하여 게이트절연막을 형성했을 때 전체 커패시턴스는 최대 및 최소 커패시턴스의 중심값에서 ±25% 정도 확보할 수 있다. 반면에 본 발명은 800℃∼900℃에서 질산화 공정으로 게이트절연막을 형성함에 따라 전체 커패시턴스가 상기 중심값에서 ±30% 이상을 확보할 수 있어 종래보다 약 10% 이상의 VCO의 주파수 튜닝 범위를 얻을 수 있다.Referring to FIG. 2, when the gate insulating layer is formed by performing a wet oxidation process at 900 ° C., the total capacitance may be about ± 25% from the center of the maximum and minimum capacitances. On the other hand, according to the present invention, as the gate insulating film is formed by nitrification at 800 ° C. to 900 ° C., the total capacitance can secure ± 30% or more from the center value, thereby obtaining a frequency tuning range of about 10% or more of the VCO. have.
즉, 전기적 두께가 30Å인 본 발명의 질산화 게이트절연막과 종래 습식산화 게이트절연막의 바이어스 전압대 커패시턴스를 비교하면, 본 발명의 게이트절연막이 종래에 비해 낮은 바이어스 전압하에서 높은 커패시턴스를 얻을 수 있어 더 넓은 주파수 튜닝 범위를 조정할 수 있다.That is, comparing the bias voltage vs. capacitance of the nitride oxide gate insulating film of the present invention having an electrical thickness of 30 Hz and the conventional wet oxide gate insulating film, the gate insulating film of the present invention can obtain a higher capacitance at a lower bias voltage than the conventional wider frequency. The tuning range can be adjusted.
상기한 바와 같이 본 발명은, 게이트절연막의 두께를 변경하지 않고서도 NMOS형 바렉터의 주파수 튜닝 범위를 넓게 확보할 수 있어 반도체장치의 전기적 특성을 크게 향상시킬 수 있는 효과가 있다.As described above, the present invention can secure a wide frequency tuning range of the NMOS type selector without changing the thickness of the gate insulating film, so that the electrical characteristics of the semiconductor device can be greatly improved.
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