KR100316016B1 - Method for fabricating semiconductor device - Google Patents
Method for fabricating semiconductor device Download PDFInfo
- Publication number
- KR100316016B1 KR100316016B1 KR1019980022331A KR19980022331A KR100316016B1 KR 100316016 B1 KR100316016 B1 KR 100316016B1 KR 1019980022331 A KR1019980022331 A KR 1019980022331A KR 19980022331 A KR19980022331 A KR 19980022331A KR 100316016 B1 KR100316016 B1 KR 100316016B1
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- KR
- South Korea
- Prior art keywords
- semiconductor device
- bpsg film
- capacitor
- peripheral circuit
- circuit region
- Prior art date
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Classifications
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/09—Manufacture or treatment with simultaneous manufacture of the peripheral circuit region and memory cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
Abstract
본 발명은 셀영역과 주변회로영역간의 단차를 완화시키도록 한 반도체소자 제조 방법에 관한 것으로서, 캐패시터가 형성된 기판 전면에 BPSG막을 형성하는 단계, 상기 BPSG막상에 상기 캐패시터의 상부를 노출시키고 상기 주변영역 중 상기 캐패시터와 동시에 형성된 부분의 상부를 노출시키는 마스크패턴을 형성하는 단계, 및 상기 마스크패턴을 이용하여 상기 노출된 부분의 상기 BPSG막을 소정 두께로 식각하는 단계를 포함하여 이루어진다.The present invention relates to a method of fabricating a semiconductor device to mitigate the step between a cell region and a peripheral circuit region, the method comprising: forming a BPSG film on an entire surface of a substrate on which a capacitor is formed; exposing an upper portion of the capacitor on the BPSG film and surrounding the peripheral area; Forming a mask pattern exposing an upper portion of a portion simultaneously formed with the capacitor, and etching the BPSG film of the exposed portion to a predetermined thickness by using the mask pattern.
Description
본 발명은 반도체소자 제조 방법에 관한 것으로, 특히 셀영역과 주변회로영역간의 단차를 완화시키도록 한 반도체소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device to mitigate a step between a cell region and a peripheral circuit region.
최근에 반도체 제조 공정 중 커패시터를 형성하는 방법에 따라 셀영역의 토폴로지(Topology)가 주변회로영역에 비해 지속적으로 높아지고 있으며, 이러한 현상은 소자의 고집적화에 따라 가속화되고 있다.Recently, according to the method of forming a capacitor during the semiconductor manufacturing process, the topology of the cell region is continuously increased compared to the peripheral circuit region, and this phenomenon is accelerated by the high integration of devices.
도 1은 종래기술에 의한 반도체소자 제조시 발생된 셀영역과 주변회로영역간의 단차를 도시한 것으로, 셀영역의 커패시터 단차에 기인한 셀영역과 주변회로영역간의 단차로 인해 후속층 형성공정시의 공정 마진이 감소하게 된다. 이를 해결하기 위해 CMP(chemical mechanical polishing)와 같이 단차 완화를 위한 식각공정 등의 여러 가지 대안이 제안되었으나, 불순물 입자의 발생이나 적용시의 효과 미흡 등의 이유로 실제 적용에는 문제가 있다.FIG. 1 illustrates a step between a cell region and a peripheral circuit region generated when a semiconductor device is manufactured according to the prior art. In the subsequent layer forming process, the step between the cell region and the peripheral circuit region due to a capacitor step of the cell region is shown. Process margins will decrease. In order to solve this problem, various alternatives such as an etching process for mitigating steps, such as chemical mechanical polishing (CMP), have been proposed. However, there are problems in the practical application due to generation of impurity particles or insufficient effect in application.
본 발명은 상기한 문제를 해결하기 위한 것으로, 단차가 높은 부분을 선택적으로 식각하여 전체적인 단차를 완화시켜 셀영역과 주변회로영역간의 단차를 완화시키는데 적합한 반도체소자 제조 방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a method of manufacturing a semiconductor device suitable for alleviating a step between a cell region and a peripheral circuit region by selectively etching a portion having a high step to alleviate the overall step.
도 1은 종래기술에 의한 반도체소자 제조시 발생된 셀과 주변회로간의 단차를 도시한 도면.1 is a view showing a step between a cell and a peripheral circuit generated when manufacturing a semiconductor device according to the prior art.
도 2 및 도 3은 본 발명에 적용되는 셀영역 레티클패턴 및 주변회로영역 레티클패턴을 각각 나타낸 도면.2 and 3 are a view showing a cell region reticle pattern and a peripheral circuit region reticle pattern respectively applied to the present invention.
도 4는 본 발명의 실시예에 의한 반도체소자 제조 방법을 나타낸 도면.4 is a view showing a semiconductor device manufacturing method according to an embodiment of the present invention.
상기 목적을 달성하기 위한 본 발명의 반도체소자 제조 방법은 셀영역과 주변회로영역을 갖는 반도체소자 제조방법에 있어서, 캐패시터가 형성된 기판 전면에 BPSG막을 형성하는 단계, 상기 BPSG막상에 상기 캐패시터의 상부를 노출시키고 상기 주변회로영역 중 상기 캐패시터와 동시에 형성된 부분의 상부를 노출시키는 마스크패턴을 형성하는 단계, 및 상기 마스크패턴을 이용하여 상기 노출된 부분의 상기 BPSG막을 소정 두께로 식각하는 단계를 포함하여 이루어짐을 특징으로 한다.In the semiconductor device manufacturing method of the present invention for achieving the above object, in the semiconductor device manufacturing method having a cell region and a peripheral circuit region, forming a BPSG film on the entire surface of the substrate on which the capacitor is formed, the upper portion of the capacitor on the BPSG film Forming a mask pattern that exposes and exposes an upper portion of a portion formed simultaneously with the capacitor in the peripheral circuit region, and etching the BPSG film of the exposed portion to a predetermined thickness by using the mask pattern. It is characterized by.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
먼저, 종래와 동일한 공정을 통해 커패시터 등과 같은 소자를 형성한 후, 그전면에 절연막을 형성한다. 대부분의 DRAM 소자에서는 상기 절연막으로 5000∼7000Å두께의 BPSG막(Boro Phospho Silicate Glass)을 증착하고 후속 열처리를 통하여 플로우(flow)시킨다.First, an element such as a capacitor is formed through the same process as in the prior art, and then an insulating film is formed on the entire surface thereof. In most DRAM devices, a BPSG film (Boro Phospho Silicate Glass) having a thickness of 5000 to 7000 으로 is deposited with the insulating film and flowed through subsequent heat treatment.
여기서, 본 발명은 BPSG막 형성 후에 단차 완화를 위한 사진공정과 식각공정 후 BPSG막을 일부 제거해야 하므로 종래보다 2000∼5000Å 두께만큼 더 높게 증착한 후, 즉 7000∼12000Å의 두께로 증착한 다음 열처리하여 플로우시킨다.Here, since the BPSG film needs to be partially removed after the BPSG film formation and the etching process for the step difference after forming the BPSG film, it is deposited by a thickness of 2000 to 5000∼ higher than that of the prior art, that is, it is deposited to a thickness of 7000 to 12000Å and then heat treated. Flow.
이어서 생산 다이(production die)내의 패턴은, 도 2(셀영역의 레티클패턴) 및 도 3(주변회로영역의 레티클패턴)에 도시한 대로 설계하고, 스크라이브 라인(scribe line)은 레티클 제작에 필요한 패턴과 웨이퍼 정렬에 필요한 표시를 제외한 모든 지역을 크롬층으로 덮어 마스크 및 식각공정에서 식각되지 않게 한다.Subsequently, the pattern in the production die is designed as shown in Fig. 2 (reticle pattern of the cell region) and Fig. 3 (reticle pattern of the peripheral circuit region), and the scribe line is a pattern necessary for manufacturing the reticle. All areas except the markings required for wafer and wafer alignment are covered with a chromium layer to prevent them from being etched during the masking and etching process.
예컨대, 도 2의 좌측에 도시된 바와 같이, 다수의 작은 사각형 모양의 스토리지노드 패턴의 끝부분(점선)과 일치하도록 우측 도면에 도시된 바와 같이 셀영역의 스토리지노드 패턴은 열어주고 나머지 부분은 크롬층으로 덮는다.For example, as shown in the left side of FIG. 2, the storage node pattern of the cell area is opened and the remaining part is chrome as shown in the right figure so as to match the ends (dotted lines) of the plurality of small square-shaped storage node patterns. Cover with layers
그리고, 도 3의 좌측에 나타낸 주변회로영역의 빗금친 부분이 스토리지노드 패턴 형성시 같이 형성되었다면 빗금친 부분의 끝부분(점섬)과 일치하도록 우측 도면과 같이 빗금친 부분은 열어주고 나머지 부분은 크롬층으로 덮는다.If the hatched portion of the peripheral circuit region shown in the left side of FIG. 3 is formed together when the storage node pattern is formed, the hatched portion is opened as shown in the right drawing to match the end portion (dotted dot) of the hatched portion and the remaining portion is chromed. Cover with layers
상술한 것처럼, 도 2 및 도 3에 도시된 레티클패턴은 상대적으로 단차가 높은 부분, 예컨대, 스토리지노드패턴, 주변회로영역의 소자패턴이 형성된 부분은 노출시키고 이들 패턴들 사이의 상대적으로 단차가 낮은 부분은 덮는 형태로 형성된다.As described above, the reticle pattern illustrated in FIGS. 2 and 3 exposes a portion having a relatively high step, for example, a storage node pattern and a portion where a device pattern of a peripheral circuit region is formed, and has a relatively low step between these patterns. The part is formed in a covering form.
다음으로, 도 2 및 도 3에 도시된 레티클패턴을 이용하여 노출된 BPSG막을 식각하는바, 식각방법으로는 건식방식과 습식방식이 있으나, 현재 건식방식은 디펙트(defect) 문제와 공정의 비용증가로 인해 장점보다는 단점이 많으므로 습식식각을 이용하는 것이 바람직하겠다. 즉, NH4F, HF를 주성분으로 하는 20:1 BOE를 사용하여 단차가 높은 지역의 BPSG막 부분을 소정 두께만큼, 예를 들면 2000Å∼5000Å, 특히 바람직하게는 3000∼4000Å 두께로 식각하여 단차를 완화시킨다.Next, the exposed BPSG film is etched using the reticle patterns shown in FIGS. 2 and 3, but the etching method includes a dry method and a wet method. However, the dry method currently has a defect problem and a process cost. Due to the increase in the number of disadvantages rather than advantages, it is preferable to use wet etching. In other words, using a 20: 1 BOE mainly composed of NH 4 F and HF, the BPSG membrane portion of the region having high step height is etched by a predetermined thickness, for example, 2000 mm to 5000 mm, particularly preferably 3000 to 4000 mm thick. To alleviate
도 4는 본 발명을 실제로 적용한 일예를 나타낸 것으로, 10000Å정도의 단차를 가진 소자에서 BPSG의 증착 두께를 종래의 5500Å에 3000Å을 더한 8500Å으로 하여 형성한 후, 습식식각에 의해 3000Å 정도 식각한 상태를 나타낸 것이다. 여기서, 약 3000Å의 단차가 완화되고 셀영역과 주변회로영역간의 단차가 5500Å정도로 양호하게 나타난 것을 알 수 있다.Figure 4 shows an example of the actual application of the present invention, after forming the deposition thickness of the BPSG in the device having a step of about 10000Å to 8500Å plus 3000Å of conventional 5500 5, after etching 3000Å by wet etching It is shown. Here, it can be seen that the step of about 3000 mW is alleviated and the step between the cell area and the peripheral circuit area is about 5500 mW.
이상에서 설명한 본 발명은 전술한 실시예 및 첨부된 도면에 의해 한정되는 것이 아니고, 본 발명의 기술적 사상을 벗어나지 않는 범위 내에서 여러 가지 치환, 변형 및 변경이 가능하다는 것이 본 발명이 속하는 기술분야에서 통상의 지식을 가진 자에게 있어 명백할 것이다.The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes are possible in the art without departing from the technical spirit of the present invention. It will be apparent to those of ordinary knowledge.
상기와 같이 본 발명에 의하면, 셀단차 완화용의 새로운 레티클을 사용하여 셀영역과 주변회로영역간의 단차를 완화하여 이후 공정의 마진을 향상시킬 수 있다.As described above, according to the present invention, the step between the cell region and the peripheral circuit region may be alleviated by using a new reticle for alleviating the cell step difference, thereby improving the margin of the subsequent process.
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980022331A KR100316016B1 (en) | 1998-06-15 | 1998-06-15 | Method for fabricating semiconductor device |
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| KR1019980022331A KR100316016B1 (en) | 1998-06-15 | 1998-06-15 | Method for fabricating semiconductor device |
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| KR100316016B1 true KR100316016B1 (en) | 2002-06-20 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US9761591B2 (en) | 2015-09-08 | 2017-09-12 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device including edge chip and related device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9761591B2 (en) | 2015-09-08 | 2017-09-12 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device including edge chip and related device |
| US9935111B2 (en) | 2015-09-08 | 2018-04-03 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device including edge chip and related device |
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