KR100313500B1 - Tape carrier package and manufacturing method thereof - Google Patents
Tape carrier package and manufacturing method thereof Download PDFInfo
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- KR100313500B1 KR100313500B1 KR1019980063530A KR19980063530A KR100313500B1 KR 100313500 B1 KR100313500 B1 KR 100313500B1 KR 1019980063530 A KR1019980063530 A KR 1019980063530A KR 19980063530 A KR19980063530 A KR 19980063530A KR 100313500 B1 KR100313500 B1 KR 100313500B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49572—Lead-frames or other flat leads consisting of thin flexible metallic tape with or without a film carrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Abstract
본 발명은 테이프 캐리어 패키지 및 그 제조방법에 관한 것으로, 티씨피 테이프의 상면에 인너리드와 오픈 패드를 형성시키고, 이 오픈 패드와 칩의 범프를 전기적으로 연결시키도록 전도성 접착막을 그 사이에 놓고 열압착함으로써, 칩 사이즈의 소형화 및 파인 피치가 가능하고 전기적 특성을 향상시키게 한 것이다.The present invention relates to a tape carrier package and a method of manufacturing the same, wherein an inner lead and an open pad are formed on an upper surface of a TPC tape, and a conductive adhesive film is disposed therebetween to electrically connect the open pad and the bump of the chip. By pressing, the chip size can be reduced in size and fine pitch, and the electrical characteristics are improved.
Description
본 발명은 반도체 패키지에 관한 것으로, 칩 사이즈의 소형화 및 파인 피치가 가능하고 전기적 특성을 향상시킨 테이프 캐리어 패키지 및 그 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and to a tape carrier package capable of miniaturizing chip size and fine pitch and improving electrical characteristics, and a method of manufacturing the same.
일반적으로 테이프 캐리어 패키지(Tape Carrier Package;TCP, 이하 티씨피라 칭한다)는 절연 폴리마이드 필름(polymide film)위에 메탈 패턴(metal pattern)이 형성된 티씨피 테이프(TCP tape)와, 메탈 범프(metal bump)된 아이씨 칩(IC chip)을 본딩하는 접속 기술 또는 패키징방법을 말하며, 상기 티씨피 테이프는 보통의 패키지공정에서 사용되는 리드 프레임(lead frame)과 같은 역할을 한다.In general, a Tape Carrier Package (TCP) is referred to as a TCP tape on which a metal pattern is formed on an insulating polymide film, and a metal bump. Refers to a connection technology or packaging method for bonding the IC chip, the TPC tape serves as a lead frame used in the normal packaging process.
첨부한 도 1은 종래의 테이프 캐리어 패키지의 구성을 도시한 종단면도로서, 종래의 티씨피의 제조공정은 웨이퍼 칩 위의 각 패드에 인너리드본딩을 위하여 일정한 높이의 금(Au)을 도금하는 공정인 범핑(bumping)공정과, 웨이퍼를 낱개의 다이(die)로 절단하는 소잉(sawing)공정과, 전기적인 도전 경로를 형성하기 위해 칩(5)의 범프(6)와 티씨피 테이프의 리드(3)를 강한 압력 및 열로 접착시키는 인너리드본딩(inner lead bonding)공정과, 인너리드본딩된 칩(5)을 외부로 부터 보호하기 위하여 플라스틱 수지로 밀봉하는 포팅(potting)공정과, 포팅된 제품의 표면에 제조일자 및 제품명을 인쇄하는 마킹(marking)공정으로 진행된다.1 is a longitudinal cross-sectional view showing the configuration of a conventional tape carrier package, the conventional manufacturing process of the TPC is a process of plating gold (Au) of a constant height for each inner pad bonding on each pad on the wafer chip Phosphorus bumping process, sawing process of cutting the wafer into individual dies, and bump 6 of chip 5 and lead of TPC tape to form an electrically conductive path ( 3) Inner lead bonding process that bonds 3) with strong pressure and heat, Potting process that seals the inner lead bonded chip 5 with plastic resin to protect it from the outside, and potted products The marking process of printing the date of manufacture and the product name on the surface of the process is carried out.
종래의 티씨피 테이프를 제조하는 공정을 설명하면 다음과 같다.Referring to the process of manufacturing a conventional TPC tape as follows.
베이스 필름(base film)(1)에 디바이스 홀(device hole)(1a)을 형성하고 접착제(2)를 사용하여 동박(copper)(3)을 접합시킨 후 인너리드의 형성을 위하여 에칭을 실시한다.A device hole 1a is formed in the base film 1, the copper foil 3 is bonded using an adhesive 2, and etching is performed to form an inner lead. .
이후 상기 디바이스 홀(1a)을 제외한 부분에 설계도면에 따라 최종 패턴 형성된 동박(3)을 보호하고 외부 이물질에 의한 쇼트방지를 목적으로 솔더 레지시트(solder resist)(4)를 도포하고, 인너리드에 주석(Sn)이나 금(Au)을 도금한다.Afterwards, a solder resist sheet 4 is applied to parts except the device hole 1a for the purpose of protecting the copper foil 3 formed with the final pattern according to the design drawing and preventing short circuit caused by external foreign matter. Tin (Sn) or gold (Au) is plated on it.
그러나, 상기와 같은 종래의 티씨피 테이프는 도 2에 도시한 바와 같이, 파인 피치(fine pitch)를 하기 위해서는 리드(3)의 폭이 좁아져야 하는데, 리드(3)의 폭을 좁게 하면 리드(3)의 세기가 약해지기 때문에 파인 피치가 불가능한 문제점이 있었다.However, in the conventional TPC tape as described above, the width of the lead 3 should be narrowed in order to have a fine pitch. When the width of the lead 3 is narrowed, the lead ( There was a problem that the fine pitch is impossible because the strength of 3) is weakened.
따라서, 칩 사이즈의 소형화가 어려웠으며, 테이프의 인너리드(3) 부위가 디바이스 홀(1a)에 의해 노출되어 있으므로 테이프 제조 후 검사 공정이나 공정을 진행하기 위해 릴(reel)에 감기거나 풀릴 때 리드(3)가 구부러지는 현상이 발생하였고, 인너리드본딩 공정 진행시 리드(3)의 폭과 두께가 얇아 작은 충격에도 리드(3)가 부러지는 리드 브로큰(lead broken) 불량이 많이 발생하는 문제점이 있었다.Therefore, it is difficult to miniaturize the chip size, and since the inner lead 3 portion of the tape is exposed by the device hole 1a, the lead when the coil is wound or unwound for the inspection process or the process after the tape is manufactured. (3) is a bent phenomenon, and during the inner lead bonding process, the width and thickness of the lead (3) is thin, a problem that leads broken lead lead (broken lead) failure a lot occurs even in a small impact there was.
또한, 공정 진행 중 전도성 이물질이 본딩되는 리드(3)에 부착되어 전기적인 불량을 유발할 가능성이 있었고, 테이프 제조시 리드(3)를 형성하기 위한 에칭공정에서 불량이 발생하는 문제점이 있었다.In addition, there was a possibility that the conductive foreign matter is attached to the lead (3) bonded during the process, causing electrical defects, there was a problem that a defect occurs in the etching process for forming the lead (3) during tape manufacturing.
따라서, 본 고안은 상기와 같은 문제점을 해결하기 위해 안출한 것으로서, 파인 피치가 가능하여 칩 사이즈의 소형화를 이룰 수 있고, 리드 벤트(lead bent), 리드 크랙(lead crack) 등의 문제점을 해결하며 전기적 특성을 향상시킨 테이프 캐리어 패키지 및 그 제조방법을 제공하는데 그 목적이 있다.Therefore, the present invention has been made to solve the above problems, fine pitch is possible to achieve the miniaturization of the chip size, and to solve the problems such as lead bent (lead bent), lead crack (lead crack) It is an object of the present invention to provide a tape carrier package having improved electrical characteristics and a method of manufacturing the same.
도 1은 종래의 테이프 캐리어 패키지의 구성을 도시한 단면도.1 is a cross-sectional view showing the configuration of a conventional tape carrier package.
도 2는 종래의 티씨피 테이프를 도시한 평면도.Figure 2 is a plan view showing a conventional TPC tape.
도 3은 본 발명의 테이프 캐리어 패키지의 구성을 분리하여 도시한 단면도.Figure 3 is a cross-sectional view showing a separate configuration of the tape carrier package of the present invention.
도 4는 본 발명의 테이프 캐리어 패키지를 도시한 단면도.4 is a cross-sectional view illustrating a tape carrier package of the present invention.
도 5는 본 발명의 티씨피 테이프를 도시한 평면도.5 is a plan view showing a TPC tape of the present invention.
***도면의 주요 부분에 대한 부호의 설명****** Description of the symbols for the main parts of the drawings ***
10; 베이스 필름 11; 접착제10; Base film 11; glue
12; 동박 13; 오픈 패드12; Copper foil 13; Open pad
14; 솔더 레지시트14; Solder resist sheet
이와 같은 본 발명의 목적을 달성하기 위하여, 베이스 필름의 상면에 부착된 동박을 에칭하여 서로 엇갈리게 배열되는 오픈 패드와 이들 오픈 패드를 내부에서 전기적으로 연결하는 인너리드가 형성된 티씨피 테이프와, 상기 오픈 패드를 제외하고 인너리드를 포함한 동박 상면에 도포되는 솔더 레지스트와, 상기 오픈 패드에 접촉되는 범프가 형성된 반도체 칩과, 상기 오픈 패드와 칩의 범프를 전기적으로 연결시키는 이방전도성 접착막과, 상기 범프와 오픈 패드가 접촉하는 일정 면적을 봉지재로 덮는 포팅부로 구성되는 것을 특징으로 하는 테이프 캐리어 패키지가 제공된다.In order to achieve the object of the present invention, the TPS tape is formed of an open pad that is arranged alternately with each other by etching the copper foil attached to the upper surface of the base film and the inner lead electrically connected to the open pad, and the open A solder resist applied to the upper surface of the copper foil including the inner lead except the pad, a semiconductor chip having bumps in contact with the open pads, an anisotropic conductive adhesive film electrically connecting the open pads and the bumps of the chip, and the bumps And a tape carrier package is provided, comprising a potting portion covering a predetermined area in contact with the open pad with an encapsulant.
상기와 같은 본 발명의 목적을 달성하기 위한 제조 방법으로서 베이스 필름의 상면에 동박을 부착시키고, 상기 동박을 에칭하여 서로 엇갈리게 배열되는 오픈 패드와 이들 오픈 패드를 내부에서 전기적으로 연결하는 인너리드를 형성하고, 상기 오픈 패드를 제외하고 인너리드를 포함하여 동박전체를 보호하기 위하여 솔더 레지시트를 도포하고, 상기 오픈 패드를 도금하여 티씨피 테이프를 제조하는 단계와, 상기 티씨피 테이프의 오픈 패드와 칩의 범프 사이에 전도성 접착막을 접착한 후 열압착하여 오픈 패드에 칩의 범프를 전기적으로 접속되도록 하는 단계와, 칩을외부로 부터 보호하기 위하여 플라스틱 수지로 밀봉하는 단계로 진행하는 것을 특징으로 하는 테이프 캐리어 패키지 제조방법.As a manufacturing method for achieving the object of the present invention as described above, the copper foil is attached to the upper surface of the base film, and the copper foil is etched to form an open pad arranged alternately with each other and an inner lead for electrically connecting the open pads therein. And applying a solder resist sheet to protect the entire copper foil including inner lead except for the open pad, and plating the open pad to manufacture a TPC tape, and an open pad and a chip of the TPC tape. Adhering a conductive adhesive film between the bumps of the tape and thermally compressing the bumps of the chip to the open pads so as to electrically connect the bumps, and sealing the chip with a plastic resin to protect the chip from the outside. Carrier Package Manufacturing Method.
이하, 본 발명에 의한 테이프 캐리어 패키지 및 그 제조방법을 첨부도면에 도시된 일실시예에 의거하여 상세하게 설명한다.Hereinafter, a tape carrier package and a method of manufacturing the same according to the present invention will be described in detail with reference to an embodiment shown in the accompanying drawings.
본 발명에 따른 테이프 캐리어 패키지를 제조하기 위한 티씨피 테이프는 도 3에 도시한 바와 같이, 베이스 필름(10)의 상면에 접착제(11)를 이용하여 부착된 동박(12)과, 상기 동박(12)을 에칭하여 형성되는 인너리드와 오픈 패드(open pad)(13)와, 상기 오픈 패드(13)를 제외하고 인너리드를 포함하여 동박(12)전체를 보호하기 위하여 도포되는 솔더 레지시트(solder resist)(14)와, 상기 오픈 패드(13)에 도금된 도금부로 구성된다.The TPC tape for manufacturing the tape carrier package according to the present invention, as shown in Figure 3, the copper foil 12 attached to the upper surface of the base film 10 using the adhesive 11, and the copper foil 12 A solder resist sheet applied to protect the entire copper foil 12 including an inner lead and an open pad 13 formed by etching) and an inner lead except the open pad 13. resist) and a plated portion plated on the open pad 13.
상기 오픈 패드(13)는 칩(16)의 범프(17)와 접촉하여 전기적인 연결을 이루는 것으로, 본 고안의 티씨피 테이프는 베이스 필름(1)에 디바이스 홀(device hole)(1a)을 형성하여 리드(3)를 노출시키는 종래의 기술과는 달리 베이스 필름(10)의 최상면에 인너리드와 연결된 오픈 패드(13)를 형성함으로써, 리드가 구부러지거나 부러지는 종래의 문제점을 해결할 수 있다.The open pad 13 is in contact with the bump 17 of the chip 16 to make an electrical connection. The TPC tape of the present invention forms a device hole 1a in the base film 1. Unlike the conventional technique of exposing the lid 3, the conventional problem that the lead is bent or broken can be solved by forming the open pad 13 connected to the inner lead on the top surface of the base film 10.
상기와 같은 티씨피 테이프를 사용하여 테이프 캐리어 패키지를 제조하는 방법을 설명하면 다음과 같다.Referring to the method of manufacturing a tape carrier package using the TPC tape as described above.
웨이퍼 칩 위의 각 패드에 인너리드본딩을 위하여 일정한 높이의 금(Au)을 도금하는 공정인 범핑(bumping)공정과, 웨이퍼를 낱개의 다이(die)로 절단하는 소잉(sawing)공정과, 상기 티씨피 테이프의 상면에 형성된 오픈 패드(13)에 이방전도성 접착막(anisotropic conductive film)(15)을 접착한 후 칩(16)의 범프(17)를 이에 열압착하여 오픈 패드(13)에 범프(17)를 전기적으로 접속시키는 인너리드본딩공정과, 인너리드본딩된 칩(16)를 외부로부터 보호하기 위하여 일정면적 플라스틱 수지로 밀봉하는 포팅(potting)공정과, 포팅된 제품의 표면에 제조일자 및 제품명을 인쇄하는 마킹(marking)공정으로 진행된다.A bumping process, which is a process of plating gold of a certain height for inner lead bonding to each pad on a wafer chip, a sawing process of cutting the wafer into individual dies, and After attaching an anisotropic conductive film 15 to the open pad 13 formed on the upper surface of the TPC tape, the bumps 17 of the chips 16 are thermally pressed against the bumps on the open pads 13. An inner lead bonding process for electrically connecting 17, a potting process for sealing the inner lead bonded chip 16 with a certain area of plastic resin to protect it from the outside, and a manufacturing date on the surface of the potted product. And a marking process of printing the product name.
첨부한 도 4는 본 발명의 테이프 캐리어 패키지를 도시한 단면도이고, 도 5는 본 발명의 티씨피 테이프를 도시한 평면도로서, 상기 티씨피 테이프의 오픈 패드(13)는 원형으로 형성되며 인접하는 오픈 패드(13)끼리 서로 엇갈리게 배열되어 있어서, 한정된 면적에서 보다 많은 오픈 패드(13)를 형성할 수 있게 된다.4 is a cross-sectional view illustrating the tape carrier package of the present invention, and FIG. 5 is a plan view showing the TPC tape of the present invention, wherein the open pad 13 of the TPC tape is formed in a circular shape and is adjacent to the open. Since the pads 13 are alternately arranged with each other, more open pads 13 can be formed in a limited area.
이상에서 설명한 바와 같이 본 발명의 테이프 캐리어 패키지 및 그 제조방법에 의하면 오픈 패드를 이용하여 칩의 범프와 연결시키므로 종래 기술에서의 문제점으로 대두되었던 리드의 구부러짐이나 부러짐을 방지하고, 전도성 이물질이 리드에 부착되어 전기적인 불량을 발생하는 문제점을 해결하여 전기적인 특성을 향상시킬 수 있는 효과가 있다.As described above, according to the tape carrier package of the present invention and a method of manufacturing the same, it is connected to the bump of the chip by using an open pad, thereby preventing bending or breaking of the lead, which has been a problem in the prior art, and conductive foreign matter on the lead. There is an effect that can improve the electrical characteristics by solving the problem of the electrical defects are attached.
또한, 오픈 패드를 엇갈리게 형성하므로 파인 피치를 이룰 수 있어 칩의 소형화를 이룰 수 있는 효과가 있다.In addition, since the open pads are staggered, a fine pitch can be achieved, thereby miniaturizing the chip.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019980063530A KR100313500B1 (en) | 1998-12-31 | 1998-12-31 | Tape carrier package and manufacturing method thereof |
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| Application Number | Priority Date | Filing Date | Title |
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| KR1019980063530A KR100313500B1 (en) | 1998-12-31 | 1998-12-31 | Tape carrier package and manufacturing method thereof |
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| KR20000046803A KR20000046803A (en) | 2000-07-25 |
| KR100313500B1 true KR100313500B1 (en) | 2001-12-12 |
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| KR19980024072A (en) * | 1996-09-05 | 1998-07-06 | 사와무라 시꼬 | Semiconductor device and mounting method thereof |
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