KR100313084B1 - Method for manufacturing a semiconductor device - Google Patents

Abstract

In the present invention, when the memory cell is formed, the word line, the capacitor, and the bit line are stacked in this order so that the dielectric material of the capacitor is deposited with tantalum oxide and then subjected to high temperature heat treatment to ensure leakage current characteristics of the tantalum oxide as well as The present invention relates to a method of manufacturing a semiconductor device having a reduced fact ratio to facilitate bit line contact etching. A word line 20 is formed on a semiconductor substrate 10, and then a first interlayer insulating layer 30 is deposited. 42 and the first bit line contact 52 are formed at the same time, the bit line contact pads 80 are formed on the first bit line contact 52 and the spacers 82 are formed on the sidewalls, and then the capacitor contacts 42 are formed. ) Form a capacitor. Then, the second interlayer insulating film 90 is deposited on the capacitor-formed front surface, the second bit line contact 54 is formed on the bit line contact pad 80, and the spacer 56 is formed on the inner sidewall. By forming the 60, the leakage current characteristic of the tantalum oxide 74 of the capacitor can be secured, and the aspect ratio during the bit line contact etching through the bit line contact pad 80 can be reduced to facilitate the etching process. There is this.

Description

Manufacturing Method of Semiconductor Device {METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE}

The present invention relates to a method of manufacturing a semiconductor device, and more particularly, in order to form a memory cell, by stacking word lines, capacitors, and bit lines in order, the dielectric material of the capacitor is deposited with tantalum oxide and then subjected to high temperature heat treatment to perform tantalum. The present invention relates to a method for fabricating a semiconductor device, which not only ensures leakage current characteristics of oxide but also reduces aspect ratio to facilitate bit line contact etching.

In general, there are many kinds of semiconductor devices, and various manufacturing techniques are used to configure transistors and capacitors formed in the semiconductor devices, and in particular, capacitors must have increased capacitance despite a small area. do. Therefore, in order to solve these problems, the structure that can maximize the surface area in a small area is studied.

As semiconductor devices become more integrated, the area of the capacitor is rapidly decreasing, and thus, the charge required for the operation of the memory device, that is, the capacitance secured in the unit area, must be further increased.

On the other hand, the basic structure of the capacitor used in the memory cell is composed of the lower electrode for the charge storage electrode, the dielectric film and the upper electrode for the plate (plate). Capacitors having such a structure have a first thin dielectric film thickness to increase the capacitance in a small area, increase the effective area through the structure of a three-dimensional capacitor, or use a dielectric film with a high dielectric constant material. Several conditions must be met, such as forming

1 is a cross-sectional view showing a memory cell region of a semiconductor device formed by a conventional method.

Referring to the structure of the DRAM as shown here, after forming the word line 20, the bit line 60 is defined thereon, and then a capacitor over bit line sequentially stacking the storage node 70 of the capacitor. ) Structure.

In this structure, a microcircuit process of 0.15 mu m or less requires subsequent heat treatment of 700 DEG C or lower by using a metal bit line 60 such as tungsten. That is, subsequent heat treatment of 700 ° C. or more is limited.

In addition, a tantalum oxide (Ta ₂ O ₅ ) dielectric is used as a high dielectric constant to obtain a large capacitance in a capacitor. In order to secure leakage current characteristics of the tantalum oxide dielectric, 800 ° C is deposited after tantalum oxide is deposited. The above high temperature heat treatment is required.

However, in the COB (Capacitor Over Bit line) structure as described above, since the bit line is already formed, after the tantalum oxide is deposited while forming a capacitor, subsequent heat treatment of 800 ° C. or higher cannot be performed to secure leakage current characteristics. There is a problem that it is difficult to implement a satisfactory heat treatment.

To solve this problem, a capacitor under bit line (CUB) structure is used in which a word line is formed, a capacitor is formed, and then stacked in the order of the bit lines, but in this structure, the bit line contact is directly placed on the active area of the cell. There is a difficulty to define. That is, the height of the cell from the capacitor to the active region of the cell is high, the aspect ratio is too large in the fine line width circuit of 0.15㎛ or less is difficult to form a bit line contact hole.

The present invention was created to solve the above problems, and an object of the present invention is to form a capacitor after forming a word line, and then using a capacitor under bit line (CUB) structure that is stacked in the order of the bit lines. When forming the capacitor lower electrode poly to easily define the bit line contact directly into the active region of the cell, the bit line contact pads are simultaneously formed to reduce the aspect ratio during the bit line contact hole etching, thereby facilitating the etching process. The present invention provides a method for manufacturing a device.

1 is a cross-sectional view showing a memory cell of a semiconductor device formed by a conventional method.

2 to 7 are cross-sectional views illustrating memory cells for explaining a method of manufacturing a semiconductor device according to the present invention.

-Explanation of symbols for the main parts of the drawings-

10: substrate 20: word line

52: first bit line contact 54: second bit line contact

60: bit line 70: storage node

80: bitline contact pad

According to an aspect of the present invention, a word line is formed on a semiconductor substrate, a first interlayer insulating layer is deposited, and then planarized to simultaneously form a capacitor contact hole and a bit line contact hole. Depositing a contact hole by depositing poly and depositing an insulating film thereon; forming a bitline contact pad on the bitline contact after depositing the insulating film; forming a spacer on the sidewall of the bitline contact pad; Forming a capacitor over the capacitor contact after forming the spacer, depositing and planarizing a second interlayer insulating film on the entire surface where the capacitor is formed, and forming the bit line contact on the bit line contact pad after planarization. And forming a spacer in the bit line contact and then filling the metal material to form the bit line. A comprise.

According to the present invention, the memory cell of the semiconductor device forms a word line and then forms a capacitor and then forms a bit line over the bit line contact to form a capacitor contact hole to prevent the miss contact of the bit line contact. By simultaneously forming the holes and forming contact pads thereon, the leakage current characteristics of the capacitor dielectric can be secured, and bitline contact holes can be easily formed during the manufacturing process of the fine line width circuit.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the present embodiment is not intended to limit the scope of the present invention, but is presented by way of example only and the same parts as in the conventional configuration using the same reference numerals and names.

2 to 7 are diagrams of memory cells for explaining a method of manufacturing a semiconductor device according to the present invention, wherein (a) are cross-sectional views and (b) are plan views.

As shown in FIG. 2, after forming the word line 20 over the semiconductor substrate 10, the first interlayer insulating layer 30 is deposited to insulate the word line 20 and the lower electrode 72 of the capacitor. Plan the work. Then, the capacitor contact hole 41 and the first bit line contact hole 51 are simultaneously formed.

3, the capacitor contact hole 41 and the first bit line contact hole 51 are filled with a plug poly to form the capacitor contact 42 and the first bit line contact 52. ) Is deposited as a lamination layer.

At this time, the insulating film 44 is deposited as an insulating film having a good selectivity of wet etching when removing the remaining oxide film to form a subsequent capacitor structure. At this time, since the insulating film 44 serves as an insulating film between the lower electrode 72, the upper electrode 78 of the capacitor, and the plug poly of the first bit line contact 52, the selectivity to wet etching should be excellent. Such materials include PE-TEOS and oxynitride films, and PE-TEOS films were used in this embodiment.

For example, a typical oxide film used to form a capacitor cylinder structure is PSG, which has a slow etching rate of PE-TEOS 1/20 compared to PSG.

Thereafter, as illustrated in FIG. 4A, a bit line contact pad 80 for forming the second bit line contact 54 is defined. At this time, the bit line contact pad 80 is defined up to the field oxide layer as shown in the plan view shown in FIG.

This is because when the second bit line contact 54 is formed on the bit line contact pad 80 after the capacitor is formed, a capacitor is formed above the active area to form the second bit line contact 54 outside the active area. It is for.

Thereafter, an oxide film or a nitride film spacer 82 is formed to insulate the sidewalls opened after the bit line contact pad 80 is formed.

Then, as shown in FIG. 5, the lower electrode 72 of the capacitor is formed to form a three-dimensional structure.

The three-dimensional structure of the capacitor may adopt a structure such as an inner / outer cylinder. Here, the structure of the outer cylinder is illustrated. At this time, in order to increase the planar area of the lower electrode 72 in order to secure the capacitance of sufficient capacity, even if the lower electrode 72 is formed up to the area where the bit line contact pad 80 is formed, the bit line contact pad ( This is possible because it is insulated by the spacer 82 formed on the sidewall of 80 and the insulating film formed thereon.

Then, as shown in FIG. 6, the lower electrode 72 of the capacitor is formed in a three-dimensional structure, and then a rapid thermal nitriding process is performed to deposit tantalum oxide 74. Then, after performing a low temperature heat treatment with plasma N 2 O or UV-O 3, a high temperature heat treatment process is performed at a temperature of 800 ° C. or higher to secure the leakage current characteristics of the tantalum oxide 74. After the TiN 76 is deposited, the upper electrode 78 is deposited to form a capacitor.

Subsequently, a second interlayer insulating film 90 is deposited on the entire surface where the capacitor is formed, as shown in FIG. 7, and then planarized, and a second bit line contact 54 is formed on the bit line contact pad 80. ) So that the second bit line contact 54 passes through the upper electrode 78 of the capacitor, thereby preventing cross bridges.

Since the bit line contact pads 80 are formed when the capacitor contact 42 is formed as described above, the height of the first to second bit line contacts 52 and 54 is the height of the capacitor and the second interlayer insulating film formed on the capacitor ( Compared to the method of forming a contact directly into the active region by the height of 90), the aspect ratio can be significantly reduced, so that the definition of the bit line contact is easy.

After that, a plug is formed of a metal such as tungsten, and a metal layer is deposited to form a bit line.

As described above, the present invention forms a metal bit line thereon after forming a tantalum oxide capacitor, thereby eliminating the restriction on high temperature heat treatment, thereby ensuring leakage current characteristics of tantalum oxide by high temperature heat treatment of 800 ° C. or higher after deposition of tantalum oxide. There is an advantage.

In addition, after forming the contact of the capacitor lower electrode and the bit line contact at the same time, the plug poly is deposited to form the bit line contact pad, thereby forming the capacitor and reducing the aspect ratio during the etching of the bit line contact hole to facilitate the etching process. There is this.

Claims (5)

Forming a word line over the semiconductor substrate, depositing a first interlayer insulating film, and then planarizing and simultaneously forming a capacitor contact hole and a bit line contact hole; Depositing a plug poly on the contact hole and filling the contact hole and depositing an insulating layer thereon; Depositing an insulating film as described above and forming a bit line contact pad on the first bit line contact; Forming a spacer on sidewalls of the bitline contact pads; Forming a capacitor over the capacitor contact after forming the spacer as described above; Depositing and planarizing a second interlayer insulating film on the entire surface where the capacitor is formed as described above; Forming a second bit line contact in the bit line contact pad after the flattening as described above; Forming a bit line by burying a metal material after forming a spacer in the second bit line contact; Method for manufacturing a semiconductor device, characterized in that consisting of. The method of claim 1, wherein the insulating film A method of manufacturing a semiconductor device, characterized in that the PE-TEOS film or the oxynitride film has an excellent selectivity ratio compared to the oxide film for forming a subsequent capacitor structure. The method of claim 1, wherein the bit line contact pad A method for manufacturing a semiconductor device, comprising a bit line contact region and a field region. The method of claim 1, wherein forming the capacitor Forming a lower electrode of the capacitor in a three-dimensional structure; Forming a lower electrode as described above and then performing a rapid thermal nitriding process to deposit tantalum oxide; Depositing tantalum oxide as described above and performing a low temperature heat treatment with either plasma N ₂ O or UV-O ₃ ; After the low temperature heat treatment as described above and the high temperature heat treatment at 800 ℃ or more, After the high temperature heat treatment as described above, depositing TiN and then depositing an upper electrode Method for manufacturing a semiconductor device, characterized in that consisting of. The method of claim 1, wherein the second bit line contact is And forming the bit line contact pads formed outside the active region.