1309073 10586twf2.doc/d 97-01-23 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件的製造方法，且特別 是有關於一種防止動態隨機存取記憶體元件之淺溝渠隔離 區遭到損害之方法。 【先前技術】 動態隨機存取記憶體係利用基底上大量的電容器之帶 電荷及不帶電荷來儲存二進位資料。一個電容器代表一記 憶位元，對於其儲存之二進位資料「〇」或「1」分別代表 電容器「帶電荷」或「不帶電荷」的狀態。藉由轉移場效 電晶體，DRAM中讀/寫的動作可被完成，其中轉移場效電 晶體之源極係與位元線(Bite Line，BL)連接，其汲極係與 電容器連接，而其閘極係與字元線(Word Line，WL)連接。 經由轉移場效電晶體，由此位元線通入一電壓使電容器帶 電荷，且轉移場效電晶體以字元線有選擇性之控制其成主 動或被動，如此就完成寫入之動作。 一般動態隨機存取記憶體元件之前段製造流程如第1A 圖至第1D圖所示。首先，請參照第1A圖，提供一基底100, 基底1〇〇具有一記憶胞區130以及一周邊電路區140,且記 憶胞區130中已形成有閘極結構110a(由閘介電層104a、閘 極導電層106a以及頂蓋層108a所構成），而周邊電路區140 中已形成有隔離區102以及閘極結構110b(由閘介電層 104b、閘極導電層106b以及頂蓋層108b所構成）。而且在 閘極結構ll〇a、110b之側壁還分別形成有一薄間隙壁 112a ' 112b ° 接著，在周邊電路區140中形成一淡摻雜汲極區114， 5 1309073 l〇586twf2.doc/d 97-〇卜23 其係形成在薄間隙壁I12b兩側之基底100中。之後，於基 底100上形成一阻障層II6’再於阻障層116上沈積一層矽 酸乙酯（TEOS)-氧化矽118 ’覆蓋閘極結構110a、110b。 請參照第1B圖，對TEOS-氧化矽層11S進行一回蝕刻 製程，直到阻障層116暴露出來。其中，在記憶胞區I30 中，因相鄰的閘極結構ll〇a之間的間隔較窄，因此在此回 蝕刻製程之後所留下的TEOS-氧化矽層118a會塡滿閘極結 構110a之間的空隙。而在周邊電路區140中，因閘極結構 110b與鄰近的元件之間的間隔較大，因此在此回鈾刻製程 之後所留下之TEOS-氧化矽層會成爲閘極結構ll〇b之間隙 壁 118b 。 然而，在此回蝕刻製程過後，往往會發現在靠近間隙 壁118b之處122的阻障層116會變薄，同樣的，在記憶胞 區的標號124所指處，阻障層116也會變得較薄，其又稱 爲弱點(weak point)。 在形成間隙壁118b之後，於間隙壁118b兩側之基底 中形成一源極/汲極區120。然後，再利用一濕蝕刻製 程’移除TEOS-氧化矽靨118a與間隙壁118b，如第1C圖 所示。在移除TEOS-氧化矽層118a與間隙壁11Sb之後， 再於基底100上形成〜層硼磷矽酸玻璃(BPSG)126,覆蓋閘 極結構ll〇a、110b ’如第1D圖所示。 然而，在上述濕蝕刻製程的過程中，原先變得較薄的 阻障層II6處(弱點處）122、124有可能會被蝕穿，而對於 在周邊電路區140中122處來說，因阻障層116底下係爲 隔離區1〇2，此濕蝕刻製程在鈾穿阻障層116之後，可能會 6 .1309073 10586twf2.doc/d 97-01-23 繼續蝕刻阻障層Π6底下的隔離區102,而造成隔離區102 中形成有孔洞。倘若隔離區102中形成有孔洞，將會使得 隔離區102之隔離能力惡化，而造成漏電流以及元件可靠 度變差等缺失。 【發明内容】 因此本發明的目的就是提供一種半導體元件的製造方 法，以解決習知於動態隨機存取記憶體的製造過程中會有 於隔離區中形成孔洞之問題。 本發明提出一種半導體元件的製造方法，此方法係首 先提供一基底，其中基底具有一記憶胞區以及一周邊電路 區，且記憶胞區中已形成有數個第一閘極結構，而周邊電 路區中已形成有數個第二閘極結構。接著，形成一阻障層， 共形的覆盖在基底、第一閘極結構以及第二閘極結構之表 面上。之後，在阻障層上形成一第一介電層，然後再回蝕 刻第一介電層，在此，於記憶胞區中，因第一閘極結構之 間的間距較小，因此保留下來之第一介電層會塡於第一閘 極結構之間的空隙。而於周邊電路區中，因第二閘極結構 與鄰近元件之間的間距較大，因此保留下來的第一介電層 會成爲第二.閘極側壁的間隙壁。隨後，在周邊電路區中形 成一源極/汲極區，其係形成在間隙壁兩側之基底中。然 後，於基底上形成一第二介電層，覆蓋保留下來的第一介 電層、間隙壁、第一閘極結構與第二閘極結構，第二介電 層係作爲層間介電層(ILD)之用，其中第二介電層之材質係 與第一介電層之材質相同。在本發明中，第一介電層與第 二介電層之材質較佳的是硼磷矽酸玻璃(BPSG)。 7 1309073 1〇586twf2.doc/d 97-01-23 由於本發明之第一介電層與第二介電層係爲相同之材 質，因此，於周邊電路區中形成源極/汲極區之後，並不需 要將第二閘極結構側壁之間隙壁移除，而可以繼續形成第 二介電層。如此，習知因移除第一介電層時會導致隔離區 中形成有孔洞之情形就不會發生。 另外，因本發明不需將第一介電層移除，而可以直接 在第一介電層上繼續沈積第二介電層，因此本發明之方法 相較於習知方法省略了移除第一介電層之步驟，因此製程 也較爲簡化。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳 細說明如下： 【實施方式】 第2A圖至第2C圖所示，其係依照本發明一較佳實施 例之動態隨機存取記憶體元件之前段製造流程剖面示意 圖。 請參照第2A圖，首先提供一基底1〇〇，其中基底1〇0 具有一記憶胞區130以及一周邊電路區140，且記憶胞區 130中已形成有閘極結構110a(由閘介電層l(Ma、閘極導電 層106a以及頂蓋層l〇8a所構成）’而周邊電路區140中已 形成有隔離區1〇2以及閘極結構ll〇b(由閘介電層1〇4b、 閘極導電層l〇6b以及頂盖層108b所構成）。在一較佳實施 例中，閘介電層l〇4a、l〇4b之材質例如是氧化矽，閘極導 電層106a、106b之材質例如是多晶砍，頂蓋層l〇8a、108b 之材質例如是氮化矽，而隔離區1〇2例如是淺溝渠隔離區。 8 1309073 105« 86twf2.doc/d 97-01-23 接著，在鬧極結構110a、n〇b之側壁分別形成薄間隙 壁112a、112b，其中形成薄間隙壁H2a、112b之方法例如 是先於基底100上形成一共形薄層(未繪示）之後，再回蝕刻 此共形薄層，即可形成薄間隙壁llh、112b。在一較佳實 施例中，薄間隙壁112a、ll2b之材質例如是氮化矽。 之後，在周邊電路區14〇中形成淡摻雜汲極區114，其 係形成在薄間隙壁112b兩側之基底1〇〇中。其中’形成淡 摻雜汲極區114之方法例如是以閘極ll〇b與薄間隙壁112b 爲植入罩幕進行一離子植入步驟而形成的。 在形成淡摻雜汲極114之後，在基底100上形成第一 介電層200，覆蓋阻障層116。在一較佳實施例中，第一介 電層200之材質例如是硼磷矽酸玻璃，且形成第一介電層 2〇〇之方法例如是爐管式低壓化學氣相沈積法 (FUrnace-LPCVD)、爐管式常壓化學氣相沈積法 (Furnace-APCVD)、單一晶片式常壓化學氣相沈積法 (Chamber-APCVD)、爐管式次常壓化學氣相沈積法 (Furnace-SAPCVD)或單一晶片式次常壓化學氣相沈積法 (Chamber-SAPCVD)。 請參照第2B圖，對第一介電層2〇〇進行一回蝕刻製 程，直到閘極結構110a、ll〇b上方之阻障層n6暴露出來。 其中，在記憶胞區13〇中，因相鄰的閘極結構110a之間的 間隔較窄，因此在此回蝕刻製程之後所留下的第一介電層 2〇Oa會塡滿閘極結構11〇a之間的空隙。而在周邊電路區 H0中，因閘極結構110b與鄰近元件之間的間隔較大，因 此在此回蝕刻製程之後所留下之第—介電層會成爲閘極結 97-01-23 1309073 1 05 86twf2.doc/d 構110b之間隙壁200b。 之後，在周邊電路區14〇中形成一源極/汲極區120 ’ 其係形成在間隙壁2〇〇b兩側之基底100中。其中’形成源 極/汲極區12〇之方法例如是以閘極結構l1〇b與間隙壁 2〇〇b爲植入罩幕進行一離子植入步驟而形成的。 請參照第2C圖，在形成源極/汲極區12〇之後’並不 需要將第一介電層2〇〇a與間隙壁2〇〇b移除，而直接在基 底100上沈積第二介電層I.26,覆蓋保留下來的第一介電層 2〇〇a、間隙壁200b、第一閘極結構u〇a與第二聞極結構 110b，第二介電層126係作爲層間介電層(ILD)之用。在此， 第二介電層126之材質係與第一介電層2〇〇a以及間隙壁 2〇Ob之材質相同。在一較佳實施例中，第二介電層126之 材質例如是硼磷矽酸玻璃，且形成第二介電層126之方法 係與形成第一介電層200之方法相同，例如是爐管式低壓 化學氣相沈積法、爐管式常壓化學氣相沈積法、單一晶片 式常壓化學氣相沈積法、爐管式次常壓化學氣相沈積法或 單一晶片式次常壓化學氣相沈積法。 後續，便可以依照記憶體元件之設計，而繼續於基底 上形成接觸窗、位元線等等構件，而完成記憶體元件之製 作。 在本發明中，由於第一介電層與第二介電層係爲相同 之材質，因此，於周邊電路區中形成源極/汲極區之後，並 不需要將記憶胞區中閘極結構之間的第一介電層以及周邊 電路區中閘極結構側壁之間隙壁移除，而可以直接在基底 上方形成第二介電層。如此一來，習知因移除第一介電層 10 97-01-23 1309073 10586twf2.doc/d 時會導致隔離區中形成有孔洞之情形就不會發生。 另外，因本發明不需將記憶胞區中閘極結構之間的第 一介電層以及周邊電路區中閘極結構側壁之間隙壁移除， 而可以直接在第一介電層上繼續沈積第二介電層，因此本 發明之方法相較於習知方法省略了移除第一介電層之步 驟，因此製程也較爲簡化。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 【圖式簡單說明】 第1A圖至第1D圖是習知動態隨機存取記憶體元件之 前段製造流程剖面示意圖；以及 第2A圖至第2C圖是依照本發明一較佳實施例之動態 隨機存取記憶體元件之前段製造流程剖面示意圖。 【主要元件符號說明】 100 :基底 102 :隔離區 104a、104b :閘介電層 l〇6a、l〇6b :閛極導電層 108a、108b :頂蓋層 110a、110b :閘極結構 112a、112b :薄間隙壁 114 :淡摻雜汲極區 116 :阻障層 13090¾ 6twf2. doc/d 97-01-23 118、118a : TEOS-氧化矽 118b、200b :間隙壁 120 :源極/汲極區 122、124 :弱點 126、200、200a : BPSG 層 121309073 10586twf2.doc/d 97-01-23 IX. Description of the Invention: [Technical Field] The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method for preventing a dynamic random access memory device The method of damage to the shallow trench isolation zone. [Prior Art] A dynamic random access memory system utilizes a large number of capacitors on a substrate with and without charge to store binary data. A capacitor represents a memory bit, and the binary data "〇" or "1" stored therein represents the state of the capacitor "charged" or "uncharged". By transferring the field effect transistor, the read/write operation in the DRAM can be completed, wherein the source of the transfer field effect transistor is connected to the bit line (BL), and the drain line is connected to the capacitor. Its gate is connected to the word line (Word Line, WL). By transferring the field effect transistor, a voltage is applied to the bit line to charge the capacitor, and the transfer field effect transistor selectively controls the active or passive word line to complete the writing operation. The manufacturing process of the general dynamic random access memory device in the previous stage is as shown in Figs. 1A to 1D. First, referring to FIG. 1A, a substrate 100 is provided. The substrate 1 has a memory cell region 130 and a peripheral circuit region 140, and a gate structure 110a has been formed in the memory cell region 130 (by the gate dielectric layer 104a). The gate conductive layer 106a and the cap layer 108a are formed, and the isolation region 102 and the gate structure 110b are formed in the peripheral circuit region 140 (the gate dielectric layer 104b, the gate conductive layer 106b, and the cap layer 108b) Composition). Further, a thin spacer 112a' 112b is formed on the sidewalls of the gate structures 11a, 110b, respectively. Then, a lightly doped drain region 114 is formed in the peripheral circuit region 140, 5 1309073 l 586 586 ftf2.doc / d 97-〇23 is formed in the substrate 100 on both sides of the thin spacer I12b. Thereafter, a barrier layer II6' is formed on the substrate 100, and a layer of ethyl phthalate (TEOS)-yttria 118' is deposited over the barrier layer 116 to cover the gate structures 110a, 110b. Referring to Fig. 1B, the TEOS-yttria layer 11S is subjected to an etching process until the barrier layer 116 is exposed. Wherein, in the memory cell region I30, since the interval between adjacent gate structures 11a is narrow, the TEOS-yttria layer 118a left after the etchback process will fill the gate structure 110a. The gap between them. In the peripheral circuit region 140, since the interval between the gate structure 110b and the adjacent elements is large, the TEOS-yttria layer left after the uranium engraving process becomes the gate structure llb. Clearance wall 118b. However, after this etch back process, it is often found that the barrier layer 116 near the spacer 118b becomes thinner. Similarly, at the location of the memory cell 124, the barrier layer 116 also changes. It is thinner, which is also called a weak point. After the spacers 118b are formed, a source/drain region 120 is formed in the substrate on both sides of the spacers 118b. Then, the TEOS-yttria 118a and the spacers 118b are removed by a wet etching process as shown in Fig. 1C. After the TEOS-yttria layer 118a and the spacers 11Sb are removed, a layer of borophosphoric acid glass (BPSG) 126 is formed on the substrate 100, and the gate structure lla, 110b' is as shown in Fig. 1D. However, during the wet etching process described above, the barrier layers II6 (weak spots) 122, 124 which were originally thinner may be etched through, and for the 122 in the peripheral circuit region 140, The barrier layer 116 is under the isolation region 1 〇 2, and the wet etching process may continue after the uranium barrier layer 116 may continue to etch the barrier layer Π6 under 6.1309073 10586 twf2.doc/d 97-01-23 The region 102 causes holes to be formed in the isolation region 102. If a hole is formed in the isolation region 102, the isolation capability of the isolation region 102 is deteriorated, resulting in a loss of leakage current and deterioration of component reliability. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a method of fabricating a semiconductor device that solves the problem of forming a hole in an isolation region during the fabrication of a dynamic random access memory. The invention provides a method for fabricating a semiconductor device. The method first provides a substrate, wherein the substrate has a memory cell region and a peripheral circuit region, and a plurality of first gate structures are formed in the memory cell region, and the peripheral circuit region is formed. A plurality of second gate structures have been formed in the middle. Next, a barrier layer is formed which conformally covers the surface of the substrate, the first gate structure and the second gate structure. Thereafter, a first dielectric layer is formed on the barrier layer, and then the first dielectric layer is etched back. Here, in the memory cell region, since the spacing between the first gate structures is small, it remains. The first dielectric layer will lie in the gap between the first gate structures. In the peripheral circuit region, since the distance between the second gate structure and the adjacent elements is large, the remaining first dielectric layer becomes the spacer of the second gate sidewall. Subsequently, a source/drain region is formed in the peripheral circuit region, which is formed in the substrate on both sides of the spacer. Then, a second dielectric layer is formed on the substrate, covering the remaining first dielectric layer, the spacer, the first gate structure and the second gate structure, and the second dielectric layer serves as an interlayer dielectric layer ( For the purpose of ILD), the material of the second dielectric layer is the same as the material of the first dielectric layer. In the present invention, the material of the first dielectric layer and the second dielectric layer is preferably borophosphoric acid glass (BPSG). 7 1309073 1〇586twf2.doc/d 97-01-23 Since the first dielectric layer and the second dielectric layer of the present invention are of the same material, after the source/drain regions are formed in the peripheral circuit region It is not necessary to remove the spacers of the sidewalls of the second gate structure, and the second dielectric layer can continue to be formed. Thus, it is conventional that the formation of a hole in the isolation region does not occur because the first dielectric layer is removed. In addition, since the present invention does not need to remove the first dielectric layer, the second dielectric layer can be deposited directly on the first dielectric layer, so the method of the present invention omits the removal method compared to the conventional method. The step of a dielectric layer, so the process is also simplified. The above and other objects, features, and advantages of the present invention will become more apparent and understood. 2C is a cross-sectional view showing the manufacturing process of the preceding stage of the dynamic random access memory device in accordance with a preferred embodiment of the present invention. Referring to FIG. 2A, a substrate 1 is first provided. The substrate 1 〇 0 has a memory cell region 130 and a peripheral circuit region 140, and a gate structure 110a has been formed in the memory cell region 130. The layer 1 (Ma, the gate conductive layer 106a and the cap layer 10a) constitutes an isolation region 1〇2 and a gate structure 11〇b (by the gate dielectric layer 1) in the peripheral circuit region 140. 4b, the gate conductive layer 16b and the cap layer 108b are formed. In a preferred embodiment, the material of the gate dielectric layers 10a, 4b, for example, yttrium oxide, gate conductive layer 106a, The material of 106b is, for example, polycrystalline chopping, the material of the cap layer 10a, 108b is, for example, tantalum nitride, and the isolation region 1〇2 is, for example, a shallow trench isolation region. 8 1309073 105« 86twf2.doc/d 97-01 -23 Next, thin spacers 112a, 112b are formed on the sidewalls of the pole structures 110a, n〇b, respectively, wherein the method of forming the thin spacers H2a, 112b is, for example, forming a conformal thin layer on the substrate 100 (not shown) After that, the conformal thin layer is etched back to form thin spacers 11h, 112b. In a preferred embodiment, the thin spacers 112a The material of ll2b is, for example, tantalum nitride. Thereafter, a lightly doped drain region 114 is formed in the peripheral circuit region 14A, which is formed in the substrate 1〇〇 on both sides of the thin spacer 112b. The method of the drain region 114 is formed, for example, by an ion implantation step of the gate mask 11b and the thin spacer 112b for the implant mask. After the lightly doped drain 114 is formed, the first layer is formed on the substrate 100. A dielectric layer 200 covers the barrier layer 116. In a preferred embodiment, the material of the first dielectric layer 200 is, for example, borophosphoric acid glass, and the method of forming the first dielectric layer 2 is, for example, Furnace-type low pressure chemical vapor deposition (FUrnace-LPCVD), furnace-tube atmospheric pressure chemical vapor deposition (Furnace-APCVD), single-wafer atmospheric pressure chemical vapor deposition (Chamber-APCVD), furnace tube Sub-atmospheric chemical vapor deposition (Furnace-SAPCVD) or single-wafer sub-atmospheric chemical vapor deposition (Chamber-SAPCVD). Please refer to Figure 2B to etch back the first dielectric layer 2 The process is until the barrier layer n6 above the gate structures 110a, 110b is exposed. In the region 13〇, since the interval between the adjacent gate structures 110a is narrow, the first dielectric layer 2〇Oa left after the etchback process is filled between the gate structures 11〇a In the peripheral circuit region H0, since the interval between the gate structure 110b and the adjacent elements is large, the first dielectric layer left after the etchback process becomes the gate junction 97-01. -23 1309073 1 05 86twf2.doc/d The spacer 200b of the structure 110b. Thereafter, a source/drain region 120' is formed in the peripheral circuit region 14A, which is formed in the substrate 100 on both sides of the spacer 2b. The method of forming the source/drain region 12 is formed, for example, by an ion implantation step of the gate structure l1b and the spacer 2b as an implantation mask. Referring to FIG. 2C, after forming the source/drain regions 12〇, it is not necessary to remove the first dielectric layer 2〇〇a and the spacers 2〇〇b, and directly deposit the second on the substrate 100. The dielectric layer I.26 covers the remaining first dielectric layer 2a, the spacer 200b, the first gate structure u〇a and the second gate structure 110b, and the second dielectric layer 126 serves as an interlayer For the dielectric layer (ILD). Here, the material of the second dielectric layer 126 is the same as that of the first dielectric layer 2A and the spacer 2〇Ob. In a preferred embodiment, the material of the second dielectric layer 126 is, for example, borophosphoric acid glass, and the method of forming the second dielectric layer 126 is the same as the method of forming the first dielectric layer 200, such as a furnace. Tube low pressure chemical vapor deposition, furnace tube atmospheric pressure chemical vapor deposition, single wafer atmospheric pressure chemical vapor deposition, furnace tube sub-atmospheric chemical vapor deposition or single wafer sub-atmospheric chemistry Vapor deposition method. Subsequently, in accordance with the design of the memory element, components such as contact windows, bit lines, and the like are formed on the substrate to complete the fabrication of the memory device. In the present invention, since the first dielectric layer and the second dielectric layer are made of the same material, after the source/drain regions are formed in the peripheral circuit region, the gate structure in the memory cell region is not required. A gap between the first dielectric layer and the sidewall of the gate structure in the peripheral circuit region is removed, and a second dielectric layer can be formed directly over the substrate. As a result, it is conventional that the removal of the first dielectric layer 10 97-01-23 1309073 10586twf2.doc/d will result in the formation of a hole in the isolation region. In addition, since the present invention does not need to remove the first dielectric layer between the gate structures in the memory cell region and the spacers of the sidewalls of the gate structure in the peripheral circuit region, the deposition can be directly performed on the first dielectric layer. The second dielectric layer, therefore, the method of the present invention omits the step of removing the first dielectric layer compared to the conventional method, and the process is also simplified. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1D are schematic cross-sectional views showing a manufacturing process of a conventional dynamic random access memory device; and FIGS. 2A to 2C are dynamic random according to a preferred embodiment of the present invention. A schematic cross-sectional view of the manufacturing process prior to accessing the memory component. [Main component symbol description] 100: Substrate 102: isolation regions 104a, 104b: gate dielectric layers 16a, 6b: gate conductive layers 108a, 108b: cap layers 110a, 110b: gate structures 112a, 112b : Thin spacer 114: lightly doped drain region 116: barrier layer 130902⁄4 6twf2. doc/d 97-01-23 118, 118a: TEOS-yttria 118b, 200b: spacer 120: source/drain region 122, 124: Weak points 126, 200, 200a: BPSG layer 12