KR100312809B1 - Recoverable Memory Modules and How to Recover Memory Modules - Google Patents

Abstract

The present invention proposes a recoverable memory module, such as dynamic random access memory (DRAM) or flash memory, and a method of recovering the memory modules. For a recoverable memory module, defective memory ICs in the module found before or after shipment can be recovered using backup memory ICs. Basically, if faulty memory ICs are found within the module, a set of zero-ohm resistors is used to shorten the plurality of selected jumping pads provided on the PCB, so that the input / output (I / O) pins on the faulty memory IC The connection to the column-address strobe pins is routed to the I / O pins and column-address strobe pins in the backup memory IC instead. This allows the function of the faulty ICs to be performed by the backup memory chip.

Description

Repairable Memory Module And Method of Repairing Memory Modules

The present invention relates to memory modules, and more particularly, to a recoverable memory module, such as a dynamic random access memory (DRAM) module, and a method for recovering the module.

1 is a schematic diagram of a conventional DRAM module designed for use with a 32-bit Pentium microprocessor. The DRAM module includes an array of eight 1M × 4 DRAM ICs used together to form a 1M × 32 SIMM (Single In-line Memory Module).

FIG. 2 shows a planar configuration when the conventional DRAM module of FIG. 1 is assembled. As shown, a DRAM module is formed by mounting eight DRAM ICs U1 to U8 on a printed circuit board (PCB). The input / output (I / O) pins on these DRAM ICs are connected to the corresponding I / O pins of the DRAM module.

Most conventional memory modules, such as DRAM or flash memory modules, are first arranged in a packaged form on the PCB, and then manufactured separately from them so that each of them can act as individual memory modules. These memory modules are each tested through a so-called module testing process to check for defective memory ICs in the module. If a memory IC is found to be defective at this time, the conventional method for repairing a defective IC is to simply remove the defective IC and replace it with a good new one. However, conventional recovery is quite cumbersome to perform.

3 is a flowchart showing processing steps related to a conventional module testing process for repairing a faulty IC. As shown, if the memory module is free of defects, it is ready for shipment to the customer. Otherwise, the defective memory IC in the memory module is detached and a good new one is attached. These two steps together are called a rework process, which is quite cumbersome and inefficient to perform.

A conventional method for fabricating low cost memory modules is to use a technique called chip-on board (COB). However, the recovery for faulty ICs in a memory module based on a COB structure is difficult to perform even before encapsulation. After encapsulation, recovery is very difficult to perform.

It is therefore a primary object of the present invention to provide a recoverable memory module that allows for defective memory ICs in the memory module, which is convenient, even if there is an additional process, without the hassle of removing the defective ICs and mounting a good new one on the printed circuit board. It is to provide a memory module that can be recovered.

It is another object of the present invention to provide a method of recovering a memory module without having to replace defective ICs with good new ones.

1 is a schematic diagram of a conventional DRAM module designed for use with a 32-bit Pentium microprocessor in a PC;

2 shows a planar configuration when the conventional DRAM module of FIG. 1 is assembled;

3 is a flow chart showing processing steps associated with a conventional method for recovering a conventional DRAM module;

4 is a plan view showing various components of the recoverable DRAM module of the present invention;

4 (a) is a plan view showing a module I / O bus;

4 (b) is a plan view showing I / O jumping pad units;

4 (c) is a plan view showing the CAS jumping pad unit JP1;

4 (d) is a plan view showing eight normalized DRAM ICs;

4 (e) is a plan view showing a backup DRAM IC U9;

FIG. 5 shows a planar configuration when the DRAM module of FIG. 4 is assembled;

6 shows an array of recoverable DRAM modules of the present invention arranged together on a printed circuit board for chip irradiation testing.

<Description of the symbols for the main parts of the drawings>

U1-U8: Standardized Memory ICs U9: Backup Memory IC

510, 520, 530: first, second, and third row of jumping pads associated with a standardized memory IC

540, 550: first and second row of jumping pads associated with a backup memory IC

JO-J7, J9-J16, J18-J25, J27-J34: I / O Jumping Pad Units

JP1: CAS Jumping Pad Unit JP1

In accordance with the above objects of the present invention, a recoverable memory module and a method for recovering a memory module are provided.

The recoverable memory module of the present invention includes the following components:

(a) a printed circuit board; (b) a plurality of standardized memory ICs mounted on the printed circuit board; (c) at least one backup memory IC selectively mounted on the printed circuit board, if necessary, the backup memory IC being used to recover from a defect in the standardized memory ICs: (d) for the memory module A module I / O bus having a plurality of I / O pins; (e) a plurality of I / O jumping pad units, each I / O jumping pad unit associated with one of the standardized memory ICs, wherein each I / O jumping pad unit has at least three rows of jumping pads; ), Each row has the same number of jumping pads as the number of I / O pins in the associated memory IC; And (f) at least one CAS jumping pad unit associated with the backup memory IC, wherein the CAS jumping pad unit has jumping pads arranged in at least two rows, each row of a CAS pin on the module I / O bus. Having a number of jumping pads equal to the number;

Furthermore, the first row of jumping pads in each of the I / O jumping pad units are connected with I / O pins in the associated one of the standardized memory I / Cs, respectively; The jumping pads in the second row are each connected with corresponding I / O pins on the module I / O bus; The jumping pads of the third row are connected to the I / O pins in the backup memory IC. And the CAS jumping pad unit, which is the jumping pads of the first row, is connected together to the CAS pin in the backup memory IC; The jumping pads of the second row are then connected to corresponding CAS pins on the module I / O bus, respectively.

Through a module testing process, if all standardized memory ICs are intact, the first row of jumping pads in each of the I / O jumping pad units are shorted with the second row of jumping pads in the same unit; On the other hand, if any of the standardized ICs have a fault, the second row of jumping pads associated with the defective I / O pins in the defective memory IC are shorted with the corresponding third row of jumping pads; The first row of jumping pads associated with normal I / O pins in the standardized memory ICs are shorted with the corresponding second row of jumping pads; And the jumping pads of the first row in the CAS jumping pad unit associated with the defective memory ICs are shorted with the corresponding jumping pads of the second row.

In various other embodiments, standardized memory ICs and the backup memory IC are mounted on a printed circuit board in package form; Or alternatively, the regular memory ICs and the backup memory IC are mounted on a printed circuit board in the form of a chip-on-board (COB); And also alternatively, the standardized memory ICs are mounted on the printed circuit board in the form of a COB, while a backup memory IC is mounted in the package form on the printed circuit board.

In addition, the shorted connection may be implemented using either a set of zero-ohm resistors or a set of jumpers each mounted to pairs of shorted jumping pads.

The maximum recoverability of the recoverable memory module of the present invention described above, that is, the maximum number of faulty ICs in the recoverable module is equal to the number of I / O pins of the backup memory IC.

According to yet another aspect, the present invention provides a method for recovering a memory module. Specifically, this method is used for a memory module having an array of standardized memory ICs and a module I / O bus associated with the standardized ICs to recover a defect in at least one of the standardized memory ICs. The method of the present invention comprises the following processing steps:

(1) providing a backup memory IC of the same type as standardized memory ICs; (2) shorting defective I / O pins in the defective memory IC with corresponding I / O pins in the backup memory IC; (3) shorting normal I / O pins in the standardized memory ICs with corresponding I / O pins in the module I / O bus; (4) Step the CAS pins on the backup memory IC with the corresponding CAS pins on the module I / O bus associated with the faulty memory IC.

In order to implement the shorted connection, the method further includes the following processing steps.

A plurality of I / O jumping pad units are provided, each I / O jumping pad unit associated with the standardized memory ICs, each I / O jumping pad unit having jumping pads arranged in at least three rows. Each row has the same number of jumping pads as the number of I / O pins in the associated memory IC, and in each of the jumping pad units, the jumping pads in the first row are in the associated one of the standardized memory ICs. Each connected to / Os; The jumping pads of the second row are each connected with corresponding I / O pins on the module I / O bus; And the jumping pads of the third row are respectively connected to I / O pins in the backup memory IC; And

Provide a set of at least one CAS jumping pads associated with the backup memory IC, wherein the CAS jumping pad unit is arranged in at least two rows, each row equaling the number of CAS pins on the module I / O bus With a number of jumping pads; In the CAS jumping pad unit, the jumping pads of the first row are connected together with the CAS pins in the backup memory IC; The jumping pads of the second row are each connected with corresponding CAS pins on the module I / O bus.

In addition, the shorted connection can be implemented with either a set of zero-ohm resistors or a set of jumpers, each mounted in shorted pairs of jumping pads. The maximum recoverability of the recoverable memory module of the present invention described above, that is, the maximum number of defective ICs in the recoverable memory module is equal to the number of I / O pins of the backup memory IC.

As described above in the prior art portion of this specification, a memory module is made by forming an array of memory ICs (hereinafter referred to as standardized memory ICs) on a printed circuit board (PCB). The storage capacity of a memory module is the sum of these standardized memory ICs. According to the present invention, at least one additional memory IC (hereinafter referred to as a backup memory IC) is incorporated into the memory module. If any of the standardized memory ICs in the module is found to be faulty, the faulty IC can be recovered using the backup memory IC in the manner set forth in detail below.

If the module is based on an array of packaged memory ICs, the backup memory IC does not need to be mounted on the PCB unless recovery is necessary. If the module is based on a chip-on-board (CCOB), the backup memory IC is mounted with the ICs standardized on the circuit board during the manufacturing process, or alternatively in a reserved area on the module when a later repair is needed. It is supplied in a package that is mounted.

Basically, if faulty memory ICs are found within the module, a set of zero-ohm resistors (jumpers) is used to shorten a plurality of selected jumping pads provided on the PCB, so that the I / O pins on the faulty memory IC The connection to the column-address strobe (CAS) pins is routed to the I / O pins and CAS pins in the backup memory IC instead. With this in mind, a preferred embodiment of the present invention is described next with reference to Figs.

4 is a schematic diagram showing five components, each designed as (a), (b), (c), (d) and (e) of the recoverable memory module of the present invention; On the other hand, Figure 5 shows a plan view when the recoverable memory module is assembled. In this embodiment, the memory module comprises an array of eight 1M × 4 DRAM ICs U1 through U8 (operating with standardized memory ICs), and one additional 1M × 4 DRAM IC U9 (with backup memory IC). Operating) and has a capacity of 1M × 32.

In Figure 4, (a) shows a module I / O bus; (b) shows a number of I / O jumping pad units J0-J7, J9-J16 used to connect the I / O pins in the active DRAM chips U1-U8 with the I / O pins in the module I / O bus. , J18-J25, J27-J34; (c) shows the CAS jumping pad unit JP1 used to connect the CAS pin in the backup memory chip with the corresponding CAS pins in the module I / O bus; (d) shows eight standardized DRAM ICs U1-U8; And (e) represents backup DRAM IC U9.

In addition, as shown in FIG. 5, each of the standardized DRAM ICs U1-U8 is associated with three jumping pad rows 510, 520, 530, each row having four jumping pads. These three jumping pad rows 510, 520, 530 are implemented using I / O jumping pad units J0-J7, J9-J16, J18-J25, J27-J34. If a 1M × 32 module is alternatively formed using two 1M × 16 DRAM ICs, each row should have 16 jumping pads corresponding to the 16 I / O pins on the module I / O bus.

As shown in FIG. 4B, the jumping pads 510 in the first row are connected to I / O pins in associated ones of the standardized DRAM ICs U1-U8, respectively. For example, for the first normalized DRAM IC U1, the four jumping pads of the associated first row 510 are each connected with the RDO-RD3 pins in the DRAM IC U1; The jumping pads of the associated second row 520 are each connected with the D0Q-DQ3 pins on the module I / O bus; And the four jumping pads of the associated third row 530 are each connected with the SP0-SP3 pins in the backup DRAM IC U9. For other standardized DRAM ICs U2-U8, the associated jumping pads are connected in a similar manner, and the jumping pads of the first row 510 are also for chip-irradiation testing for the associated ICs in the standardized DRAM ICs U1-U8. Used.

핀과 접속된다; 한편 아래쪽 행 550에 있는 점핑 패드들(JP1에 있는 1, 3, 5, ,7)은 다음의 표 1에 주어진 바와 같이 규격화된 DRAM IC들 U1-U8에 있는 다양한 칼럼-어드레스 스트로브 핀들과 접속된다.Backup DRAM IC U9 is associated with two jumping pad rows 540, 550, each row having four jumping pads. These two jumping pad rows 540 and 550 are implemented using the CAS jumping pad unit JP1. As shown in Fig. 4C, the jumping pads (2, 4, 6, 8 in JP1) in the top row 540 are together in the backup DRAM IC U9.

Connected with the pin; Meanwhile, the jumping pads (1, 3, 5, and 7 in JP1) in the lower row 550 are connected with various column-address strobe pins in the standardized DRAM ICs U1-U8 as given in Table 1 below. .

After the module is assembled, the next step is to perform a module testing process to check for faulty ICs in the module.

If all of the DRAM ICs U1-U8 in the module are free of defects (if no fault is found), then for all DRAM ICs U1-U8, a number of zero-ohm registers or jumpers may be used in the first row 510. It is used to shorten each of the jumping pads with the corresponding jumping pads of the second row 520, but the two rows of jumping pads 540, 550 associated with the backup DRAM IC U9 are not shorted by the zero-ohm registers. . (I.e., all pairs of jumping pads in JP1 shown in FIG. 4 (c) remain open). This is the I / O jumping pad units J0-J7, J9-J16, J18-J25, J27-J34 respectively. Short the first and second jump pads on. For standardized DRAM IC U1, mounting of the zero-ohm registers causes each of the RDO-RD3 pins in the standardized DRAM IC U1 to be shorted with the DQ0-DQ3 pins on the module I / O bus. Shorting connections are performed in a similar manner for other standardized DRAM ICs U2-U8.

If the module is based on a COB structure, the backup DRAM IC does not need to be mounted at manufacture unless defective chips are found in the module. If the module is based on packaged DRAM ICs, the layout area reserved for the backup DRAM IC may be left empty until defective chips are found in the module.

On the other hand, if the module does not pass the testing, the backup DRAM IC U9 is used to recover the faulty IC. The accompanying recovery operation mounts a set of zero-ohm registers to selected pairs of jumping pads, thus connecting the I / O pins on the faulty IC and the connection to the column-address stove pins, instead of the I / Os on the backup DRAM IC U9. Switch to O pins and column-address strobe pins.

Specifically, in the repair operation, a first set of zero-ohm registers are used to shorten each of the jumping pads of the second row 520 associated with the faulty IC with the corresponding jumping pads of the third row 530; Then for the faulty ICs, a second set of zero-ohm registers is used to shorten each of the jumping pads of the first row 510 with the corresponding jumping pads of the second row 520; Also, for backup DRAM IC U9, a third set of zero-ohm resistors are used to short the jumping pads in the lower row 550 with the jumping pads in the corresponding upper row 540, respectively (as shown in Table 1). .

In the above example, backup DRAM IC U9 was used to recover one of the defective ICs of standardized DRAM ICs U1-U8. However, the recovery capacity of the recoverable memory module of the present invention is not limited to this. Backup DRAM IC U9 can be used to recover up to four faulty ICs in the module. Basically, the maximum recovery capacity of the recoverable memory module of the present invention, that is, the maximum number of faulty ICs in the recoverable module is equal to the number of I / O pins of the backup memory IC. Examples of two such recovery operations are given in Tables 2 and 3, respectively.

In addition to the connections shown in Tables 2 and 3, the jumping pads in the first row 510 associated with the normal I / O pins in the normal ICs are each connected with the jumping pads in the corresponding second row 520. For Table 3, the normal I / O pins on the normal ones of the standardized DRAM ICs U1-U8 are connected as follows: each I / O jumping pad units J1, J2, J5, J6, J9-J16, The jumping pads of the first and second rows in J18-J25, J27-J34 respectively are shorted to each other; In addition, the jumping pads of the second and third rows in each of the I / O jumping pad units J0, J3, J4, J7 are shorted to each other.

The recoverable memory modules of the present invention may be arranged in an array, as shown in FIG. 6, for chip-irradiation testing. This allows testing to be performed on multiple modules simultaneously.

To test the I / O pins and column-address strobe pins, the first pad 510 jumping pads associated with the DRAM ICs U1-U8 with the probes specified and the first pad 540 jumping pads associated with the backup DRAM IC U9 Can reach the fields. To test the address pins and other control pins, the probe may touch the pads associated with the I / O pins on the module I / O bus. Alternatively, these address pins and control pins can be arranged close to the jumping pads for convenient testing.

In conclusion, the recoverable memory module of the present invention has several advantages over the prior art. First, if the recoverable memory module is based on a COB structure, the backup DRAM IC may be mounted with the standardized DRAM ICs U1-U8, or later after the faulty ICs are found. Second, if a recoverable memory module is made of packaged memory ICs, this can reduce manufacturing costs since the memory modules do not have to be mounted with redundant backup DRAM ICs. Third, the use of a backup DRAM IC to recover the faulty ICs is very convenient for the technician to carry out. Fourth, if no faulty ICs are found prior to shipping, the layout area for the backup DRAM IC can be reserved for use later when faulty ICs are found. At that time, the backup DRAM IC is mounted to recover the faulty ICs in the faulty module. Fifth, since recoverable memory modules can be arranged in an array, in module testing, a test is allowed to be performed on multiple modules simultaneously. This can greatly increase the efficiency of testing.

The present invention has been described with reference to preferred embodiments. However, the scope of the present invention is not limited to the disclosed embodiments, but includes various modifications and similar configurations. Therefore, the claims should be construed as broadly as possible to encompass such variations and similar arrangements.

Claims (9)

A recoverable memory module, comprising: a printed circuit board; A plurality of standardized memory ICs mounted on the printed circuit board; At least one backup memory IC selectively mounted on the printed circuit board, if necessary, the backup memory IC being used to recover a faulty IC among the memory ICs of the specification; A module I / O bus having a plurality of I / O pins for the memory module; A plurality of I / O jumping pad units and each I / O jumping pad unit are associated with one of the standardized memory ICs, each I / O jumping pad unit arranged in at least three rows and associated with each row. Having the same number of jumping pads as the number of I / O pins in the memory IC; And at least one CAS jumping pad unit associated with the backup memory IC and the CAS jumping pad unit are arranged in at least two rows, each row having the same number of jumps as the number of CAS pins on the module I / O bus. Have pads; In each of the I / O jump pad units, the jumping pads in the first row are each connected with I / O pins in one of the associated standardized memory ICs; The jumping pads of the second row are each connected with corresponding I / O pins on the module I / O bus; The jumping pads of the third row are each connected with I / O pins in the backup memory IC; In the CAS jumping pad unit, the jumping pads of the first row are connected together to the CAS pins in the backup memory IC; The jumping pads of the second row are each connected with corresponding CAS pins on the module I / O bus; And if all of the standardized memory ICs are intact, the first row of jumping pads in each of the I / O jumping pad units are shorted with the second row of jumping pads in the same unit; And if at least one of the standardized memory ICs has a defect, the second row of jumping pads associated with the defective I / O pins in the defective memory IC are shorted with the corresponding third row of jumping pads; The first row of jumping pads associated with normal I / O pins in the standardized memory ICs are shorted with the corresponding second row of jumping pads; And the first row of jumping pads in the CAS jumping pad unit associated with the defective memory IC are shorted with the corresponding second row of jumping pads. The recoverable memory module of claim 1, wherein the standardized memory ICs and the backup memory IC are mounted in a package form on a printed circuit board. The recoverable memory module of claim 1, wherein the standardized memory ICs and the backup memory IC are mounted in a chip-on-board form on a printed circuit board. The recoverable memory module of claim 1, wherein the standardized memory ICs are mounted in chip-on-board form on the printed circuit board while the backup memory IC is mounted in package form on the printed circuit board. 2. The recoverable memory module of claim 1 wherein the shorted connection is implemented using a set of zero-ohm registers. 2. The recoverable memory module of claim 1 wherein the shorted connections are implemented using a set of jumpers. A method of using to recover defective ICs of at least one of the standardized memory ICs in a memory module in a memory module having an array of standardized memory ICs and a module I / O bus associated with the standardized memory ICs: Providing a backup memory IC of the same type as standardized memories; Shorting the faulty I / O pins in the faulty memory IC with the corresponding I / O pins in the backup memory IC; Shorting normal I / O pins in the standardized memory ICs with corresponding I / O pins in the module I / O bus; Shorting the CAS pin in the backup memory IC with corresponding CAS pins in the module I / O bus associated with the faulty memory IC; Providing a plurality of I / O jumping pad units; Providing at least one set of CAS jumping pads associated with the backup memory IC; Each I / O jumping pad unit is associated with one of the standardized memory ICs, each I / O jumping pad unit being arranged in at least three rows, each row being associated with the number of I / O pins in the associated memory IC. Have the same number of jumping pads; In each of the I / O jumping pad units, the jumping pads in a first row are respectively connected with I / O pins in an associated IC of the standardized memory ICs; The jumping pads of the second row are each connected with corresponding I / O pins on the module I / O bus; The jumping pads of the third row are respectively connected to the I / O pins in the backup memory IC; The CAS jumping pad unit is arranged in at least two rows of jumping pads and each row has a number of jumping pads equal to the number of CAS pins on the module I / O bus; In the CAS jumping pad unit, the jumping pads in the first row are connected together with the CAS pins in the backup memory IC; Wherein each of the jumping pads in the second row is connected with corresponding CAS pins in the module I / O bus. 9. The method of claim 8, wherein the shorted connections are implemented by mounting a set of zero-ohm resistors on the jumping pad pairs to be shorted. 10. The method of claim 8, wherein the shorted connections are implemented by mounting a set of jumpers to shorted pairs of jumping pads.

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